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Summary of Contents for Acromag AXM-VFX-EDK
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USER’S MANUAL ACROMAG INCORPORATED Tel: (248) 295-0310 30765 South Wixom Road Fax: (248) 624-9234 P.O. BOX 437 Wixom, MI 48393-7037 U.S.A. solutions@acromag.com Copyright 2009, Acromag, Inc., Printed in the USA. 8500-828-B09G006 Data and specifications are subject to change without notice.
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It is important that you perform satisfactory overall system design and it is agreed between you and Acromag, that this is your responsibility. 1.0 General Information KEY FEATURES…………...… … …… .… ……… … ..
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AXM-VFX-EDK User’s Manual Mezzanine Board ___________________________________________________________________ TABLE OF 6.0 SPECIFICATIONS CONTENTS PHYSICAL..............ENVIRONMENTAL..…….…………………………….. LVTTL INPUT/OUTPUT..........DRAWINGS 4502-055 AXM MECHANICAL ASSEMBLY..... 4502-107 VFX EDK I/O LOCATION DRAWING..Trademarks are the property of their respective owners. ________________________________________________________________________ Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
AXM-VFX-EDK User’s Manual Mezzanine Board __________________________________________________________________ 1.0 GENERAL The AXM-VFX-EDK board (sold with the PMC-VFX base boards’ Engineering Design Kit) provides the standard Xilinx JTAG header, two INFORMATION RS232 terminal connections, as well as direct connections to the Xilinx FPGA. These general purpose LVTTL (Low Voltage TTL) I/O points allow the user to emulate AXM-D modules while using ChipScope®.
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SOFTWARE AXM-VFX-EDK. However, the AXM-VFX-EDK module can be accessed via the control software for the base PMC module. The AXM-VFX-EDK can be used withthe following operating systems: Windows® DLL, VxWorks®, and QNX®. Refer to the PMC base board’s manual for further information.
Acromag PMC-VFX module. The default configuration of the Configuration control register bits at power-up is described in section 3. The AXM-VFX-EDK board has four front I/O connectors. The first is a Front Panel Field I/O double row 14-pin 2mm header (male) for JTAG programming. This is the Connector standard Xilinx JTAG Header.
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AXM-VFX-EDK User’s Manual Mezzanine Board ___________________________________________________________________ AXM-VFX-EDK The AXM-VFX-EDK has a standard 34 pin double row 0.1” header for front I/O. The I/O are LVTTL/CMOS compatible. These pin connections Front I/O can emulate the 30 differential channels on the AXM-D02 and AXM-D04 models and the 22 differential channels on the AXM-D03 model using LVTTL signaling.
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I/O grounds. As such, the field I/O connections are not Considerations isolated from the system. Care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections. __________________________________________________________________________ Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
8027 Not Used 8024 mapping. 802B Not Used 8028 4. The board will return 0 for all addresses that are "Not 802F 802C ↓ Used". ↓ Reserved for base PMC Module 1FFFFF 1FFFFC ________________________________________________________________________ Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
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2. All other 3 bit values are reserved for future use. 3. Bit function is defined by the base PMC Module. This register can be written with either 8-bit, 16-bit, or 32-bit data transfers. __________________________________________________________________________ Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
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INPUT/OUTPUT (PCIBAR2 + 8004H) REGISTERS The AXM-VFX-EDK LVTTL channels may be individually accessed via this register at the carrier PCIBAR2 + 8004H. This includes all 30 general purpose LVTTL channels on the AXM-VFX-EDK. Each channel is controlled by its corresponding data bit, as shown in the register mapping table below.
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Reading or writing to this register is possible via 32-bit, 16-bit or 8-bit data transfers. Data-bits 30 and 31 are not used and will return 0 when read. __________________________________________________________________________ Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
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The data direction (input or output) of the digital channels is selected via this register at the carrier PCIBAR2 + 8010H. This includes twelve auxiliary LVTTL I/O on the AXM-VFX-EDK module. The direction of each channel is controlled by its corresponding data bit. The register mapping is the same as the Digital I/O Register.
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Interrupt Polarity Register. Channel read or write operations use 8-bit, 16-bit, or 32-bit data transfers. Note that no interrupts will occur unless they are enabled by the Interrupt Enable Register. __________________________________________________________________________ Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
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“0”. All bits are set to “0” following a reset, which means that the inputs will cause interrupts when they are logic low (provided they are enabled for interrupt on level). ________________________________________________________________________ Acromag, Inc. Tel:248-295-0310 Fax:248-624-9234 Email:solutions@acromag.com http://www.acromag.com...
I/O that can be found on the AXM-D series modules. Therefore the same registers can be used to simulate the Field I/O on the AXM-VFX-EDK. The 30 general purpose I/O map to the 30 differential I/O on the AXM-D02, the 22 differential I/O on the AXM-D03, and 30 LVDS I/O on the AXM-D04.
REPAIR repair. It is highly recommended that a non-functioning board be returned to Acromag for repair. The board can be easily damaged unless special SMT repair and service tools are used. Further, Acromag has automated test equipment that thoroughly checks the performance of each board. When a board is first produced and when any repair is made, it is tested, placed in a burn-in room at elevated temperature, and retested before shipment.
1.62 mm (0.064 in) AXM-VFX-EDK: 1.44oz (0.0408Kg) Unit Weight (Including all mounting hardware) Connectors • AXM-VFX-EDK Front Field I/O: 14-pin, 2mm double row male header (standard Xilinx JTAG header). 34-pin, 0.1” double row header. Power Requirements 3.3V (±5%) VFX-EDK 30mA 70mA Table 6.1: Power...
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B equipment. Shielded cable with I/O connections in shielded enclosure are required to meet compliance. Mean Time Between Failure: Contact the Factory. Reliability Prediction Channel Configuration: 42 Channels (AXM-VFX-EDK) Bi-directional LVTTL signals are independently direction controlled. LVTTL I/O Reset/Power Up Condition: All Digital Channels Default to Input.
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FLAT HEAD 2-56 OPTIONAL FLAT HEAD 2-56 NYLON SCREWS (x2) NYLON SCREWS (x2) 1. INSERT CMC BEZEL OVER AXM MODULE (A). USE TWO BEZEL SCREWS TO SECURE IF NECESSARY. THE PORTION OF THE AXM MODULE COVERED BY THE CMC BEZEL IS OUTLINED. 2.
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