Atmel AT43USB320A Manual

Full-speed usb microcontroller with an embedded hub

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Features

•

AVR

8-bit RISC Microcontroller with 83 ns Instruction Cycle Time

•

USB Hub with One Attached and Four External Ports

•

USB Function with Two Programmable Endpoints

•

External Program Memory, 512-byte Data SRAM

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32 x 8 General Purpose Working Registers

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32 Programmable I/O Port Pins

•

Programmable Serial UART

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Master/Slave SPI Serial Interface

•

One 8-bit Timer/Counter with Separate Pre-scaler

•

One 16-bit Timer/Counter with Separate Pre-scaler and Two PWMs

•

External and Internal Interrupt Sources

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Programmable Watchdog Timer

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6 MHz Oscillator with On-chip PLL

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5V Operation with On-chip 3.3V Power Supply

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100-lead LQFP Package

Description

The Atmel AT43USB320A is an 8-bit microcontroller based on the AVR RISC architec-

ture. By executing powerful instructions in a single clock cycle, the AT43USB320A

achieves throughputs approaching 12 MIPS. The AVR core combines a rich instruc-

tion set with 32 general-purpose working registers. All 32 registers are directly

connected to the ALU allowing two independent registers to be accessed in one single

instruction executed in one clock cycle. The resulting architecture is more code effi-

cient while achieving throughputs up to ten times faster than conventional CISC

microcontrollers.

The AT43USB320A features an on-chip 512-byte of data memory. It is supported by a

standard set of peripherals such as timer/counter modules, watchdog timer and inter-

n al an d ext er n al int er r u p t s ou r ce s. Th e m ajo r p e r iph e ra l in clu d ed in th e

AT43USB320A is the USB Hub with an embedded function for use in peripherals such

as monitor with remote control as shown in Figure 1.

Note:

There are two versions of the AT43USB320A. They are indicated by the internal part

numbers 55618D and 55618E. The only difference between the two versions is in the

polarity of the SUSPEND pin. The 55618D SUSPEND pin is active low, while the

55618E SUSPEND pin is active high.

Full-speed USB

Microcontroller

with an

Embedded Hub

AT43USB320A

Rev. 1443D–USB–12/03

Table of Contents

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Summary of Contents for Atmel AT43USB320A

Page 1: Table Of Features
CISC microcontrollers. The AT43USB320A features an on-chip 512-byte of data memory. It is supported by a standard set of peripherals such as timer/counter modules, watchdog timer and inter- n al an d ext er n al int er r u p t s ou r ce s. Th e m ajo r p e r iph e ra l in clu d ed in th e AT43USB320A is the USB Hub with an embedded function for use in peripherals such as monitor with remote control as shown in Figure 1.
Page 2: Hub/Monitor/Ir Chip Application
Hub/Monitor/IR Chip Application Figure 1. Application Example MONITOR µC I C /UART HUB/MONITOR/IR XCVR XCVR CHIP REMOTE UPSTREAM UNIT PORT DOWNSTREAM PORTS TO USB HOST TO USB DEVICES Pin Configurations 100-lead LQFP AT43USB320A 1443D–USB–12/03...
Page 3: Pin Assignment
AT43USB320A Pin Assignment Type: I = Input O = Output B = Bi-directional V = Power Supply, Ground Pin Number Signal Type Pin Number Signal Type CEXT1 SUSPEND 6/12N XTAL1 XTAL2 TESTN – – – – 1443D–USB–12/03...
Page 4 Pin Number Signal Type Pin Number Signal Type CEXT2 – – AT43USB320A 1443D–USB–12/03...
Page 5: Signal Description
Test Pin – This pin should be tied to ground. SUSPEND Output Suspend – This pin is asserted when the AT43USB320A enters the Suspend status. In the 55618D, it is active low and in the 55618E and later versions, it is active high.
Page 6 Figure 2. The AT43USB320A Enhanced RISC Architecture External Program Status and Interrupt Program Counter Control Unit Memory 8-bit Timer/Counter 32 x 8 Instruction General-purpose Register Registers 16-bit Timer/Counter Instruction Decoder Watchdog Timer 512 x 8 Control SRAM Lines SPI Unit...
Page 7: Architectural Overview
Family. The registers for managing the USB operations are mapped into its SRAM space. The I/O section on page 16 summarizes the available I/O registers. The “AVR Register Set” on page 36 covers the AVR registers. Please refer to the Atmel AVR manual for more information.
Page 8: The General-Purpose Register File
32 locations of the user Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-registers can be set to index any register in the file. AT43USB320A 1443D–USB–12/03...
Page 9: Y- And Z- Registers
Program Memory The AT43USB320A operates from an external program memory. Since all instructions are 16- or 32-bit words, the program memory is organized as X16. The AT43USB320A Program Counter (PC) is 16 bits wide, thus addressing the 64K program memory addresses.
Page 10: Sram Data Memory
SRAM Data Table 3 summarizes how the AT43USB320A SRAM Memory is organized. The lower 608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. Memory The first 96 locations address the Register File + I/O Memory, and the next 512 locations address the internal data SRAM.
Page 11 AT43USB320A Table 2. SRAM Organization Register File Data Address Space $0000 $0001 $001E $001F I/O Registers $0020 $0021 $005E $005F Internal SRAM $0060 $0061 $025E $045F USB Registers $1F00 $1FFE $1FFF 1443D–USB–12/03...
Page 12 Hub Port 5 Status Register $1FBB HPSTAT4 Hub Port 4 Status Register $1FBA HPSTAT3 Hub Port 3 Status Register $1FB9 HPSTAT2 Hub Port 2 Status Register $1FB8 HPSTAT1 Hub Port 1 Status Register $1FB4 HPSCR5 Hub Port 5 Status Change Register AT43USB320A 1443D–USB–12/03...
Page 13 AT43USB320A Table 3. USB Hub and Function Registers (Continued) Address Name Function $1FB3 HPSCR4 Hub Port 4 Status Change Register $1FB2 HPSCR3 Hub Port 3 Status Change Register $1FB1 HPSCR2 Hub Port 2 Status Change Register $1FB0 HPSCR1 Hub Port 1 Status Change Register...
Page 14 – DPSTATE DMSTATE PSTATE2 $1FA9 – – – – – – DPSTATE DMSTATE PSTATE1 $1FA8 – – – – – – DPSTATE DMSTATE HCAR0 $1FA7 CTL DIR DATA END FORCE STALL TX PACKET READY STALL_SENT-ACK RX_SETUP_ACK RX_OUT_PACKET_ACK TX_COMPLETE-ACK AT43USB320A 1443D–USB–12/03...
Page 15 AT43USB320A Table 4. USB Hub and Function Registers (Continued) Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FCAR0 $1FA5 CTL DIR DATA END FORCE STALL TX PACKET READY STALL_SENT-ACK RX_SETUP_ACK...
Page 16: I/O Memory
I/O Memory The I/O space definition of the AT43USB320A is shown in the following table: Table 5. I/O Memory Space I/O (SRAM) Address Name Function $3F ($5F) SREG Status Register $3E ($5E) Stack Pointer High $3D ($5D) Stack Pointer Low...
Page 17: Usb Hub
Port 5. Ports 1 through 4 are available as external ports. The actual number of ports used is strictly defined by the firmware of the AT43USB320A and can vary from 0 to 4. Because the exact configuration is defined by firmware, ports 1 to 4 may even function as per- manently attached ports as long as the Hub Descriptor identifies them as such.
Page 18 Figure 3. USB Hardware Port 1 XCVR Port 0 XCVR Port 2 XCVR Port 3 Hub Repeater XCVR Port 4 XCVR Serial Interface Engine Port 5 Function Interface Interface Unit Unit Data Address Control AVR Microcontroller AT43USB320A 1443D–USB–12/03...
Page 19: Functional Description
CEXT1 and 2 pins. I/O Pin The I/O pins of the AT43USB320A should not be directly connected to voltages less than V or more than the voltage at the CEXT pins. If it is necessary to violate this rule, insert a series...
Page 20: Reset And Interrupt Handling
0.22 UF 0.01 UF Reset and The AT43USB320A provides 22 different interrupt sources with 13 separate reset vectors, each with a separate program vector in the program memory space. Eleven of the interrupt Interrupt Handling sources share 2 interrupt reset vectors. These 11 are the USB related interrupts. All interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt.
Page 21 AT43USB320A The most typical and general program setup for the Reset and Interrupt Vector Addresses are: Address Labels Code Comments $000 RESET ; Reset Handler $004 EXT_INT1 ; IRQ1 Handler $00E TIM0_OVF ; Timer0 Overflow Handler $018 USB_HW ; USB Handler...
Page 22: Reset Sources
FRMWUP INT0, SUSP/RSM GLB SUSP RESET Reset Sources The AT43USB320A has four sources of reset: • Power-on Reset – The MCU is reset when the supply voltage is below the power-on reset threshold. • External Reset – The MCU is reset when a low level is present on the RESET pin for more than 50 ns.
Page 23: Power-On Reset
AT43USB320A Figure 6. Reset Logic USB Reset POR Ckt Reset Ckt RSTN Cntr Reset Watchdog Timer FSTRT System Clock 14-bit Cntr Divider Table 7. Number of Watchdog Oscillator Cycles FSTRT Time-out at V = 5V Number of WDT cycles Programmed 1.1 ms...
Page 24: External Reset
INTERNAL RESET Non-USB Related The AT43USB320A has two non-USB 8-bit Interrupt Mask control registers; GIMSK (General Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). Interrupt Handling When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled.
Page 25 AT43USB320A If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. If one or more interrupt conditions occur when the global interrupt enable bit is cleared (zero), the corresponding interrupt flag(s) will be set and remembered until the global interrupt enable bit is set (one), and will be executed by order of priority.
Page 26: General Interrupt Mask Register - Gimsk
Request 0 is executed from program memory address $002. See also “External Interrupts” on page 29. • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read as zero. General Interrupt Flag Register – GIFR $3A ($5A)
Page 27 TIFR. • Bit 4 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero. • Bit 3 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled.
Page 28: Timer/Counter Interrupt Flag Register - Tifr
• Bit 4 – Res: Reserved Bit This bit is a reserved bit in the AT43USB320A and always reads zero. • Bit 3 – ICF1: - Input Capture Flag 1 The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1.
Page 29: External Interrupts
AT43USB320A External Interrupts The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if enabled, the INT0/INT1 interrupt will trigger even if the INT0/INT1 pins are configured as outputs. This fea- ture provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level.
Page 30: Mcu Control Register - Mcucr
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (1), Power Down mode is selected as sleep mode. The AT43USB320A does not support the Idle Mode and SM should always be set to one when entering the Sleep Mode.
Page 31: Usb Interrupt Sources
AT43USB320A USB Interrupt The USB interrupts are described below. Sources Table 10. USB Interrupt Sources Interrupt Description SOF Received Whenever USB hardware decodes a valid Start of Frame. The frame number is stored in the two Frame Number Registers. EOF2 Activated whenever the hub's frame timer reaches its EOF2 time point.
Page 32: Usb Endpoint Interrupt Sources
1. RX OUT Packet is set (control and OUT endpoints) 2. TX Packet Ready is cleared AND TX Complete is set (control and IN endpoints) 3. RX SETUP is set (control endpoints only) 4. TX Complete is set AT43USB320A 1443D–USB–12/03...
Page 33 AT43USB320A USB Interrupt Acknowledge Register – UIAR $1FF5 SOF INTACK EOF2 INTACK – – HEP0 INTACK FEP2 IMSK FEP1 INTACK FEP0 INTACK UIAR Read/Write Initial Value • Bit 7 – SOF INTACK: Start of Frame Interrupt Acknowledge The microcontroller firmware writes a 1 to this bit to clear the SOF INT bit.
Page 34 Port 1. An interrupt is generated if the RSM IE bit of the SPRSIE register is set. • Bit 0 – GLB SUSP: Global Suspend The USB hardware sets this bit when a USB global suspend signaling is detected. An interrupt is generated if the GLBSUSP IE bit of the SPRSIE register is set. AT43USB320A 1443D–USB–12/03...
Page 35 AT43USB320A Suspend/Resume Interrupt Enable Register – SPRSIE $1FF9 – – – – – FRWUP GLB SUSP SPRSIE Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved and are always read as zeros. • Bit 3 – BUS INT EN: USB Reset Interrupt Enable When the BUS INT EN bit is set, the USB and microcontroller resets are separated.
Page 36: Avr Register Set
The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. AT43USB320A 1443D–USB–12/03...
Page 37: Sleep Modes
AT43USB320A Stack Pointer Register – SP $3E ($5E) $3D ($5D) Read/Write Initial Value The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled.
Page 38: Timer/Counters
Timer/Counters The AT43USB320A provides two general-purpose Timer/Counters - one 8-bit T/C and one 16- bit T/C. The Timer/Counters have individual prescaling selection from the same 10-bit prescal- ing timer. Both Timer/Counters can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting.
Page 39: 8-Bit Timer/Counter0
AT43USB320A 8-bit The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Timer/Counter0 Register (TCCR0). The overflow status flag is found in the Timer/Counter Interrupt Flag Regis- ter (TIFR).
Page 40: Timer/Counter0 Control Register - Tccr0
Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read as zero. • Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, bit 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0.
Page 41: 16-Bit Timer/Counter1
AT43USB320A 16-bit Timer/Counter1 Figure 11. Timer/Counter1 Block Diagram T/C1 T/C1 COMPARE T/C1INPUT T/C1 COMPARE OVERFLOW IRQ MATCHB IRQ CAPTURE IRQ MATCHA IRQ TIMER INT. MASK T/C1 CONTROL T/C1 CONTROL TIMER INT. FLAG REGISTER (TIMSK) REGISTER A (TCCR1A) REGISTER B (TCCR1B)
Page 42: 16-Bit Timer/Counter1 Operation
If the noise canceler function is enabled, the actual trigger condition for the capture event is monitored over 4 samples, and all 4 must be equal to activate the capture flag. Figure 12. ICP Pin Schematic Diagram NOISE CANCELER EDGE SELECT ICF1 ICNC1 ICES1 ACIC ACIC: COMPARATOR IC ENABLE ACC0: COMPARATOR OUTPUT AT43USB320A 1443D–USB–12/03...
Page 43 • Bits 3..2 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read zero. • Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select Bits 1 and 0 These bits select PWM operation of Timer/Counter1 as specified in Table 14.
Page 44: Timer/Counter1 Control Register B - Tccr1B
Timer/Counter1 contents are transferred to the ICR1 on the rising edge of the ICP. • Bits 5, 4 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read zero. • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match.
Page 45 AT43USB320A Table 15. Clock 1 Prescale Select (Continued) CS12 CS11 CS10 Description CK/1024 External Pin T1, falling edge External Pin T1, rising edge The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the 12 MHz system clock. If the external pin modes are used for Timer/Counter1, transitions on PB1/(T1) will clock the counter even if the pin is configured as an output.
Page 46: Timer/Counter1 - Tcnt1H And Tcnt1L
If Time r/Cou nte r1 is written to an d a clo ck so urce is selecte d, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. AT43USB320A 1443D–USB–12/03...
Page 47 AT43USB320A Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL $2B ($4B) – – – – – – – OCR1AH $2A ($4A) – – – – – – – OCR1AL Read/Write Initial Value Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL $29 ($49) –...
Page 48: Timer/Counter1 Input Capture Register - Icr1H And Icr1L
COM1B1/COM1B0 bits in the Timer/Counter1 Control Register TCCR1A. Refer to Table 17 for details. Table 16. Timer TOP Values and PWM Frequency PWM Resolution Timer TOP value Frequency 8-bit $00FF (255) /510 TCK1 9-bit $01FF (511) /1022 TCK1 10-bit $03FF(1023) /2046 TCK1 AT43USB320A 1443D–USB–12/03...
Page 49 AT43USB320A Table 17. Compare1 Mode Select in PWM Mode COM1X1 COM1X0 Effect on OCX1 Not connected Not connected Cleared on compare match, up-counting. Set on compare match, down-counting (non-inverted PWM). Cleared on compare match, down-counting. Set on compare match, up-counting (inverted PWM).
Page 50: Watchdog Timer
Table 19 for a detailed description. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT43USB320A resets and executes from the reset vector.
Page 51 Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and will always read as zero. • Bit 4 – WDTOE: Watch Dog Turn-Off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled.
Page 52: Serial Peripheral Interface (Spi)
Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT43USB320A a nd peripheral devices or betwee n several AVR d evice s. The Interface (SPI) AT43USB320A SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer •...
Page 53 AT43USB320A The interconnection between master and slave CPUs with SPI is shown in Figure 16. The PB7(SCK) pin is the clock output in the master mode and is the clock input in the slave mode. Writing to the SPI data register of the master CPU starts the SPI clock generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI) pin of the slave CPU.
Page 54 Figure 17. SPI Transfer Format with CPHA = 0 and DORD = 0 SCK Cycle # (For Reference) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (From Master) MISO (From Slave) SS (To Slave) Note: * Not defined but normally LSB of character just received. AT43USB320A 1443D–USB–12/03...
Page 55 AT43USB320A Figure 18. SPI Transfer Format with CPHA = 1 and DORD = 0 SCK Cycle # (For Reference) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (From Master) MISO (From Slave) SS (To Slave) Note: * Not defined, but normally LSB of previously transmitted character.
Page 56 The relationship between SCK and the Oscillator Clock frequency is shown in the following table: Table 21. Relationship Between SCK and the Oscillator Frequency SPR1 SPR0 SCK Frequency 3 MHz 750 kHz 187.5 kHz 93.75 kHz AT43USB320A 1443D–USB–12/03...
Page 57: Spi Status Register - Spsr
WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. • Bit 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and will always read as zero. SPI Data Register – SPDR $0F ($2F) –...
Page 58: Data Transmission
(zero), the PD1 pin can be used for general I/O. When TXEN is set, the UART Transmitter will be connected to PD1, which is forced to be an output pin regardless of the setting of the DDD1 bit in DDRD. AT43USB320A 1443D–USB–12/03...
Page 59: Data Reception
AT43USB320A Figure 19. UART Transmitter Data Reception Figure 20 shows a block diagram of the UART Receiver. The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, one single sample of logical "0" will be interpreted as the fall- ing edge of a start bit and the start bit detection sequence is initiated.
Page 60 This bit must be set to the wanted value before a transmission is initiated by writing to the UDR register. The ninth data bit received is the RXB8 bit in the UCR register. Figure 20. UART Receiver AT43USB320A 1443D–USB–12/03...
Page 61: Uart Control
AT43USB320A Figure 21. Sampling Received Data UART Control UART I/O Data Register – $0D ($2C) – – – – – – Read/Write Initial Value The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. When reading from UDR, the UART Receive Data register is read.
Page 62 The OR bit is cleared (zero) when data is received and transferred to UDR. • Bits 2...0 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and will always read as zero. UART Control Register –...
Page 63: Baud Rate Generator
AT43USB320A • Bit 2 – CHR9: 9-bit Characters When this bit is set (one) transmitted and received characters are 9 bits long plus start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in UCR, respec- tively.
Page 64: I/O-Ports
MOS pull-up resistor is activated. To switch the pull-up resistor off, the PORTAn has to be cleared (zero) or the pin has to configured as an output pin. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not active. AT43USB320A 1443D–USB–12/03...
Page 65: Port B
AT43USB320A Table 23. DDAn Effects on Port A Pins DDAn PORTAn Comment Input Tri-state (Hi-Z) Input Tri-state (Hi-Z) Output Push-Pull Zero Output Output Push-Pull One Output Note: n: 7,6...0, pin number. Port B Port B is an 8-bit bi-directional I/O port. The Port B output buffers can sink or source 4 mA.
Page 66: Port B Data Register - Portb
Table 25. DDBn Effects on Port B Pins DDBn PORTBn Comment Input Tri-state (Hi-Z) Input Tri-state (Hi-Z) Output Push-Pull Zero Output Output Push-Pull One Output Note: n: 7, 6...0, pin number. AT43USB320A 1443D–USB–12/03...
Page 67: Portc
AT43USB320A Port C Port C is an 8-bit bi-directional I/O port with push-pull outputs. The Port C output buffers can sink 4 mA Three I/O memory address locations are allocated for the Port C, one each for the Data Regis-...
Page 68: Port D
The Port D Input Pins address (PIND) is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. AT43USB320A 1443D–USB–12/03...
Page 69: Programming The Usb Module
CPU. It initiates interrupts and acts upon commands sent by the firmware. The USB function hardware of the AT43USB320A makes the physical interface and the proto- col layer transparent to the user. To start the process, the firmware must first enable the endpoints and which place them in receive mode by default.
Page 70 IN(1) IN(0) … IN(0/1) OUT(1) Read DATA0 DATA1 DATA0 DATA0/1 DATA1(0) Setup Status Stage Stage Legend: No-data DATAn Data packet with PID’s SETUP(0) IN(1) Control data toggle bit equal to n DATA0 DATA1(0) DATA1(0) Zero length DATA1 packet AT43USB320A 1443D–USB–12/03...
Page 71 AT43USB320A The following state diagram shows how the various state transitions are triggered. Additional decision making may take place within the response states to determine the next expected state. Unmarked arcs represent transitions that trigger immediately following completion of the response state processing.
Page 72 The following information describes how the AT43USB320A’s USB hardware and firmware operates during a control transfer between the host and the hub’s or function’s control endpoint. Legend: DATA1/DATA0 = Data packet with DATA1 or DATA2 PID DATA1(0) = Zero length DATA1 packet Idle State This is the default state from power-up.
Page 73 AT43USB320A No-data Status The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero Response State length DATA1 packet until receiving an ACK from the host, then asserts a TX_COMPLETE interrupt. Hardware Firmware 1. IN token from Host 2.
Page 74 6. Read CSR0 7. Read FIFO 8. Clear RX OUT If last data packet, set Force STALL, set DATA END. 9. Set UIAR[EP0 INTACK] to clear the interrupt source Repeat steps 1 through 9 until last DATA PACKET: AT43USB320A 1443D–USB–12/03...
Page 75 AT43USB320A Control Write Status The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero Response State length DATA1 packet, retrying until it receives an ACK back from the Host. The FIU then asserts a TX_COMPLETE interrupt.
Page 76 FIU places the incoming data into the FIFO, issues an ACK to the host, and asserts an RX_OUT interrupt. 1. Read UISR 2. Read FCSR1/2 3. Read FIFO 4. Clear RX_OUT If more data: Wait for RX_OUT interrupt If no more data: set DATA END 5. Set UIAR[FEP1/2 INTACK] to clear the interrupt source AT43USB320A 1443D–USB–12/03...
Page 77: Usb Registers
AT43USB320A USB Registers The following sections describe the registers of the AT43USB320A’s USB hub and function units. Reading a bit for which the microcontroller does not have read access will yield a zero value result. Writing to a bit for which the microcontroller does not have write access has no effect.
Page 78: Endpoint Registers
1 = Enable endpoint • Bit 6..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 3 – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances.
Page 79 1 = Enable endpoint • Bit 6..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 3 – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances.
Page 80 Read/Write Initial Value • Bit 7, 6 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 5 – P5 SC: Port 5 Status Change • Bit 4 – P4 SC: Port 4Status Change •...
Page 81 BYTCT4 BYTCT3 BYTCT2 BYTCT1 BYTCT0 FBYTE_CNT2 Read/Write Initial Value • Bit 7..5 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 4..0 – BYTCT4..0: Byte Count – Length of Endpoint Data Packet 1443D–USB–12/03...
Page 82 Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[Endpoint] request.
Page 83 AT43USB320A Hub Endpoint 0 Control and Acknowledge Register – HCAR0 Function Endpoint 0 Control and Acknowledge Register – FCAR0 STALL_ RX_OUT_ Hub EP0 DATA FORCE PACKET SENT_ SETUP_ PACKET_ COMPLETE_ HCAR0 $1FA7 STALL READY STALL_ RX_OUT_ Function DATA FORCE PACKET...
Page 84 Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[Endpoint] request.
Page 85 Initial Value • Bit 7 – Reserved This bit is reserved in the AT43USB320A and will read as zero. • Bit 6 – DATA END When set to 1 by firmware, this bit indicate that the microcontroller has either placed the last data packet in FIFO, or that the microcontroller has processed the last data packet it expects from the Host.
Page 86: Usb Hub
The first two tasks of the hub are similar to that of a USB function and are described in detail in the following section. The descriptions will cover the features of the AT43USB320A's hub and how to program it to make a USB-compliant hub.
Page 87 Initial Value • Bit 7...5 – Reserved Bits These bits are reserved in the AT43USB320A and will read as zeros. • Bit 4 – SUSP FLG: Suspend Flag This bit is set to 1 while the USB hardware is in the suspended state. This bit is a firmware read only bit.
Page 88 Hub Status Register In the AT43USB320A overcurrent detection and port power switch control output processing is done in firmware. The hardware is designed so that various types of hubs are possible just through firmware modifications. 1. Hub local power status, bits 0 and 2, are optional features and apply to hubs that report on a global basis.
Page 89 Initial Value • Bit 7 – Reserved This bits is reserved in the AT43USB320A and will read as zero. • Bit 6..4 – HPCON2..0: Hub Port Control Command These bits are written by firmware to control the port states upon receipt of a Host request.
Page 90 These bits define which port is being addressed for the command defined by bits [2:0]. Bit2 Bit1 Bit0 Port addresses Port 5 Port 4 Port 3 Port 2 Port 1 AT43USB320A 1443D–USB–12/03...
Page 91 AT43USB320A Selective Suspend The host can selectively suspend and resume a port through the Set Port Feature and Resume (PORT_SUSPEND) and Clear Port Feature (PORT_SUSPEND). A port enters the suspend state after the microcontroller interprets the suspend request and sets the appropriate bits of the Hub Port Control Register, HPCON. From this point on he hub repeater hardware is responsible for proper actions in placing Ports [1:4] in the suspend mode.
Page 92 Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the AT43USB320A and will read as zero. • Bit 6 – LSP: Low-speed Device Attached 0 = Full-speed device attached to this port 1 = Slow-speed device attached to this port Set to 0 for Port 1 (full-speed only).
Page 93 GetBusState request. • Bit 7..2 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 1 – DPSTATE: DPlus State Value of DP at last EOF. Set and cleared by hardware at EOF2.
Page 94 USB hardware. Otherwise, the firmware should only clear these bits. • Bit 7..5 – Reserved These bits are reserved in the AT43USB320A and will read as zero. • Bit 4 – RSTSC: Port Reset Status Change 0 = No change...
Page 95 Port 5. Hardware sets this bit for Port 5 after a hub reset. Cleared by firmware via Host request ClearPortFeature(PORT_CONNECTION). Hub and Port Power For the utmost flexibility, the USB hardware of the AT43USB320A is designed to accommo- Management date hubs of various capacitance. Management of the downstream port power is also defined by the firmware: per port or global overcurrent sensing, individual or gang power switching.
Page 96: Suspend And Resume
PORT4_POWER PORT4_GND Suspend and The AT43USB320A enters suspend only when requested by the USB host through bus inac- tivity for at least 3 ms. The USB hardware would detect this request, sets the GLB_SUSP bit of Resume SPRSR, Suspend/Resume Register, and interrupts the microcontroller if the interrupt is enabled.
Page 97 AT43USB320A rupt to the microcontroller. The microcontroller starts executing where it left off and services the interrupt. As part of the ISR, the firmware clears the GLB SUSP bit. At completion of RESUME signaling, the USB hardware sets the Port Suspend Status Change bits of the Hub Port Status Change Registers.
Page 98 6. Restore GPIO states if required 7. Clear UOVCER bit 2 8. Enable peripheral activity Selective Suspend, Downstream Ports Hardware Firmware 1. Set or Clear Port Feature PORT_SUSPEND decoded 2. Write HPCON[2:0] and HPADD[2:0] bits 3. Suspend or resume port per command AT43USB320A 1443D–USB–12/03...
Page 99 AT43USB320A Selective Suspend, Embedded Function Hardware Firmware 1. Set Port Feature PORT_SUSPEND decoded 2. Disable Port 5’s endpoints 3. Set GPIO to low power state if required Selective Resume, Embedded Function Hardware Firmware 1. Clear Port Feature PORT_SUSPEND decoded 2. Clear Port 5 suspend status bit 3.
Page 100: Electrical Specification
The values shown in this table are valid for TA = 0°C to 85°C, VCC = 4.4 to 5.25V, unless oth- erwise noted. Table 30. Power Supply Symbol Parameter Condition Unit 5V Power Supply 5.25 5V Supply Current Suspended Device Current AT43USB320A 1443D–USB–12/03...
Page 101 AT43USB320A Table 31. USB Signals: DPx, DMx Symbol Parameter Condition Unit Input Level High (driven) Input Level High (floating) Input Level Low Differential Input Sensitivity DPx and DMx Differential Common Mode Range RL of 1.5 kΩ Static Output Low to 3.6V RL of 15 kΩ...
Page 102 Figure 23. Full-speed Load TxD+ TxD- = 50 pF Table 35. USB Driver Characteristics, Low-speed Operation Symbol Parameter Condition Unit Rise time CL = 200 - 600 pF Fall time CL = 200 - 600 pF TRFM TR/TF matching AT43USB320A 1443D–USB–12/03...
Page 103 AT43USB320A Figure 24. Low-speed Downstream Port Load TxD+ 3.6V 1.5 K Ohm TxD- = 200 pF to 600 pF Table 36. USB Source Timings, Full-speed Operation Symbol Parameter Condition Unit TDRATE Full Speed Data Rate Average Bit Rate 11.97 12.03...
Page 104 Crossover Point PERIOD Extended Differential Data Lines Diff. Data-to- Source EOP Width: FEOPT SE0 Skew LEOPT PERIOD DEOP Receiver EOP Width: FEOPR LEOPR Figure 27. Receiver Jitter Tolerance PERIOD Differential Data Lines Consecutive Transitions PERIOD Consecutive Transitions PERIOD AT43USB320A 1443D–USB–12/03...
Page 105 AT43USB320A Table 37. Hub Timings, Full-speed Operation Symbol Parameter Condition Unit THDD2 Hub Differential Data Delay without cable THDJ1 Hub Diff Driver Jitter to Next Transition for Paired THDJ2 Transitions TFSOP Data Bit Width Distortion after SOP TFEOPD Hub EOP Delay Relative...
Page 106 TURLK Time to detect a long K µs from upstream TURLSEO Time to detect a long SEO µs from upstream TURPSEO Duration of repeating SEO upstream bits TUDEOP Duration of sending SEO upstream after EOF1 bits AT43USB320A 1443D–USB–12/03...
Page 107 AT43USB320A Figure 28. Hub Differential Delay, Differential Jitter and SOP Distortion Upstream Crossover Downstream End of Point Port 50% Point of Cable Initial Swing Hub Delay Hub Delay Crossover Upstream Crossover Differential Downstream Point Upstream Port Point Data Lines HDD1 HDD2 A.
Page 108 Condition Unit Address to Output Delay CEN to Output Delay CEN to Output Float Output Hold from CEN or Address, whichever occurred first Figure 30. External Program Memory Read Timing Diagram ADDRESS ADDRESS VALID OUTPUT HIGHZ OUTPUT VALID AT43USB320A 1443D–USB–12/03...
Page 109: Ordering Information
AT43USB320A Ordering Information Ordering Code Package Operation Range AT43USB320A 100 LQFP Commercial (0°C to 70°C) 1443D–USB–12/03...
Page 110: Packaging Information
0.75 0.50 TYP 04/29/2002 TITLE DRAWING NO. REV. 2325 Orchard Parkway 100AA, 100-lead, 14 x 14 mm Body Size, 1.4 mm Body Thickness, 100AA San Jose, CA 95131 0.5 mm Lead Pitch, Low Profile Quad Flat Pack (LQFP) AT43USB320A 1443D–USB–12/03...
Page 111: Table Of Contents
Table of Contents Table of Features ....................1 Contents Description .................... 1 Hub/Monitor/IR Chip Application............2 Pin Configurations................2 Pin Assignment ................... 3 Signal Description ....................5 Architectural Overview................. 7 The General-purpose Register File ............. 8 X-, Y- and Z- Registers..................9 ALU –...
Page 112 8-bit Timer/Counter0................... 39 16-bit Timer/Counter1..................41 16-bit Timer/Counter1 Operation ................ 42 Watchdog Timer ....................50 Serial Peripheral Interface (SPI) ................. 52 UART....................57 Data Transmission................58 Data Reception..................59 UART Control ..................61 Baud Rate Generator................63 I/O-Ports....................64 Port A........................64 Port B........................
Page 113 No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems.