Nuvoton NuMicro ML51 Series Manuals

Manuals and User Guides for Nuvoton NuMicro ML51 Series. We have 2 Nuvoton NuMicro ML51 Series manuals available for free PDF download: Technical Reference Manual

Nuvoton NuMicro ML51 Series Technical Reference Manual (719 pages)

8-bit Microcontroller

Brand: Nuvoton | Category: Microcontrollers | Size: 7 MB

Table of Contents
2
General Description
11
Features
12
Part Information
17
ML51/ML54/ML56 Series Package Type
17
ML51/ML54/ML56 Series Selection Guide
18
ML51 Series
18
ML54 Series
21
ML56 Series
22
ML51/ML54/ML56 Series Selection Code
23
Pin Configuration
24
ML51/ML54/ML56 Series Pin Diagram
24
Figure 4.1-1 ML51SD1AE Pin Assignment
24
Figure 4.1-2 ML54SD1AE / ML56SD1AE Pin Assignment
25
Figure 4.1-3 ML51LD1AE Pin Assignment
26
Figure 4.1-4 ML54LD1AE / ML56LD1AE Pin Assignment
26
Figure 4.1-5 ML54MD1AE / ML56MD1AE Pin Assignment
27
Figure 4.1-6 ML51TD1AE / ML51TC0AE / ML51TB9AE Pin Assignment
27
Figure 4.1-7 ML51PC0AE / ML51PB9AE Pin Assignment
28
Figure 4.1-8 ML51EC0AE / ML51EB9AE Pin Assignment
28
Figure 4.1-9 ML51UC0AE / ML51UB9AE Pin Assignment
29
Figure 4.1-10 ML51FB9AE Pin Assignment
29
Figure 4.1-11 ML51OB9AE Pin Assignment
30
Figure 4.1-12 ML51XB9AE Pin Assignment
30
Figure 4.1-13 ML51DB9AE Pin Assignment
31
Figure 4.1-14 ML51BB9AE Pin Assignment
31
ML51/ML54/ML56 Series Multi Function Pin Diagram
32
Figure 4.1-15 ML51SD1AE Multi-Function Pin Assignment
32
Figure 4.1-16 ML54SD1AE Multi-Function Pin Assignment
35
Figure 4.1-17 ML56SD1AE Multi-Function Pin Assignment
38
Figure 4.1-18 ML51LD1AE Multi-Function Pin Assignment
41
Figure 4.1-19 ML54LD1AE Multi-Function Pin Assignment
44
Figure 4.1-20 ML56LD1AE Multi-Function Pin Assignment
47
Figure 4.1-21 ML54MD1AE Multi-Function Pin Assignment
50
Figure 4.1-22 ML56MD1AE Multi-Function Pin Assignment
53
Figure 4.1-23 ML51TD1AE Multi-Function Pin Assignment
56
Figure 4.1-24 ML51TC0AE / ML51TB9AE Multi-Function Pin Assignment
58
Figure 4.1-25 ML51PC0AE / ML51PB9AE Multi-Function Pin Assignment
60
Figure 4.1-26 ML51EC0AE / ML51EB9AE Multi-Function Pin Assignment
62
Figure 4.1-27 ML51UC0AE / ML51UB9AE Multi Function Pin Assignment
64
Figure 4.1-28 ML51FB9AE Multi Function Pin Assignment
66
Figure 4.1-29 ML51OB9AE Multi Function Pin Assignment
67
Figure 4.1-30 ML51XB9AE Multi Function Pin Assignment
68
Figure 4.1-31 ML51DB9AE Multi Function Pin Assignment
70
Figure 4.1-32 ML51BB9AE Pin Assignment
71
Pin Description
72
ML51/ML54/ML56 Series Pin Mapping
72
ML51/ML54/ML56 Series Pin Functional Description
74
Block Diagram
79
ML51/ML54/ML56 Series Full Function Block
79
Figure 5.1-1 Functional Block Diagram
79
Functional Description
80
Memory Organization
80
Program Memory
80
Figure 6.1-1 ML51/ML54/ML56 Series Program Memory Map
81
Security Protection Memory (SPROM)
82
Figure 6.1-2 SPROM Memory Mapping and SPROM Security Mode
82
96-Bit Unique Code (UID)
83
Data Flash
83
Data Memory
84
Figure 6.1-3 Data Memory Map
84
Figure 6.1-4 Internal 256 Bytes RAM Addressing
85
Config Bytes
86
Figure 6.1-5 CONFIG0 any Reset Reloading
87
Figure 6.1-6 CONFIG2 Power-On Reset Reloading
89
Special Function Register (SFR)
91
Table 6.1-1Special Function Register (SFR) Memory Map
99
Table 6.1-2 SFR Definitions and Reset Values
111
System Manager
292
Clock System
292
Figure 6.2-1 Clock System Block Diagram
292
Power Management
301
Table 6.2-1 Power Mode Table
301
Table 6.2-2 Entry Setting of Power-Down Mode
301
Power Monitering and Reset
304
Figure 6.2-2 Brown-Out Detection Block Diagram
306
Table 6.2-3 BOF Reset Value
306
Figure 6.2-3 Boot Selecting Diagram
318
Interrupt System
321
Table 6.2-4 Interrupt Vectors
321
Table 6.2-5 Interrupt Priority Level Setting
328
Table 6.2-6 Characteristics of each Interrupt Source
330
Flash Memory Control
341
In-Application-Programming (IAP)
341
Figure 6.3-1 IAP Modes and Command Codes
350
Figure 6.3-2. CRC-8 Block Diagram
351
In-Circuit-Programming (ICP)
357
On-Chip-Debugger (ICE)
358
GPIO Port Structure and Operation
361
GPIO Mode
361
Table 6.4-1 Configuration for Different I/O Modes
361
Figure 6.4-1 Quasi-Bidirectional Mode Structure
362
Figure 6.4-2 Push-Pull Mode Structure
362
Figure 6.4-3 Input-Only Mode Structure
363
Figure 6.4-4 Open-Drain Mode Structure
363
External Interrupt Pins
380
Table 6.4-2 External Interrupt Pin Multi-Function Pin List
380
Pin Interrupt (PIT)
382
Figure 6.4-5 Pin Interface Block Diagram
382
Timer
389
Overview
389
Timer/Counter 0 and 1
389
Figure 6.5-1 Timer/Counters 0 and 1 in Mode 0
390
Figure 6.5-2 Timer/Counters 0 and 1 in Mode 1
390
Figure 6.5-3 Timer/Counters 0 and 1 in Mode 2
391
Figure 6.5-4 Timer/Counter 0 in Mode 3
391
Timer 2 and Input Capture
401
Figure 6.5-5 Timer 2 Block Diagram
401
Figure 6.5-6 Timer 2 Auto-Reload Mode and Input Capture Module Functional Block Diagram
402
Figure 6.5-7 Timer 2 Compare Mode and Input Capture Module Functional Block Diagram
403
Timer 3
410
Figure 6.5-8 Timer 3 Block Diagram
410
Watchdog Timer (WDT)
414
Time-Out Reset Timer
414
Table 6.6-1 Watchdog Timer-Out Interval under Different Pre-Scalars
414
General Purpose Timer
415
Figure 6.6-1 WDT as a Time-Out Reset Timer
415
Figure 6.6-2 Watchdog Timer Block Diagram
415
Register Description
416
Typical Structure of WDT Service Routine
419
Self Wake-Up Timer (WKT)
421
Overview
421
Block Diagram
421
Figure 6.7-1 Self Wake-Up Timer Block Diagram
421
Control Register
422
Pulse Width Modulated (PWM)
428
Overview
428
Features
428
Block Diagram
429
Figure 6.8-1 PWM0 Block Diagram
429
Figure 6.8-2 PWM1/ PWM2 / PWM3 Block Diagram
430
Functional Description
431
Figure 6.8-3 PWM0 and Fault Brake Output Control Block Diagram
432
Figure 6.8-4 PWM1/2/3 Control Block Diagram
433
Figure 6.8-5 PWM Edge-Aligned Type Waveform
444
Figure 6.8-6 PWM Center-Aligned Type Waveform
445
Figure 6.8-7 PWM Complementary Mode with Dead-Time Insertion
447
Figure 6.8-8 Fault Brake Function Block Diagram
453
PWM Interrupt
456
Figure 6.8-9 PWM Interrupt Type
458
Register Description
459
Serial Port (UART0 & UART1)
475
Overview
475
Features
475
Functional Description
476
Figure 6.9-1 Serial Port Mode 0 Timing Diagram
476
Figure 6.9-2 Serial Port Mode 1 Timing Diagram
477
Figure 6.9-3 Serial Port Mode 2 and 3 Timing Diagram
478
Table 6.9-1 Serial Port 0 Mode / Baud Rate Description
479
Table 6.9-2 Serial Port 1 Mode / Baud Rate Description
480
Register Description
486
Smart Card Interface (SC)
503
Overview
503
Features
503
Block Diagram
503
Figure 6.10-1 SC Controller Block Diagram
503
Operating Modes
504
Figure 6.10-2 SC Interface Connection
504
Table 6.10-1 SC Activation and Cold Reset Sequence
505
Table 6.10-2 SC Warm Reset Sequence
505
Smart Card Data Transfer
506
Figure 6.10-3 SC Data Character
506
Table 6.10-3 SC Deactivation Sequence
506
Figure 6.10-4 Initial Character TS
507
Figure 6.10-5 SC Error Signal
507
Figure 6.10-6 Transmit Direction Block Guard Time Operation
508
Figure 6.10-7 Receive Direction Block Guard Time Operation
508
Figure 6.10-8 Extra Guard Time Operation
508
Register Description
509
Serial Peripheral Interface (SPI)
522
Overview
522
Features
522
Block Diagram
523
Figure 6.11-1 SPI Block Diagram
523
Functional Description
524
Figure 6.11-2 SPI Multi-Master, Multi-Slave Interconnection
524
Figure 6.11-3 SPI Single-Master / Single-Slave Interconnection
525
Figure 6.11-4 SPI Clock Formats
526
Figure 6.11-5 SPI Clock and Data Format with CPHA = 0
527
Figure 6.11-6 SPI Clock and Data Format with CPHA = 1
527
Table 6.11-1 Slave Select Pin Configurations
528
Figure 6.11-7 SPI Overrun Waveform
529
Figure 6.11-8 SPI Interrupt Request
529
Register Description
530
Inter-Integrated Circuit (I 2 C)
536
Overview
536
Features
536
Functional Description
536
Figure 6.12-1 I 2 C Bus Interconnection
536
Figure 6.12-2 I C Bus Protocol
537
Figure 6.12-3 START, Repeated START, and STOP Conditions
537
Figure 6.12-4 Master Transmits Data to Slave by 7-Bit
538
Figure 6.12-5 Master Reads Data from Slave by 7-Bit
538
Figure 6.12-6 Data Format of One I
539
Figure 6.12-7 Acknowledge Bit
539
Figure 6.12-8 Arbitration Procedure of Two Masters
540
Figure 6.12-9 Control I
540
Figure 6.12-10 Flow and Status of Master Transmitter Mode
542
Figure 6.12-11 Flow and Status of Master Receiver Mode
543
Figure 6.12-12 Flow and Status of Slave Receiver Mode
545
Figure 6.12-13 Flow and Status of General Call Mode
546
C Time-Out
547
Figure 6.12-14 Status Display in I2STAT Register
547
Figure 6.12-15 I C Time-Out Counter
548
C Interrupt
550
Register Description
550
Typical Structure of I C Interrupt Service Routine
557
12-Bit Analog-To-Digital Converter (ADC)
561
Overview
561
Block Diagram
562
Figure 6.13-1 12-Bit ADC Block Diagram
562
Functional Description
563
Figure 6.13-2 External Triggering ADC Circuit
564
Figure 6.13-3 ADC Result Comparator
564
Figure 6.13-4 ADC Continues Mode with DMA
565
Register Description
566
Voltage Reference
583
Ref
583
Figure 6.14-1 VREF Block Diagram
583
Figure 6.14-2 Pre-Load Timing
583
Analog Comparator Controller (ACMP)
585
Overview
585
Feature
585
Block Diagram
586
Figure 6.15-1 Analog Comparator Block Diagram
586
Functional Description
587
Figure 6.15-2 Comparator Hysteresis Function
587
Figure 6.15-3 Comparator Reference Voltage Block Diagram
588
Figure 6.15-4 Analog Comparator Interrupt Sources
588
Register Description
589
PDMA Controller (PDMA)
595
Overview
595
Feature
595
Block Diagram
595
Figure 6.16-1 PDMA Interface Diagram
595
Functional Description
596
Figure 6.16-2 PDMA Controller Block Diagram
596
Figure 6.16-3 CRC-8 Block Diagram
598
Register Description
599
LCD Driver
610
Overview
610
Features
610
Block Diagram
611
Figure 6.17-1 LCD Block Diagram
611
Functional Description
612
Figure 6.17-2. LCD Register Map Example
613
Figure 6.17-3 One Frame of LCD Energized
613
Figure 6.17-4. Example of Type a and Type B 8 COM and SEG Driving Signals of 1/3 Bias
614
Figure 6.17-5. Example of Type a and Type B 8 COM and SEG Driving Signals of 1/4 Bias
615
Table 6.17-1 VLCD Source Selection Table
616
Table 6.17-2 LCD Driving Mode Regiter Setting
616
Register Description
618
LCD Program Flow
633
Real Time Clock (RTC)
634
Overview
634
Features
634
Block Diagram
635
Figure 6.18-1 RTC Block Diagram
635
Functional Description
636
Table 6.18-1 RTC Read/Write Enable
637
Table 6.18-212/24 Hour Time Scale Selection
638
Table 6.18-3 Registers Value after Powered on
639
Register Description
640
Table 6.19-1 All Touch Key Pins Select Source List
667
Figure 6.19-1Touch Key Block Diagram
668
Figure 6.19-2 Touch Key Sensing Method
670
Figure 6.19-3 Finger Touch Detection Method
671
Figure 6.19-4 Touch Key Controller Interrupt Modes for Threshold Control
673
Table 6.20-1 Instruction Set and Addressing Modes
696
Table 6.20-2 Instructions Affect Flag Settings
697
Table 6.20-3 Instruction Set
701
Figure 9.1-1 LQFP 64L Package Dimension
705
Figure 9.2-1 LQFP-48 Package Dimension
706
Figure 9.3-1 LFP44 Package Dimension
707
Figure 9.4-1 QFN-33 Package Dimension
708
Figure 9.5-1 LQFP-32 Package Dimension
709
Figure 9.6-1 TSSOP-28 Package Dimension
710
Figure 9.7-1 SOP-28 Package Dimension
711
Figure 9.8-1 TSSOP-20 Package Dimension
712
Figure 9.9-1 SOP-20 Package Dimension
713
Figure 9.10-1 QFN-20 Package Dimension
714
Figure 9.11-1 TSSOP-14 Package Dimension
715
Figure 9.12-1 MSOP-10 Package Dimension
716
Table 10.1-1 List of Abbreviations
717

Nuvoton NuMicro ML51 Series Technical Reference Manual (401 pages)

8-bit Microcontroller

Brand: Nuvoton | Category: Microcontrollers | Size: 5 MB

Table of Contents
2
General Description
12
Features
14
Part Information
17
3.1 ML51 Series Selection Guide
17
3.2 ML51 Series Selection Code
18
Pin Configuration
19
ML51 Series Pin Diagram
19
Figure 4.1-1 Pin Assignment of QFN-33 Package
19
Figure 4.1-2 Pin Assignment of LQFP-32 Package
20
Figure 4.1-3 Pin Assignment of TSSOP-28 Package
20
Figure 4.1-4 Pin Assignment of SOP-28 Package
21
Figure 4.1-5 Pin Assignment of TSSOP-20 Package
21
Figure 4.1-6 Pin Assignment of TSSOP-20 Package
22
Figure 4.1-7 Pin Assignment of QFN-20 Package
22
Figure 4.1-8 Pin Assignment of TSSOP-14 Package
23
Figure 4.1-9 Pin Assignment of MSOP-10 Package
23
ML51 Series Multi Function Pin Diagram
24
Figure 4.1-10 Multi Function Pin Assignment of QFN-33 Package
24
Figure 4.1-11 Multi Function Pin Assignment of LQFP-32 Package
25
Figure 4.1-12 Multi Function Pin Assignment of TSSOP-28 Package
26
Figure 4.1-13 Multi Function Pin Assignment of SOP-28 Package
26
Figure 4.1-14 Multi Function Pin Assignment of TSSOP-20 Package
26
Figure 4.1-15 Multi Function Pin Assignment of SOP-20 Package
27
Figure 4.1-16 Multi Function Pin Assignment of QFN-20 Package
27
Figure 4.1-17 Multi Function Pin Assignment of Package
28
Figure 4.1-18 Pin Assignment of MSOP-10 Package
28
4.2 Pin Description
29
Block Diagram
37
5.1 Ml51 Full Function Block
37
Figure 5.1-1 Functional Block Diagram
37
Memory Organization
38
6.1 Program Memory
38
6.2 Data Memory
40
Figure 6.1-1 ML51 Program Memory Map
40
Figure 6.2-1 Data Memory Map
40
Figure 6.2-2 Internal 256 Bytes RAM Addressing
42
6.3 On-Chip XRAM
43
6.4 Data Flash
43
Special Function Register (Sfr)
44
Sfr
44
Table 7.1-1 Special Function Register (SFR) Memory Map
45
Table 7.1-2 SFR Definitions and Reset Values
47
7.2 All SFR Description
63
General 80C51 System Control
152
Table 7.2-1 Instructions that Affect Flag Settings
154
O Port Structure and Operation
156
9.1 Quasi-Bidirectional Mode
156
Table 7.2-1 Configuration for Different I/O Modes
156
9.2 Push-Pull Mode
157
Figure 9.1-1 Quasi-Bidirectional Mode Structure
157
Figure 9.2-1 Push-Pull Mode Structure
157
9.3 Input-Only Mode
159
9.4 Open-Drain Mode
159
9.5 Read-Modify-Write Instructions
159
Figure 9.3-1 Input-Only Mode Structure
159
Figure 9.4-1 Open-Drain Mode Structure
159
9.6 Control Registers of I/O Ports
160
Input and Output Data Control
160
GPIO Mode Control
163
GPIO Multi-Function Select
164
Input Type
166
Output Slew Rate Control
167
Pull-Up Resister Control
168
Figure 10.1-1 Timer/Counters 0 and 1 in Mode 0
175
Figure 10.2-1 Timer/Counters 0 and 1 in Mode 1
175
Figure 10.3-1 Timer/Counters 0 and 1 in Mode 2
176
Figure 10.4-1 Timer/Counter 0 in Mode 3
177
Figure 10.4-1 Timer 2 Block Diagram
178
Figure 11.1-1 Timer 2 Auto-Reload Mode and Input Capture Module Functional Block Diagram
182
Figure 11.2-1 Timer 2 Compare Mode and Input Capture Module Functional Block Diagram
183
Figure 11.4-1 Timer 3 Block Diagram
189
Figure 13.1-1 WDT as a Time-Out Reset Timer
193
Table 11.4-1 Watchdog Timer-Out Interval under Different Pre-Scalars
193
Figure 13.2-1 Watchdog Timer Block Diagram
194
Figure 13.2-1 Self Wake-Up Timer Block Diagram
196
Figure 15.1-1 Serial Port Mode 0 Timing Diagram
199
Figure 15.2-1 Serial Port Mode 1 Timing Diagram
200
Figure 15.3-1 Serial Port Mode 2 and 3 Timing Diagram
201
Table 15.5-1 Serial Port 0 Mode / Baudrate Description
202
Table 15.5-2 Serial Port 1 Mode / Baudrate Description
203
Figure 16.1-1 SC Controller Block Diagram
216
Figure 16.4-1 SC Data Character
228
Figure 16.4-2 Initial Character TS
229
Figure 16.4-3 SC Error Signal
229
Figure 16.4-4 Transmit Direction Block Guard Time Operation
230
Figure 16.4-5 Receive Direction Block Guard Time Operation
230
Figure 16.4-6 Extra Guard Time Operation
230
Figure 17.1-1 SPI Block Diagram
231
Figure 17.1-2 SPI Multi-Master, Multi-Slave Interconnection
232
Figure 17.1-3 SPI Single-Master, Single-Slave Interconnection
233
Table 17.2-1 Slave Select Pin Configurations
238
Figure 17.4-1 SPI Clock Formats
241
Figure 17.4-2 SPI Clock and Data Format with CPHA = 0
242
Figure 17.4-3 SPI Clock and Data Format with CPHA = 1
242
Figure 17.8-1 SPI Overrun Waveform
244
Figure 17.9-1 SPI Interrupt Request
244
Figure 18.1-1 I 2 C Bus Interconnection
245
Figure 18.1-2 I 2 C Bus Protocol
246
Figure 18.1-3 START, Repeated START, and STOP Conditions
247
Figure 18.1-4 Master Transmits Data to Slave by 7-Bit
247
Figure 18.1-5 Master Reads Data from Slave by 7-Bit
248
Figure 18.1-6 Data Format of One I C Transfer
248
Figure 18.1-7 Acknowledge Bit
249
Figure 18.1-8 Arbitration Procedure of Two Masters
250
Figure 18.1-9 Control I C Bus According to the Current I C Status
251
Figure 18.1-10 Flow and Status of Master Transmitter Mode
252
Figure 18.1-11 Flow and Status of Master Receiver Mode
253
Figure 18.1-12 Flow and Status of Slave Receiver Mode
255
Figure 18.1-13 Flow and Status of General Call Mode
256
Figure 18.4-1 I 2 C Time-Out Counter
267
Figure 18.5-1 Pin Interface Block Diagram
269
Figure 20.1-1 PWM Block Diagram
275
Figure 20.1-2 PWM and Fault Brake Output Control Block Diagram
276
Figure 20.1-3 PWM Edge-Aligned Type Waveform
282
Figure 20.1-4 PWM Center-Aligned Type Waveform
283
Figure 20.1-5 PWM Complementary Mode with Dead-Time Insertion
285
Figure 20.1-6 Fault Brake Function Block Diagram
288
Figure 20.2-1 PWM Interrupt Type
292
Figure 21.1-1 12-Bit ADC Block Diagram
293
Figure 21.1-2 External Triggering ADC Circuit
295
Figure 21.1-3 ADC Result Comparator
296
Figure 21.1-4 ADC Continues Mode with DMA
296
Figure 21.2-1 VREF Block Diagram
304
Figure 21.2-2 Pre-Load Timing
304
Figure 23.1-1 Analog Comparator Block Diagram
306
Figure 23.2-1 Comparator Hysteresis Function
308
Figure 23.3-1 Comparator Reference Voltage Block Diagram
309
Figure 23.4-1 Analog Comparator Interrupt Sources
309
Figure 23.5-1 PDMA Interface Diagram
314
Figure 24.1-1 PDMA Controller Block Diagram
315
Table 26.1-1 Interrupt Vectors
323
Table 26.3-1 Interrupt Priority Level Setting
329
Table 26.3-2 Characteristics of each Interrupt Source
330
Table 27.1-1 IAP Modes and Command Codes
343
Table 27.4-1 Power Mode Table
352
Table 27.4-2 Entry Setting of Power down Mode
352
Figure 28.4-1 Clock System Block Diagram
355
Figure 30.2-1 Brown-Out Detection Block Diagram
362
Table 30.2-1 BOF Reset Value
364
Table 30.2-2 Minimum Brown-Out Detect Pulse Width
366
Figure 31.6-1 Boot Selecting Diagram
371
Table 33.2-1 Instruction Set
380
Figure 36.1-1 CONFIG0 any Reset Reloading
386
Figure 36.3-1 CONFIG2 Power-On Reset Reloading
388
Figure 37.1-1 LQFP-48 Package Dimension
390
Figure 37.2-1 QFN-33 Package Dimension
391
Figure 37.3-1 LQFP-32 Package Dimension
392
Figure 37.4-1 TSSOP-28 Package Dimension
393
Figure 37.5-1 SOP-28 Package Dimension
394
Figure 37.6-1 TSSOP-20 Package Dimension
395
Figure 37.7-1 SOP-20 Package Dimension
396
Figure 37.8-1 QFN-20 Package Dimension
397
Figure 37.9-1 TSSOP-14 Package Dimension
398
Figure 37.10-1 MSOP-10 Package Dimension
399

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