Chipset Configuration - Asus DSBF-D Series Manual

Echo TPR [Disabled] Echo TPR [Disabled]
Echo TPR [Disabled] Echo TPR [Disabled] Echo TPR [Disabled]
Configuration options: [Disabled] [Enabled]
Discrete MTRR Allocation [Disabled] Discrete MTRR Allocation [Disabled] Discrete MTRR Allocation [Disabled]
Discrete MTRR Allocation [Disabled] Discrete MTRR Allocation [Disabled]
Configuration options: [Disabled] [Enabled]
4.4.2 4.4.2 4.4.2

Chipset Configuration

Chipset Configuration Chipset Configuration
4.4.2 4.4.2 Chipset Configuration Chipset Configuration
This menu shows the chipset configuration settings. Select an item then
press <Enter> to display a pop-up menu with the configuration options.
Advanced
Crystal Beach Configure Enable
SERR Signal Condition
4GB PCI Hole Granularity
Memory Branch Mode
Branch 0 Rank Sparing
Branch 1 Rank Sparing
Enhanced x8 Detection
Force ITK Config Clocking
Enable Multimedia Timer
FBDIMM(S)Thermal Throttling Control
Open Loop Type
Memory Cache
↑ ↑ ↑ ↑ ↑ ↓ ↓ ↓ ↓ ↓ : Select Item
F1:Help
→← →←: Select Menu →←
ESC: Exit →← →←
Crystal Beach Configure Enable [Enabled] Crystal Beach Configure Enable [Enabled]
Crystal Beach Configure Enable [Enabled] Crystal Beach Configure Enable [Enabled] Crystal Beach Configure Enable [Enabled]
Allows you to enable or disable the Configuration/Memory mapped
accesses to the Crystal Beach Configuration space located in Device 8, Fn
0, and Fn 1. Configuration options: [Disabled] [Enabled]
SERR Signal Condition [Single Bit] SERR Signal Condition [Single Bit] SERR Signal Condition [Single Bit] SERR Signal Condition [Single Bit] SERR Signal Condition [Single Bit]
Allows you to select the ECC error that the SERR# asserts.
Configuration options: [None] [Single Bit] [Multiple Bit] [Both]
4GB PCI Hole Granularity [256 MB] 4GB PCI Hole Granularity [256 MB] 4GB PCI Hole Granularity [256 MB] 4GB PCI Hole Granularity [256 MB] 4GB PCI Hole Granularity [256 MB]
Allows you to select the granularity of the PCI hole for PCI resource.
Configuration options: [256 MB] [512 MB] [1.0 GB] [2.0 GB]
Memory Branch Mode [Interleave] Memory Branch Mode [Interleave] Memory Branch Mode [Interleave]
Memory Branch Mode [Interleave] Memory Branch Mode [Interleave]
Allows you to select the memory branch mode.
Configuration options: [Sequential] [Interleave] [Mirror] [Single Channel]
A S U S D S B F - D S e r i e s A S U S D S B F - D S e r i e s
A S U S D S B F - D S e r i e s A S U S D S B F - D S e r i e s A S U S D S B F - D S e r i e s
PhoenixBIOS Setup Utility
Chipset Configuration
[Enabled]
[Single Bit]
[256 MB]
[Interleave]
[Disabled]
[Disabled]
[Enabled]
[Disabled]
[No]
[Open Loop]
[Best Performan]
-/+: Change Values
Enter: Select
Item Specific Help
Enable Configuration/
Memory mapped accesses to
the Crystal Beach
Configuration space
located in Device 8, Fn
0, and Fn 1.
F9: Setup Defaults
Sub-menu F10: Save and Exit
4 - 1 9 4 - 1 9
4 - 1 9 4 - 1 9 4 - 1 9