Seco Q7-C25 User Manual page 30

Table of Contents

Please take note that USB Port #1 with its Superspeed Signals during normal condition does work as USB 3.0 Host Port. Client mode is supported only during serial

download when signal BOOT_ALT# is driven low. With Software customization if needed, this port can be configured to work always in Client mode.

3.2.8

Audio interface signals

Q7-C25 module supports I2S audio format, thanks to native support offered by the processor to this audio codec standard.

Here following the signals related to AC'97/I2S Audio interface:

I2S_WS: I2S Word Select Signal. Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_RST#: I2S Codec Reset. Active Low signal Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_CLK: I2S Serial Data Clock signal. Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_SDO: I2S Serial Data Out signal. Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_SDI: I2S Serial Data In signal. Input to the module from the Carrier board, electrical level +3.3V_RUN.

All these signals have to be connected, on the Carrier Board, to an I2S Audio Codec. Please refer to the chosen Codec s Reference Design Guide for correct

implementation of audio section on the carrier board.

3.2.9

LVDS and eDP Flat Panel signals

All processors included in i.MX8M family provide a four-lane MIPI display serial interface operating up to a maximum bit rate of 1.5 Gbps. The MIPI-DSI is used to

implement a 18/24 bit Dual Channel LVDS or, as a factory alternative, an eDP interface

ONLY ONE set of signals from the following two sets are present, dependent on the factory board configuration.

EITHER the signals for primary channel are LVDS:

LVDS_A0+ / LVDS_A0- : LVDS Channel #A differential data pair #0

LVDS_A1+/ LVDS_A1-: LVDS Channel #A differential data pair #1

LVDS_A2+/LVDS_A2-: LVDS Channel #A differential data pair #2

LVDS_A3+/ LVDS_A3-: LVDS Channel #A differential data pair #3

LVDS_A_CLK+ / LVDS_A_CLK-: LVDS Channel #A differential Clock

OR the signals for primary channel are eDP:

eDP0_TX0+/ eDP0_TX0-: embedded DisplayPort Channel #0 differential data pair #0

eDP0_TX1+/ eDP0_TX1-: embedded DisplayPort Channel #0 differential data pair #1

eDP0_TX2+/ eDP0_TX2-: embedded DisplayPort Channel #0 differential data pair #2