Seco Q7-C25 User Manual page 26

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3.2.4 PCI Express interface signals
The Q7-C25 module can offer two PCI Express x1 lanes, which are directly managed by i.MX8M processor (all versions).
PCI express Gen 2.0 (5Gbps) is supported.
Here following the signals involved in PCI express management
PCIE0_RX+/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair
PCIE0_TX+/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair
PCIE1_RX+/PCIE1_RX-: PCI Express lane #1, Receiving Input Differential pair
PCIE1_TX+/PCIE1_TX-: PCI Express lane #1, Transmitting Output Differential pair
PCIE_CLK_REF+/PCIE_CLK_REF-: PCI Express Reference Clock, Differential Pair
PCIE_RST#: Reset Signal that is sent from Qseven
directly to drive externally a single RESET Signal. In case there is the need to supply Reset signal to multiple devices, it is recommended to provide for a buffer on the
carrier board.
PCIE_WAKE#: Wake up Signal that is asserted from any PCI-e device available on the carrier board to Qseven
-up resistor. Controlled by a STM32 MCU soldered onboard the Q7 module.
3.2.5 UART interface signals
According to Qseven ® Rel. 2.1 specifications, Q7-C25 offers one UART interface, directly managed by i.MX8M processor (all versions). This interface is optional, and
is available when UART is not used for WiFi + BT module. Please be sure of factory configuration for the module ordered.
Here following the signals related to UART interface:
UART0_TX: UART Interface, Serial data Transmit (output) line, +3.3V_RUN electrical level.
UART0_RX: UART Interface, Serial data Receive (input) line, +3.3V_RUN electrical level.
Q7-C25
Q7-C25 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.0 - Authors: S.B. and A.R - Reviewed by N.P. - Copyright © 2020 SECO S.p.A
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® Module to any PCI-e device available on the carrier board. It is a +3.3V_RUN active-low signal; it can be used
218 N.C.
219 220 VCC
221 222 VCC
223 224 VCC
225 226 VCC
227 228 VCC
229 230 VCC
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®
Module. It is a 3V3_ALW active-low signal with a
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