Power Block; Analog Video Output Circuit; Digital Image Data Processing Circuit; Outline Of Main Cpu Operation - Sony SNC-Z20N Service Manual

4-3. SY-310 Board

4-3-1. Power Block

There are two methods of supplying the power as follows.
1. The 24 VAC or 12 V DC is supplied from CN503 on
the CT-229 board.
2. A power is supplied by PoE (IEEE 802.3af standard)
from the RJ45 terminal of CN802 on the SY-310
board.
When the power is input simultaneously, the PoE with
higher voltage takes priority.
In the case of (1), when the power is input from CN503, it
is connected to the power module via CN501 on the CT-
229 board.
In the case of (2), a power supply of 48 V DC input from
the RJ45 terminal is connected to the power module via
CN805.
The power module uses a relay to switch AC-DC in order
to improve the efficiency. A current limiter (400 mA) is
provided in the preliminary step so that the DC power
input from PoE does not exceed the specification. The 10
V DC, 5 V DC and 3.3 V DC that are required in this unit
are generated by these inputs.
The 10 V DC is used for the camera block. The 5 V DC
and 3.3 V DC are used for the SY-310 board. These
voltages are connected to CN801 on the SY-310 board via
CN103 on the power module.
n
PoE : Power-over-ethernet (Power supply method
conforming to IEEE 802.3af)
Maximum rating that can be consumed in the terminal:
12.95 W
Maximum current that can be used in the terminal:
400 mA
Power supply: 48 V DC

4-3-2. Analog Video Output Circuit

The video signal generated in the camera block is
connected to CN804 on the SY-310 board and it is output
from the BNC connector via CN702 on the SY-310 board
through CN502 on the CT-229 board.
SNC-Z20N/Z20P (E)

4-3-3. Digital Image Data Processing Circuit

The digital image data processing circuit outputs the
interlaced YUV411 digital image data (CAMY[7:0] and
CAMC[3:0]) and control signal (CCLK) and inputs them
from the camera block to MJPEG controller (IC703)
through CN701. In IC703, an image format is converted
into YCbCr422, and frame data is written in SDRAM
(IC702). The conversion of interlacing to non-interlacing
and the data conversion such as square latticing and
resizing are performed to make a raster block conversion
using a buffer (SRAM, IC706). The resultant data is sent
to JPEG IC (IC705). Data is JPEG-compressed in JPEG
IC (IC705).
IC703 incorporates a DMA interface with Main CPU
HD6417615 (IC606). IC703 transfers the JPEG
compression data to SDRAM (IC607 and IC609) by DMA
(XSH_DREQ and XSH_DACK) and stores it at high
speed. SH bus address decoding, external interrupt control
or external wait control is provided. The control signals
from each IC are input to IC703 and output to Main CPU
(IC606) after it is controlled. IC703 also has an internal
dynamic detector.

4-3-4. Outline of Main CPU Operation

HD6417615 (Main CPU, IC606) mainly controls the
access to MJPEG controller (IC703), system memory
(SDRAM, IC607 and IC609), system ROM (flash
memory, IC610 and IC611), a PC card controller (IC203),
and a PHY chip (IC801). It also transfers data (JPEG
image data) via a network or records data in a PC card.
Moreover, Main CPU performs the external interface (RS-
232, sensor input, and alarm output) control, the LED
control, the clock generation (output of a 30 MHz clock to
IC605), the interrupt control, the RTC (IC602) control, the
software reset (XSRST) control, etc.

4-3-5. System ROM

The system ROM (flash memory, IC610 and IC611) that
has a capacity of 8 MB stores the data on the operation
program of Main CPU (IC606), Web contents, or system
environmental information. The data is read and written
by an SH data bus.
Since the system ROM is constituted by flash memory, it
can upgrade software from a PC card through a network.
4-3