Spi; Table 11-2. I2C Interface Signal Routing Requirements; Table 11-3. I2C Signal Connections; Table 11-4. Jetson Nano Spi Pin Description - Nvidia Jetson Nano Product Design Manual

Table 11-2. I2C Interface Signal Routing Requirements
Parameter
Max frequency
Topology
Max loading
Reference plane
Trace impedance
Trace spacing
Max trace length/delay
Notes:
1. Fm = Fast-mode, Fm+ = Fast-mode Plus.
2. Avoid routing I2C signals near noisy traces, supplies or components such as a switching power regulator.
3. No requirement for decoupling caps for PWR reference.
Table 11-3. I2C Signal Connections
Module Pin Name Type
I2C0_SCL/SDA I/OD
I2C1_SCL/SDA I/OD
I2C2_SCL/SDA I/OD
CAM_I2C_SCL/SDA I/OD
Notes:
1. If some devices require a different voltage level than others connected to the same I2C bus, level shifters are required.
2. For I2C interfaces that are pulled up to 1.8V, disable the E_IO_HV option for these pads. For I2C interfaces that are pulled up to 3.3V, enable the E_IO_HV
option. The E_IO_HV option is selected in the Pinmux registers.
11.2

SPI

The Jetson Nano brings out two of the Tegra SPI interfaces. See Figure 11-2.
Table 11-4. Jetson Nano SPI Pin Description
Pin # Module Pin Name Tegra X1 Signal
89 SPI0_MOSI SPI1_MOSI
91 SPI0_SCK SPI1_SCK
93 SPI0_MISO SPI1_MISO
95 SPI0_CS0* SPI1_CS0
97 SPI0_CS1* SPI1_CS1
104 SPI1_MOSI SPI2_MOSI
106 SPI1_SCK SPI2_SCK
108 SPI1_MISO SPI2_MISO
NVIDIA Jetso n Nano
Standard-mode / Fm / Fm+
Standard-mode / Fm / Fm+
Standard Mode
Fm, Fm+ Modes
Termination
2.2kΩ pull-ups to VDD_3V3_SYS on Jetson
Nano
2.2kΩ pull-ups to VDD_3V3_SYS on Jetson
Nano
2.2kΩ pull-ups to VDD_1V8 on Jetson Nano
2.2kΩ pull-ups to VDD_3V3_SYS on Jetson
Nano
Usage/Description
SPI 0 Master Out / Slave In
SPI 0 Clock
SPI 0 Master In / Slave Out
SPI 0 Chip Select 0
SPI 0 Chip Select 1
SPI 1 Master Out / Slave In
SPI 1 Clock
SPI 1 Master In / Slave Out
Requirement
100 / 400 / 1000
Single ended, bi-directional, multiple masters/slaves
400
GND or PWR
50 – 60
1x
3400 (~20)
1700 (~10)
Description
I2C #0 Clock and Data. Connect to CLK and Data pins of any 3.3V devices
I2C #1 Clock and Data. Connect to CLK and Data pins of 3.3V devices.
I2C #2 Clock and Data. Connect to CLK and Data pins of any 1.8V devices
Camera I2C Clock and Data. Connect to CLK and Data pins of any 3.3V
devices
Usage on NVIDIA DevKit
Carrier Board
Expansion header
Miscellaneous Interfaces
Units Notes
kHz See Note 1
pF Total of all loads
Ω ±15%
dielectric
ps (in)
MPIO Pad
Direction Pin Type
Code
LV_CZ
LV_CZ
LV_CZ
LV_CZ
Bidir CMOS – 1.8V
LV_CZ
CZ
CZ
CZ
DG-09502-001_v2.1 | 59
Power-on
Reset
pd
pd
pd
pu
pu
pd
pd
pd