Power Supply And Sequencing; Figure 5-1. Jetson Nano Power And Control Block Diagram - Nvidia Jetson Nano Product Design Manual

Pin # Module Pin Name Tegra X1 Signal
Notes:
1. In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals.
2. The directions for FORCE_RECOVERY* and SLEEP/WAKE* signals are true when used for those functions. Otherwise as GPIOs, the
direction is bidirectional.
3. The MPIO Pad Codes are described in the
(PinMux)" section for details.
The Power-on Reset State column indicates the pin state when reset is active and when it is deactivated before any changes are made by
4.
software. "z" is tristate, pu/pd indicates internal weak pull-up/down resistor is enabled, 1/0 indicates actively driven high/low.
Figure 5-1.
251
252
253
Main 5V
254
Power
255 VDD_IN
Source
256
257
258
259
260
Super
PMIC_ BBAT
Cap or
235
Li Cell
5.1

Power Supply and Sequencing

The carrier board receives the main power source and uses this to generate the enable to
Jetson Nano (
POWER_EN
associated decoupling capacitors have charged. The carrier board supplies are not enabled at
this time. Once
POWER_EN
module Power-ON sequence has completed, the
this is used by the carrier board to enable its various supplies.
can be driven by the carrier board to reset Jetson Nano, which results in a full system power
cycle. The
SHUTDOWN_REQ*
must be shut down, due to a critical thermal issue, etc. The power control logic on the carrier
board should drive
signal is latched to a logic low level when the
NVIDIA Jetso n Nano
Usage/Description
is controlled by system software and should
not be modified.
Tegra X1 SoC Technical Reference Manual
Jetson Nano Power and Control Block Diagram
Jetson Nano
Power Subsystem
Memory/Peripherals
LPDDR4, eMMC,
Ethernet
) after the carrier board has ensured the main supply is stable and the
is driven active (high), Jetson Nano begins to Power-ON. When the
signal from Jetson Nano can be driven active (low) if the system
inactive (low) if
POWER_EN
Usage on NVIDIA DevKit
Carrier Board
"Multi-Purpose I/O Pins and Pin Multiplexing
POWE R_E N
VDD_1V8
SYS _RESET*
VDD_1V8
VDD_1V8
SLEEP /WAKE *
Tegra X1
MOD_SLEEP *
100kΩ
Level
VDD_IN (5V)
Shifter
SHUTDOWN_REQ*
signal is driven inactive (high) and
SYS_RESET*
SYS_RESET*
is asserted. The
SHUTDOWN_REQ*
supply is at or below 4.2V.
VDD_IN
Power
MPIO Pad
Direction Pin Type
Code
From Carrier Board power
237
ON/OFF control logic
System Reset from Carrier
Board. Carrier Board power
239
enable from Module.
Optional Sleep/Wake Button
SLEEP/WAKE
240
Indicates Module is entering
178
Sleep (LP0) mode
To Carrier Board – Used to force
power off if shutdown request
233
(Thermal Shutdown, Power Bad or
Software Shutdown, etc.) is received
is bidirectional and
SHUTDOWN_REQ*
DG-09502-001_v2.1 | 12
Power-on
Reset