Nvidia Jetson Nano Product Design Manual
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Nvidia Jetson Nano Product Design Manual

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NVIDIA Jetson Nano
Product Design Guide
DG-09502-001_v2.1
|
July 2020

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Summary of Contents for Nvidia Jetson Nano

  • Page 1 NVIDIA Jetson Nano Product Design Guide DG-09502-001_v2.1 July 2020...
  • Page 2 Removed GPIO08 for SD Card Detect from Table 9-3 since figure shows generic GPIO • Updated Table 11-6 to mention buffer on module • The Jetson Nano pin description and design checklist are now attachments to this design guide NVIDIA Jetso n Nano DG-09502-001_v2.1 | ii...

  • Page 3: Table Of Contents

    Table of Contents Chapter 1. Introduction ....................1 References ......................1 Abbreviations and Definitions..................2 Chapter 2. Jetson Nano ....................4 Chapter 3. Developer Kit Feature Considerations ............7 USB SuperSpeed Hub.....................7 Power Over Ethernet (PoE) ..................7 TI TXB0108 Level Shifters ..................8 Features Not to be Implemented ................8 Chapter 4.
  • Page 4 Chapter 13. Unused Interface Terminations ..............69 13.1 Unused Multi-purpose Standard CMPS Pad Interfaces .......... 69 Chapter 14. Jetson Nano Pin Descriptions and Design Checklist........70 Chapter 15. General Routing Guidelines ................71 15.1 Signal Name Conventions ..................71 15.2 Routing Guideline Format ..................
  • Page 5 List of Figures Figure 2-1. Jetson Nano Block Diagram................5 Figure 4-1. Jetson Nano Module Installed in SODIMM Connector ........10 Figure 4-2. Module to Connector Assembly Diagram ............. 10 Figure 5-1. Jetson Nano Power and Control Block Diagram........... 12 Figure 5-2.
  • Page 6 Figure 11-3. Basic SPI Master and Slave Connections ............. 60 Figure 11-4. SPI Topologies .................... 61 Figure 11-5. Jetson Nano UART Connections ..............62 Figure 11-6. Jetson Nano Fan Connections ..............64 Figure 11-7. JTAG and Debug UART Connections ............65 Figure 11-8.
  • Page 7 Jetson Nano Power and System Pin Descriptions ........11 Table 6-1. Jetson Nano USB 2.0 Pin Descriptions............15 Table 6-2. Jetson Nano USB 3.0 and PCIe Pin Descriptions .......... 15 Table 6-3. Jetson Nano USB 3.0 and PCIe Lane Mapping Configurations....... 16 Table 6-4.
  • Page 8 Jetson Nano UART Pin Description.............. 62 Table 11-7. UART Signal Connections................63 Table 11-8. Jetson Nano Fan Pin Description..............63 Table 11-9. Jetson Nano JTAG and Debug UART Description.......... 64 Table 11-10. JTAG Connections..................66 Table 11-11. Debug UART Connections ................66 Table 12-1.

  • Page 9: Chapter 1. Introduction

    Refer to software release documentation for information on supported capabilities. Note: Most of the interface usage noted in this design guide is based on the NVIDIA developer kit carrier board design.

  • Page 10: Abbreviations And Definitions

    Millimeter PCIe Peripheral Component Interconnect Express interface Pulse Code Modulation Physical Interface (i.e. USB PHY) Pico-Seconds Power Management Unit 8P8C modular connector used in Ethernet and other data RJ45 links Real Time Clock NVIDIA Jetso n Nano DG-09502-001_v2.1 | 2...
  • Page 11 Introduction Abbreviation Definition SD Card Secure Digital Card SDIO Secure Digital I/O Interface Single-Ended Serial Peripheral Interface TMDS Transition-minimized differential signaling UART Universal Asynchronous Receiver-Transmitter Universal Serial Bus NVIDIA Jetso n Nano DG-09502-001_v2.1 | 3...

  • Page 12: Chapter 2. Jetson Nano

    Chapter 2. Jetson Nano The Jetson Nano resides at the center of the embedded system solution and includes the following: Power (PMIC/Regulators, etc.)  DRAM (LPDDR4)  eMMC  Gigabit Ethernet Controller  Power Monitor  In addition, a wide range of interfaces are available at the main connector for use on the carrier board as shown Table 2-1 and Figure 2-1.

  • Page 13: Figure 2-1. Jetson Nano Block Diagram

    16GB Note: DP on eDP interface does not support HDCP or Audio Table 2-2 lists the 260-pin SO-DIM description for the Jetson Nano connector. Table 2-2. Jetson Nano Connector Pinout Matrix Module Signal Name Pin # Pin # Module Signal Name...
  • Page 14 USB2 D P GPIO02 VDD IN VDD IN GPIO03 VDD_IN VDD_IN GPIO04 GPIO05 VDD IN VDD IN GPIO06 VDD IN VDD IN PCIE0 RX0 N Legend Ground Power Reserved - must be left unconnected NVIDIA Jetso n Nano DG-09502-001_v2.1 | 6...

  • Page 15: Chapter 3. Developer Kit Feature Considerations

    PoE supply (38V-60V) and convert it to the correct voltage for the custom carrier board. This could be the 5V that the Jetson Nano DevKit uses, or a different voltage depending on the design of the custom carrier board.

  • Page 16: Ti Txb0108 Level Shifters

    Features Not to be Implemented The Jetson Nano Developer Kit carrier board features that should not be copied as they are not required or useful for a custom carrier board design. The ID EEPROM (P3449 - U11) is a feature that is used for NVIDIA internal purposes, but not useful on a custom design.

  • Page 17: Chapter 4. Modular Connector

    Jetson Nano modules connect to the carrier board using a 260-pin SO-DIMM connector. The mating connector used on the Developer Kit carrier board is listed in the Jetson Nano SCL (Supported Components List). This connector is a DDR4 SODIMM, 260-pin, right-angle, standard key type.

  • Page 18: Module Installation And Removal

    Arc down the module board until the SODIMM connector latch engages. d) Secure the Jetson Nano module to the baseboard with screws into the standoff/spacer. The Developer Kit (shown in Figure 4-2) uses a standoff and screws to secure the module to the system/base- board.

  • Page 19: Chapter 5. Power

    5.0V (see the VDD_IN Nano Data Sheet for supply tolerance and maximum current). CAUTION: Jetson Nano is not hot-pluggable. When installing the module, the main power supply should not be connected. Before removing the module, the main power supply (to pins) VDD_IN must be disconnected and allowed to discharge below 0.6V.

  • Page 20: Power Supply And Sequencing

    Notes: 1. In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. 2. The directions for FORCE_RECOVERY* and SLEEP/WAKE* signals are true when used for those functions. Otherwise as GPIOs, the direction is bidirectional.

  • Page 21: Figure 5-2. System Power And Control Block Diagram

    Power Up Sequence Power-up Sequence (No Power Button – Auto-Power-On Enabled) VDD_IN POWER_EN Module Power SYS_RESET* Carrier Board Supplies Figure 5-4. Power Down – Initiated by SHUTDOWN_REQ* Assertion) VDD_IN SHUTDOWN_REQ* POWER_EN T < 10uS NVIDIA Jetso n Nano DG-09502-001_v2.1 | 13...

  • Page 22: Figure 5-5. Power Down - Sudden Power Loss

    T > 10mS SHUTDOWN_REQ* POWER_EN T < 10uS Note: - must always be serviced by the carrier board to toggle from SHUTDOWN_REQ* POWER_EN high to low, even in cases of sudden power loss. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 14...

  • Page 23: Chapter 6. Usb And Pci Express

    − Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The direction of GPIO00 is true when used for this function. Otherwise as a GPIO, the direction is bidirectional.

  • Page 24: Table 6-3. Jetson Nano Usb 3.0 And Pcie Lane Mapping Configurations

    Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The directions for PCIE_WAKE*, PCIE0_RST*, and PCIE0_CLKREQ are true when used for those functions. Otherwise as GPIOs, the direction is bidirectional.

  • Page 25: Usb

    TX_p TPD4E 05U06 Notes: 1. AC capacitors should be located close to either the USB connector, or the Jetson Nano pins. 2. For USB 3.0 IF shown above ( ), AC caps are required on the TX lines. If routed USBSS_TX/RX directly to a peripheral, AC caps are needed on the peripheral TX lines as well.

  • Page 26: Usb 2.0 Design Guidelines

    Diff pair / SE 85-90 / 45-55 Ω ±15% Trace Spacing – for TX/RX non-interleaving TX-RX Xtalk is very critical in PCB trace routing. The ideal solution is to route TX and RX on different layers. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 18...
  • Page 27 Common-mode choke (not recommended – only used if absolutely required for EMI issues) See Chapter 15 for details on CMC if implemented. Component Order Chip ̶ AC capacitor (TX only) ̶ common mode choke ̶ Component order ESD ̶ Connector: See Figure 6-6. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 19...

  • Page 28: Figure 6-2. Il/Next Plot

    3. Place GND vias as symmetrically as possible to data pair vias. The following figures show the USB 3.0 interface signal routing requirements. Figure 6-2. IL/NEXT Plot Figure 6-3. Trace Spacing for TX/RX Non-Interleaving Figure 6-4. Via Structures NVIDIA Jetso n Nano DG-09502-001_v2.1 | 20...

  • Page 29: Common Usb Routing Guidelines

    PCBs/flexes must be used for the max trace and skew calculations. Keep critical USB related traces away from other signal traces or unrelated power traces/areas or power supply components. Table 6-6. Tegra USB 2.0 Signal Connections Jetson Nano Ball Name Type Termination Description USB[2:0]_D_P DIFF I/O 90Ω...

  • Page 30: Pcie

    PCIe controller that brings one interface up to four lanes to the ® ® module pins for use on the carrier board. A second single-lane PCIe interface is used on- module for Ethernet. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 22...

  • Page 31: Pcie Design Guidelines

    Configuration / device organization Load Topology Point-point Unidirectional, differential Termination Ω To GND Single Ended for P and N Impedance Trace Impedance diff / SE 85 / 50 Ω ±15%. See Note 1 Reference plane Spacing NVIDIA Jetso n Nano DG-09502-001_v2.1 | 23...
  • Page 32 3. Longer trace lengths may be possible if the total trace loss is equal to or better than the target. If the loss is greater, the max trace lengths will need to be reduced. 4. Do length matching before via transitions to different layers or any discontinuity to minimize common mode conversion. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 24...

  • Page 33: Figure 6-8. Ac Cap Voiding

    PCIE0_RX3_N/P (Lane 3) DIFF IN Series 0.1uF capacitors Differential Receive Data Pairs: Connect to RX_N/P pins of PCIe near Jetson Nano pins or connector or TX_N/P pin of PCIe device through AC cap PCIE0_RX2_N/P (Lane 2) according to supported configuration.

  • Page 34: Gigabit Ethernet

    − − Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. Tegra X1 SoC Technical Reference Manual The MPIO Pad Codes are described in the “Multi-Purpose I/O Pins and Pin Multiplexing (PinMux)”...

  • Page 35: Figure 6-10. Gigabit Ethernet Magnetics And Rj45 Connections

    Gigabit Ethernet MDI IF Pairs: Connect to Magnetics -/+ pins GBE_LED_LINK 110Ω series resistor Gigabit Ethernet Link LED: Connect to green LED on RJ45 connector GBE_LED_ACT 110Ω series resistor Gigabit Ethernet Activity LED: Connect to yellow LED on RJ45 connector NVIDIA Jetso n Nano DG-09502-001_v2.1 | 27...

  • Page 36: Chapter 7. Display

    CMOS – 1.8V Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The direction of GPIO07 is true when used for this function. Otherwise as a GPIO, the direction is bidirectional.

  • Page 37: Figure 7-1. Dsi 1 X 2 Lane Connection Example

    DSI_A_D1_P − Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. Tegra X1 SoC Technical Reference Manual The MPIO Pad Codes are described in the “Multi-Purpose I/O Pins and Pin Multiplexing (PinMux)”...

  • Page 38: Mipi Dsi And Csi Design Guidelines

    DSI display DSI_D[1:0]_N/P DIFF OUT DSI Differential Data Lanes 1:0: Connect to corresponding data lanes of DSI display. GPIO07 Optional LCD Backlight Pulse Width Modulation: Connect to LCD backlight solution PWM input if supported NVIDIA Jetso n Nano DG-09502-001_v2.1 | 30...

  • Page 39: Edp And Dp

    CMOS – 1.8V Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The direction for DP0_HPD is true when used for this function. Otherwise as a GPIO, the direction is bidirectional...

  • Page 40: Figure 7-2. Dp/Edp Connection Example On Dp0 Pins

    LANE_0P TPD4E 05U06 Notes: • Level shifter required on DP0_HPD to avoid the pin from being driven when Jetson Nano is off. The level shifter must be non-inverting (preserve the polarity of the HPD signal from the display). • Load Switch enable is from powergood pin of main 3.3V supply.

  • Page 41: Edp Routing Guidelines

    See Note 2. Max PCB via dist. from connector No requirement 7.63 (0.3) mm (in) RBR/HBR HBR2 Max trace length/delay from Jetson Nano TX to 175ps/inch assumption for stripline, 150ps/inch for connector microstrip. RBR/HBR (Stripline / Microstrip) 215 (1138)/215 (975) mm (ps) NVIDIA Jetso n Nano DG-09502-001_v2.1 | 33...
  • Page 42 3. Do not perform length matching within breakout region. Recommend doing trace length matching to <1ps before vias or any discontinuity to minimize common mode conversion. 4. The average of the differential signals is used for length matching. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 34...

  • Page 43: Figure 7-4. S-Parameter

    From module pin: 10kΩ pull-up to 1.8V, level shifter DP0_HPD eDP/DP: Hot Plug Detect: Connect to HPD pin on and 100kΩ pulldown on connector side of shifter and display connector through level shifter. ESD to GND. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 35...

  • Page 44: Hdmi And Dp

    Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The directions for DP1_HPD and HDMI_CEC are true when used for these functions. Otherwise as GPIOs, the direction is bidirectional...

  • Page 45: Hdmi

    3. The DP1_TXx pads are native DP pads and require series AC capacitors (ACCAP) and pull-downs (RPD) to be HDMI compliant. The 499Ω, 1% pull-downs must be disabled when Jetson Nano is off or in sleep mode to meet the HDMI VOFF requirement. The enable to the FET, enables the pull-downs when the HDMI interface is to be used.

  • Page 46: Figure 7-8. Hdmi Clk And Data Topology

    6GHz IL/FEXT plot: See Figure 7-9 TDR plot: See Figure 7-10 Impedance Trace impedance Diff pair Ω ±10%. Target is 100Ω. 95Ω for the breakout and main route is an implementation option. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 38...
  • Page 47 (seg A) Max distance between ESD and signal via Add-on Components Example of a case where space is limited for Top: See Figure 7-12 Bottom: See Figure 7-13 placing components. AC Cap NVIDIA Jetso n Nano DG-09502-001_v2.1 | 39...
  • Page 48 4. If routing includes a flex or 2nd PCB, the max trace delay and skew calculations must include all the PCBs/flex routing. Solutions with flex/2nd PCB may not achieve maximum frequency operation. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 40...

  • Page 49: Figure 7-9. Il And Fext Plot

    Display The following figures show the HDMI interface signal routing requirements. Figure 7-9. IL and FEXT Plot Figure 7-10. TDR Plot Figure 7-11. HDMI Via Topology Figure 7-12. Add-on Components – Top NVIDIA Jetso n Nano DG-09502-001_v2.1 | 41...

  • Page 50: Figure 7-13. Add-On Components - Bottom

    Display Figure 7-13. Add-on Components – Bottom Figure 7-14. AC Cap Void Figure 7-15. RPD, Choke, FET Placement Figure 7-16. ESD Footprint Figure 7-17. ESD Void NVIDIA Jetso n Nano DG-09502-001_v2.1 | 42...

  • Page 51: Figure 7-18. Smt Pad Trace Entering

    Adequate decoupling (0.1uF and 10uF recommended) on HDMI 5V supply to connector: Connect to +5V supply near connector and ESD to GND. on HDMI connector. Note: Any ESD and /or EMI solutions must support targeted modes (frequencies). NVIDIA Jetso n Nano DG-09502-001_v2.1 | 43...

  • Page 52: Dp On Dp1 Pins

    LANE_0P TPD4E 05U06 Notes: 1. Level shifter required on DP1_HPD to avoid the pin from being driven when Jetson Nano is off. The level shifter must be non-inverting (preserve the polarity of the HPD signal from the display). 2. Any EMI/ESD included on the HDMI_DP pins must be suitable for the highest frequency modes supported (<1pf capacitive load recommended).

  • Page 53: Dp Interface Signal Routing Requirements

    Adequate decoupling (0.1uF and 10uF DP supply to connector: Connect 3.3V supply recommended) on supply near connector. pin on DP connector to VDD_3V3_SYS. Note: Any ESD and/or EMI solutions must support targeted modes (frequencies). NVIDIA Jetso n Nano DG-09502-001_v2.1 | 45...

  • Page 54: Chapter 8. Mipi Csi Video Input

    Each data lane has a peak bandwidth of up to 1.5 Gbps. Note: In Table 8-1 and Table 8-2 the Direction column, the Output is from Jetson Nano and the Input is to Jetson Nano. Bidir is for bidirectional signals.

  • Page 55: Table 8-2. Jetson Nano Camera Miscellaneous Pin Description

    CSI4_D3_P CSI_D_D1_P Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. Tegra X1 SoC Technical Reference Manual The MPIO Pad Codes are described in the “Multi-Purpose I/O Pins and Pin Multiplexing (PinMux)”...

  • Page 56: Figure 8-1. 4 Lane Csi Camera Connection Example

    2. If CSI 0/1 and CSI 4 are used for 4-lane interfaces each, CSI 2 and CSI 2 can be used for two 1 or 2-lane interfaces. 3. Each 2-lane options shown above can also be used for one single lane camera. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 48...

  • Page 57: Figure 8-2. Available Cameral Control Pins

    Note: Any EMI/ESD devices must be tuned to minimize impact to signal quality and meet the timing and Vil/Vih requirements at the receiver and maintain signal quality and meet requirements for the frequencies supported by the design. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 49...

  • Page 58: Csi Design Guidelines

    I2C Table 8-4. address 7’h40. CAM[1:0]_MCLK 120Ω bead in series (on Jetson Nano) Camera Master Clocks: Connect to camera reference clock inputs. See note related to EMI/ESD under MIPI CSI Signal Connections table.

  • Page 59: Chapter 9. Sd Card And Sdio

    Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The directions for SDMMC_x and GPIO08 are true when used for these functions. Otherwise as GPIOs, the directions are bidirectional.

  • Page 60: Figure 9-1. Sd Card Connection Example

    SDR50 / SDR25 / SDR12 / HS / DS 16 (100) mm (ps) 139 (876) SDR104 / DDR50 16 (100) 83 (521) Max trace length/delay skew in/between CLK and See Note 3 CMD/DAT 14 (87.5) mm (ps) NVIDIA Jetso n Nano DG-09502-001_v2.1 | 52...

  • Page 61: Table 9-3. Sd Card And Sdio Signal Connections

    SD Card / SDIO Clock: Connect to CLK pin of device. SDMMC_CMD SD Card / SDIO Command: Connect to CMD pin of device SDMMC_D[3:0] SD Card / SDIO Data: Connect to Data pins of device NVIDIA Jetso n Nano DG-09502-001_v2.1 | 53...

  • Page 62: Chapter 10. Audio

    Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The directions for I2S[1:0]x and GPIO09 are true when used for those functions. Otherwise as GPIOs, the directions are bidirectional.

  • Page 63: Figure 10-1. Audio Codec Connection Example

    GPIOs that supports this function. 2.I2C2 supports 1.8V operation since the interface is pulled to 1.8V through 4.7kΩ resistors on the module. If another I2C interface on Jetson Nano is used, a level shifter will be required as all the others are 3.3V.

  • Page 64: Table 10-2. Interface Signal Routing Requirements

    I2S Data Output: Connect to data input pin of audio device. I2S[1:0]_DIN I2S Data Input: Connect to data output pin of audio device. GPIO09 Audio Codec Master Clock: Connect to clock pin of audio codec. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 56...

  • Page 65: Chapter 11. Miscellaneous Interfaces

    Open Drain – 1.8V the module. Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. Tegra X1 SoC Technical Reference Manual The MPIO Pad Codes are described in the “Multi-Purpose I/O Pins and Pin Multiplexing...

  • Page 66: I2C Design Guidelines

    11.1.1 I2C Design Guidelines Care must be taken to ensure I2C peripherals on same I2C bus connected to Jetson Nano do not have duplicate addresses. Addresses can be in two forms: 7-bit, with the read/write bit removed or 8-bit including the read/write bit. Be sure to compare I2C device addresses using the same form (all 7-bit or all 8-bit format).

  • Page 67: Spi

    2. For I2C interfaces that are pulled up to 1.8V, disable the E_IO_HV option for these pads. For I2C interfaces that are pulled up to 3.3V, enable the E_IO_HV option. The E_IO_HV option is selected in the Pinmux registers. 11.2 The Jetson Nano brings out two of the Tegra SPI interfaces. See Figure 11-2. Table 11-4. Jetson Nano SPI Pin Description...

  • Page 68: Figure 11-2. Spi Connections

    SPI 1 Chip Select 1 Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The directions for SPI[1:0]x are true when used for those functions. Otherwise as GPIOs, the directions are bidirectional.

  • Page 69: Spi Design Guidelines

    MOSI, MISO, SCK and CS Max trace length/delay skew from MOSI, MISO and CS to SCK 16 (100) mm (ps) At any point Note: Up to four signal vias can share a single GND return via. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 61...

  • Page 70: Uart

    Input Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The directions for UART[2:0]x are true when used for those functions. Otherwise as GPIOs, the direction is bidirectional. Tegra X1 SoC Technical Reference Manual The MPIO Pad Codes are described in the “Multi-Purpose I/O Pins and Pin Multiplexing...

  • Page 71: Fan

    Notes: In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. The directions for GPIO14 and GPIO08 are true when used for those functions. Otherwise as GPIOs, the directions are bidirectional.

  • Page 72: Debug

    Notes: 1. In the Type/Dir column, Output is from Jetson Nano. Input is to Jetson Nano. Bidir is for Bidirectional signals. 2. The direction for UART2_RXD is true when used for this function. Otherwise as a GPIO, the direction is bidirectional.

  • Page 73: Jtag

    1.Pull-ups or Pull-downs are present on the UART TX and RTS lines for RAM Code strapping. 2.If level shifter is implemented, pull-up is required on the RXD line on the non-Jetson Nano side of the level shifter. This is required to keep the input from floating and toggling when no device is connected to the debug UART.

  • Page 74: Debug Uart

    UART #2 Transmit: Connect to RX pin of serial device UART2_RXD If level shifter implemented, 100kΩ to supply UART #2 Receive: Connect to TX pin of on the non-Jetson Nano side of the device. serial device NVIDIA Jetso n Nano DG-09502-001_v2.1 | 66...

  • Page 75: Chapter 12. Pads

    If these signals need the pull-ups during Power-ON, external pull-up resistors should be added. The following list is the affected pins list. These are the Jetson Nano pins on the dual-voltage blocks powered at 1.8V with Power-ON reset default of Internal pull-up enabled.

  • Page 76: Pins Pulled And Driven High During Power-On

    The Jetson Nano is powered up before the carrier board (See Section 5.1). Table 12-1 lists the pins on Jetson Nano that default to being pulled or driven high. Care must be taken on the carrier board design to ensure that any of these pins that connect to devices on the carrier board (or devices connected to the carrier board) do not cause damage or excessive leakage to those devices.

  • Page 77: Chapter 13. Unused Interface Terminations

    Unused Multi-purpose Standard CMPS Pad Interfaces The following Jetson Nano pins (and groups of pins) are Tegra MPIO pins that support either special function IOs (SFIO) and/or GPIO capabilities. Any unused pins or portions of pin groups listed in Table 13-1 that are not used can be left unconnected.

  • Page 78: Chapter 14. Jetson Nano Pin Descriptions And Design Checklist

    Chapter 14. Jetson Nano Pin Descriptions and Design Checklist The Jetson Nano pin description and design checklist are attached to this design guide. To access the attached files, click the Attachment icon on the left-hand toolbar on this PDF (using Adobe Acrobat Reader or Adobe Acrobat). Select the file and use the Tool Bar options (Open, Save) to retrieve the documents.

  • Page 79: Chapter 15. General Routing Guidelines

    Signal Type Codes Code Definition Analog DIFF I/O Bidirectional Differential Input/Output DIFF IN Differential Input DIFF OUT Differential Output Bidirectional Input/Output Input Output Open Drain Output I/OD Bidirectional Input / Open Drain Output Power NVIDIA Jetso n Nano DG-09502-001_v2.1 | 71...

  • Page 80: Routing Guideline Format

    Each interface has different trace impedance requirements and spacing to other traces. It is up to designer to calculate trace width and spacing required to achieve specified SE and Diff impedances. Unless otherwise noted, trace impedance values are ±15%. NVIDIA Jetso n Nano DG-09502-001_v2.1 | 72...

  • Page 81: General Pcb Routing Guidelines

    Flex/ secondary PCB segment connected to main PCB. The max length/delay should be from Jetson Nano to the actual connector (i.e. USB, HDMI, etc.) or device (i.e. onboard USB device, Display driver IC, camera imager IC, etc.)

  • Page 82: Common High-Speed Interface Requirements

    Routing over voids not allowed except void around device ball/pin the signal is routed to. Noise Coupling Keep critical high-speed traces away from other signal traces or unrelated power traces/areas or power supply components NVIDIA Jetso n Nano DG-09502-001_v2.1 | 74...

  • Page 83: Figure 15-2. Common Mode Choke

    General Routing Guidelines The following figures are the common high-speed interface signal routing requirements figures. Figure 15-2. Common Mode Choke Figure 15-3. Serpentine NVIDIA Jetso n Nano DG-09502-001_v2.1 | 75...
  • Page 84 NVIDIA product and may result in additional or different conditions and/or requirements beyond those contained in this document. NVIDIA accept s no liability related to any default, damage, costs, or problem which may be based on or attributable to: (i) the use of the NVIDIA product in any manner that is contrary to this document or (ii) customer product designs.

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