Spi Design Guidelines; Figure 11-4. Spi Topologies; Table 11-5. Spi Interface Signal Routing Requirements - Nvidia Jetson Nano Product Design Manual

11.2.1

SPI Design Guidelines

Figure 11-4 shows the SPI topologies and Table gives the SPI interface signal routing
requirements.

Figure 11-4. SPI Topologies

Point-Point Topology
Jetson
Tegra
Main trunk

Table 11-5. SPI Interface Signal Routing Requirements

Parameter
Max frequency
Configuration / device organization
Max loading (total of all loads)
Reference plane
Breakout region impedance
Max PCB breakout delay
Trace impedance
Via proximity (signal to reference)
Trace spacing
Max trace length/delay (PCB main trunk)
For MOSI, MISO, SCK and CS 2x-load star/daisy
Max trace length/delay (Branch-A)
for MOSI, MISO, SCK and CS
Max trace length/delay skew from MOSI, MISO and CS to SCK
Note: Up to four signal vias can share a single GND return via.
NVIDIA Jetso n Nano
2x-Load Star Topology
Jetson
SPI
Tegra
Device
Main trunk
Microstrip / Stripline
Point-point
2x-load star/daisy
SPI
Device
Branch-A
#1
Jetson
SPI
Tegra
Device
Branch-B
#2
Requirement
65
4
15
GND
Minimum width and
spacing
75
50 – 60
< 3.8 (24)
4x / 3x dielectric
195 (1228)
120 (756)
75 (472)
16 (100)
Miscellaneous Interfaces
2x-Load Daisy Topology
SPI
Device
Branch-A
#1
Main trunk Branch-B
Units Notes
MHz
load
pF
ps
Ω ±15%
mm (ps) See note
mm (ps)
mm (ps)
mm (ps) At any point
DG-09502-001_v2.1 | 61
SPI
Device
#2