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Service Information
4.3
Principles of operation
The following paragraphs discuss the basic operating princi-
ples for the Model 7174A. A schematic diagram of the
matrix card may be found in drawings 9174-106 (mother
board) and 9174-126 (air matrix relay board) located at the
end of Section 5.
4.3.1 Block diagram
Figure 4-1 shows a simplified block diagram of the Model
7174A. Key elements include the buffer (U410), ID data cir-
cuits (U406, U408, and U410), relay drivers (U101 through
U113), relays (K101-K204), and the power-on safe guard
(U409). The major elements are discussed below.
4.3.2 ID data circuits
At power up, the card identification data information from
each card is read by the mainframe. This ID data includes
such information as card ID, hardware settling time for the
card, and a relay configuration table, which tells the main-
frame which relays to close for a specific crosspoint. This
configuration table is necessary because some cards (such as
the Model 7174A) require the closing of more than one relay
to close a specific crosspoint.
Address
Counter
U407
CLRADDR
To
Mainframe
Figure 4-1
Model 7174A block diagram
4-2
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ROM
A0-A11
D0-D7
U406
NEXTADDR
CARDSEL
IDDATA
Buffer
RELAYDATA
STROBE
U410
Power-On
Safeguard
U409
ID Data is contained within an on-card ROM, U406. In order
to read this information, the sequence below is performed
upon power up. Figure 4-2 shows the general timing of this
sequence.
1. The CARDSEL line is brought low, enabling the ROM
outputs. This line remains low throughout the ID data
transmission sequence.
2. The CLRADDR line is pulsed clearing the address
counter to zero. At this point, a ROM address of zero is
selected. This pulse occurs only once.
3. The NEXTADDR line is set low. NEXTADDR going
low increments the counter and enables parallel loading
of the parallel-to-serial converter. NEXTADDR is kept
low long enough for the counter to increment and the
ROM outputs to stabilize. This sequence functions
because the load input of the parallel-to-serial converter
is level sensitive rather than edge sensitive. The first
ROM address is location 1, not 0.
4. The CLK line clocks the parallel-to-serial converter to
shift all eight data bits from the converter to the main-
frame via the IDDATA line.
The process in steps 3 and 4 repeats until all the necessary
ROM locations have been read. A total of 498 bytes of infor-
mation are read by the mainframe during the card ID
sequence.
Parallel
to Serial
Converter
U408
NEXTADDR
CLK
Relay
Drivers
U101-U113
K101-K204
Output
Enable
Relays
Rows
A-H
Columns
1-12
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