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PC 6150/FPC6150 User's Manual
DRAM Timing By SPD
This item is selected depending on whether the board has paged
DRAMs or EDO (extended data output) DRAMs.
System BIOS Cacheable
Selecting "Enabled" allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
The choice: Enabled, Disabled.
Video RAM Cacheable
Selecting "Enabled" allows caching of the A/B segment, resulting in better
system performance.
The choice: Enabled, Disabled.
Memory Hole At 15M-16M
To improve performance, certain space in memory is reserved for ISA
cards. This memory must be mapped into the memory space below
16MB. The available choices are Enabled and Disabled.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select "Enabled" to support compliance with PCI
specification version 2.1.
AGP Aperture Size (MB)
The field sets aperture size of the graphics. The aperture is a portion of
the PCI memory address range dedicated for graphics memory address
space. Host cycles that hit the aperture range are forwarded to the AGP
without any translation. The options available are 4M, 8M, 16M, 32M,
64M, 128M and 256M.
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Appendix
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