Xycom XVME-100 Manual page 36

Ram/rom memory module
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X V M E - 1 0 0 M a n u a l
March, 1987
Signal
Mnemonic
BRO*-BR3*
DSO*
DS1*
D T A C K *
D00- D 1 5
G N D
Ta b l e A - 1 . V M E b u s S i g n a l I d e n t i f i c a t i o n ( c o n t ' d )
Connector
and
Pin N u m b e r
Signal N a m e a n d D e s c r i p t i o n
1B:12-15
BUS R E Q U E S T ( 0 - 3 ) : O p e n - c o l l e c t o r d r i v e n s i g n a l s
generated b y Requesters. T h e s e s i g n a l s i n d i c a t e t h a t a
D T B m a s t e r i n t h e d a i s y - c h a i n r e q u i r e s access t o t h e
bus.
1A:13
D A T A S T R O B E 0 : T h r e e -state d r i v e n s i g n a l t h a t
indicates d u r i n g b y t e a n d w o r d t r a n s f e r s t h a t a d a t a
t r a n s f e r w i l l o c c u r o n d a t a buss l i n e s (DOO-D07).
1A:12
D A T A S T R O B E 1 : T h r e e -state d r i v e n s i g n a l t h a t
indicates d u r i n g b y t e a n d w o r d t r a n s f e r s t h a t a d a t a
t r a n s f e r w i l l o c c u r o n d a t a b u s l i n e s (DO-D15).
1A:16
D A T A T R A N S F E R A C K N O W L E D G E : O p e n - c o l l e c t o r
d r i v e n s i g n a l g e n e r a t e d b y a D T B s l a v e . T h e f a l l i n g
edge o f t h i s s i g n a l i n d i c a t e s t h a t v a l i d d a t a i s a v a i l a b l e
on t h e d a t a b u s d u r i n g a r e a d c y c l e , o r t h a t d a t a h a s
been accepted f r o m t h e d a t a bus d u r i n g a w r i t e cycle.
1A:1-8
D A T A B U S ( b i t s 0 - 1 5 ) : T h r e e -state d r i v e n , b i -
1C:1-8
d i r e c t i o n a l d a t a l i n e s t h a t p r o v i d e a d a t a p a t h b e t w e e n
the D T B master a n d slave.
1A:9,11,
G R O U N D
15,17,19,
1B:20,23,
1C:9
2B:2,12,
22,31
A-3

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