Store Loop Adapter System Status Byte - IBM 4684 Store Loop Adapter/A Manual

5.11 Store Loop Adapter System Status Byte

This table describes the bits of the store loop adapter system status byte
(SSB). The values in the SSB represent the current state of the store
loop adapter hardware.
+------------------------------------------------------------------------+
¦ Table 5-5. Store Loop Adapter System Status Byte
+------------------------------------------------------------------------¦
¦ Bit ¦ Definition
+-------------+----------------------------------------------------------¦
¦ ¦ Reserved
¦ Bit 7 ¦
¦ (Read only) ¦
¦ ¦
+-------------+----------------------------------------------------------¦
¦ ¦ 1 = Generate(d) a store loop adapter POR.
¦ Bit 6 ¦ 0 = Reset the POR mechanism.
¦ (Read/write)¦
¦ ¦
+-------------+----------------------------------------------------------¦
¦ ¦ Reserved
¦ Bit 5 ¦
¦ (Read/write)¦
¦ ¦
+-------------+----------------------------------------------------------¦
¦ ¦ Reserved
¦ Bit 4 ¦
¦ (Read only) ¦
¦ ¦
+-------------+----------------------------------------------------------¦
¦ ¦ 1 = Enable the interrupt mechanism.
¦ Bit 3 ¦ 0 = Disable the interrupt mechanism.
¦ (Read/write)¦
¦ ¦
+-------------+----------------------------------------------------------¦
¦ ¦ 1 = Level 7 interrupt is active.
¦ Bit 2 ¦ 0 = Level 7 interrupt is inactive.
¦ (Read only) ¦
¦ ¦
+-------------+----------------------------------------------------------¦
¦ ¦ 1 = Shared buffer access is complete.
¦ Bit 1 ¦ 0 = Shared buffer return is complete.
¦ (Read/write)¦
¦ ¦
+-------------+----------------------------------------------------------¦
¦ ¦ 1 = Request(ed) shared buffer access.
¦ Bit 0 ¦ 0 = Shared buffer return is complete.
¦ (Read/write)¦
¦ ¦
+------------------------------------------------------------------------+
4684 Store Loop Adapter/A
Store Loop Adapter System Status Byte
¦ Copyright IBM Corp. 1991
5.11 - 1
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