Output Signals; Pixel Clock; Frame Valid Bit; Line Valid Bit - Basler A102k User Manual

Camera Interface

2.5 Output Signals

The camera's output signals include a pixel clock, video data, and video data qualifiers such as
frame valid and line valid. An integrate enabled output signal is also available. Sections
through 2.5.6

2.5.1 Pixel Clock

As shown in Figure 2-3 and in Table 2-3, the pixel clock is assigned to the TxClkIn (transmit clock)
pin of the Camera Link transmitter. The pixel clock is used to time the sampling and transmission
of pixel data as shown in Figure 2-4 and Figure 2-5. The transmitter used in A102
requires pixel data to be sampled and transmitted on the rising edge of the clock.
The frequency of the pixel clock is 28 MHz.
Note that the timing used for sampling the data at the Camera Link receiver in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.

2.5.2 Frame Valid Bit

As shown in Figure 2-4 and Figure 2-5, the frame valid bit indicates that a valid frame is being
transmitted.

2.5.3 Line Valid Bit

As shown in Figure 2-4 and Figure 2-5, the line valid bit indicates that a valid line is being
transmitted. Pixel data is only valid when the frame valid bit and the line valid bit are both high.

2.5.4 Data Valid Bit

The data valid bit is used for horizontal binning only (see Section 3.9.2). In normal operation, it is
always high and should be ignored.
2-8
DRAFT
describe the output signals.
2.5.1
cameras
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BASLER A102
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