Strong SRT8500 Service Manual page 26

6
1V5D
D
N3
[5]
B-MADR0
A0
P7
[5]
B-MADR1
A1
P3
[5]
B-MADR2
A2
N2
[5]
B-MADR3 A3
P8
[5]
B-MADR4 A4
[5] P2
B-MADR5 A5
[5] R8
B-MADR6 A6
[5] R2
B-MADR7 A7
[5] T8
B-MADR8
A8
R3
[5]
B-MADR9
A9
L7
[5]
B-MADR10
A10
R7
[5]
B-MADR11
A11
N7
[5]
B-MADR12
A12
[5] M2
M1-BA0 BA0
[5] N8
M1-BA1 BA1
[5] M3
M1-BA2 BA2
L2
/CS
J3
[5]
RASZM1
/RAS
K3
[5]
CASZM1
/CAS
L3
[5]
WEZM1
/WE
K1
[5]
B-ODT ODT
[5] M8
MVREF-CA VREFCA
C
J1
NC1
J9
NC2
L1
NC3
L9
NC4
M7
NC5
T3
[5]
B-MADR13
A13
T7
B-MADR14 NC7
R450
240R 1%
1V5D 1V5D
R451 C421
1K 1% 104
B [5]
MVREF-CA
R452 C422
1K 1% 104
1V5D
C426
C427 C428 C429
10uF
104 104 104
0805
A
5
D3
[5]
B-DQM1
DMU
C7
[5]
B-DQS1P
DQSU
B7
[5]
B-DQS1M
/DQSU
D7
[5]
DQU0 B-MDATA8
C3 [5]
DQU1 B-MDATA9
C8 [5]
DQU2 B-MDATA10
C2 [5]
DQU3 B-MDATA11
A7 [5]
B-MDATA12
DQU4
A2
[5]
B-MDATA13
DQU5
B8
[5]
B-MDATA14
DQU6
A3
[5]
B-MDATA15
DQU7
U402 E7 [5]
DML B-DQM0
F3 [5]
DQSL B-DQS0P
G3 [5]
DDR3_2Gbit_1600
/DQSL B-DQS0M
E3
[5]
DQL0 B-MDATA0
F7
[5]
B-MDATA1
DQL1
F2
[5]
B-MDATA2
DQL2
F8
[5]
B-MDATA3
DQL3
H3
[5]
DQL4 B-MDATA4
H8 [5]
DQL5 B-MDATA5
G2 [5]
DQL6 B-MDATA6
H7 [5]
DQL7 B-MDATA7
H1 [5]
VREFDQ MVREF-DQ
J7
[5]
M1_CLK+
CK K7
[5]
M1_CLK-
/CK
K9
[5]
M1-CKE
CKE
T2 [5]
/RESET B-RST
R453 C424
1K 1% 104
[5]
MVREF-DQ
R454 C423
1K 1% 104
C430 C431 C434 C435 C436 C437 C438
104 104 104 104 104 104 104
4
[3] R459 0R [5]
B_MADR13 B-MADR13
[3] R460 0R [5]
B_MADR9 B-MADR9
R461 0R
[3] [5]
B_BA0
M1-BA0
R462 0R
[3] [5]
M1_BA2
M1-BA2
[3] R463 0R [5]
B_RST
B-RST
[3] R464 0R [5]
B_MADR7 B-MADR7
[3] R465 0R [5]
B_MADR6 B-MADR6
[3] R466 0R [5]
B_MADR8 B-MADR8
R467 0R
[3] [5]
B_MADR10
B-MADR10
R468 0R
[3] [5]
B_BA1
M1-BA1
[3] R469 0R [5]
B_MADR3
B-MADR3
[3] R470 0R [5]
B_MADR5 B-MADR5
[3] R471 0R [5]
M1_CKE M1-CKE
R472 0R
[3] [5]
B_MADR12 B-MADR12
R473 0R
[3] [5]
B_MADR4 B-MADR4
R474 0R
[3] [5]
B_MADR11
B-MADR11
R475 0R
[3] [5]
B_MADR1
B-MADR1
[3] R476 0R [5]
B_CASZ CASZM1
[3] R477 0R [5]
B_RASZ RASZM1
[3] R478 0R [5]
B_MADR0 B-MADR0
R479 0R
[3] [5]
B_MADR2 B-MADR2
R480 0R
[3] [5]
B_ODT
B-ODT
R481 0R
[3] [5]
B_WEZ
WEZM1
[3] R482 0R [5]
B_MDATA11 B-MDATA11
[3] R483 0R [5]
B_MDATA13 B-MDATA13
[3] R484 0R [5]
B_MDATA15 B-MDATA15
[3] R485 0R [5]
B_MDATA9 B-MDATA9
R486 0R
[3] [5]
B_DQS1P
B-DQS1P
R487 0R
[3] [5]
B_DQS1M
B-DQS1M
[3] R488 0R [5]
B_MDATA12 B-MDATA12
[3] R489 0R [5]
B_MDATA8 B-MDATA8
[3] R490 0R [5]
B_MDATA14 B-MDATA14
R491 0R
[3] [5]
B_MDATA10 B-MDATA10
R492 0R
[3] [5]
B_DQM0
B-DQM0
R493 0R
[3] [5]
B_DQM1
B-DQM1
[3] R494 0R [5]
B_MDATA6 B-MDATA6
[3] R495 0R [5]
B_MDATA4 B-MDATA4
[3] R496 0R [5]
B_MDATA0 B-MDATA0
[3] R497 0R [5]
B_MDATA2 B-MDATA2
R498 0R
[3] [5]
B_DQS0M
B-DQS0M
R499 0R
[3] [5]
B_DQS0P
B-DQS0P
R449 0R
[3] [5]
B_MDATA1 B-MDATA1
[3] R448 0R [5]
B_MDATA3 B-MDATA3
R447 0R [5]
[3]
B_MDATA7 B-MDATA7
R446 0R [5]
[3]
B_MDATA5 B-MDATA5
R457 0R
[3] [5]
B_MCLK M1_CLK+
R458 0R
[3] [5]
B_MCLKZ M1_CLK-
R455 R456
100R 100R
C445
103
Place Close to DRAM
3 2
HISTORY OF MODIFICATIONS
REV.
1
2
Serial NOR FLASH
[5] A2
F_NCA2 NC
[5] A3
F_NCA3 NC
[5] A4
F_NCA4 NC
A5
NC
B1
F_NCB1 [5]
NC
B2
SPI_CLK [3,5]
SCK
B3
GND
B4
3V3_FLASH VCC
B5
NC
[5] C1
F_NCC1 NC
C2
[3,5]
SPI_CZ0 /CS
C3
[5]
RDBUSY RDY//BSY
C4
[3,5]
/FLASH_WP /WP
C5
NC
A1
NC
[5] A2
F_NCA2 NC
[5] A3
F_NCA3 NC
[5] A4
F_NCA4 NC
B1
[5]
F_NCB1 NC
B2
[3,5]
SPI_CLK SCLK
B3
GND
B4
3V3_FLASH VCC
[5] C1
F_NCC1 NC
[3,5] C2
SPI_CZ0 /CS
[5] C3
RDBUSY NC
[3,5] C4
/FLASH_WP /WP_SIO2
VCC3_3V_PM 3V3_FLASH
L481
FB/60R
0603
C482 C483
10uF 104
0805
Nand flash
VCC3_3V_PD 3V3_NAND
L482
FB/60R
0603
C484 C485
104 102
U406
Nand 128M
[3] H4
NF_D0 I/O0
J4
[3]
NF_D1 I/O1
K4
[3]
NF_D2
I/O2
K5
[3]
NF_D3 I/O3
K6
[3]
NF_D4 I/O4
J7
[3]
NF_D5 I/O5
[3] K7
NF_D6 I/O6
[3] J8
NF_D7 I/O7
1Gbit
NAND Flash (8-bit)
Shenzhen Jiuzhou Electric CO.,LD
DDR & FLASH
DESCRIPTION
DOC.NO.:
SCH P/N:
PCB P/N:
THIS DOCUMENT IS THE PROPERTY OF Shenzhen
Jiuzhou Electric CO.,LD. THE CONTENTS OF THIS
DOCUMENT ARECONFIDENTIAL AND CONTSTITUTE
TRADE SECERTSPROPRIETARY TO Shenzhen Jiuzhou
Electric CO.,LD.
NEITHER THIS DOCUMENT NOR ITS CONTENTS SHALL
BE DISCLOSED TO ANY UNAUTHORIZED PERSON.
COPIED OR PUBLISHED WITHOUT Shenzhen Jiuzhou
Electric CO.,LD.'S PRIOR WRITTEN
COPYRIGHT C 2011 Shenzhen Jiuzhou Electric CO.,LD
1
CHECK.BY APP.BY DATE
U403
M25PX64
E1 [5]
NC E2 F_NCE1
[5] D
NC E3 F_NCE2
[5]
NC E4 F_NCE3
[5]
NC E5
F_NCE4
NC
D1 [5]
NC D2 F_NCD1
[3,5]
SO D3 SPI_DO
[3,5]
SI D4 SPI_DI
Flash Reset
[5]
/RESET D5 3V3_FLASH
NC
U405
NC(MX25Lxx_55d) F1
NC
F2
NC
F3
NC
F4
NC
E1
[5]
NC E2 F_NCE1
[5]
NC E3 F_NCE2
[5]
NC E4 F_NCE3
[5]
NC F_NCE4
D1 [5]
NC D2 F_NCD1
[3,5] C
SO_SIO1 D3 SPI_DO
[3,5]
SI_SIO0 D4 SPI_DI
Flash Reset [5]
NC_SIO3 3V3_FLASH
B
D4 [3]
RE NF_REZ
C6 [3]
NF_CEZ
CE
D5
[3]
NF_CLE
CLE
C4
[3]
ALE NF_ALE
C7
[3]
WE NF_WEZ
C3 [3]
WP NF_WPZ
C8 [3]
R/B NF_RBZ
R425 4K7
3V3_NAND
R424
4K7
A
MODEL NO.:
PROJECT CODE:
DOC. REV.: V1.1
SIGN
DESIGNED BY: Xuewei 2011-12-19
DATE
SIGN
DRAWN BY:
DATE
SIGN
CHECKED BY:
DATE
SIGN
APPROVED BY:
DATE
CONSENT.
SIZE: A2 SHEET: 5 OF 11