Strong SRT8500 Service Manual page 24

6
C21
RF_AGC
D21
IF_AGC
F20
IM_Q
E20
IP_Q
G21
D IM_I
G20
IP_I
F21
AVSS_MPLL
TS1/I2S_OUT_IN/SPI/EJ
U20
TS1_CLK_/_I2S_IN_BCK_/_EJ_DINT_/_TMS_MCU
U19
TS1_D7_/_I2S_IN_WS_/_EJ_RST_/_TDO_MCU_/_
T20
TS1_D6_/_I2S_IN_D0_/_EJ_TCK_/_RX2
T21
TS1_D5_/_EJ_TMS
T19
TS1_D4_/_I2S_OUT_MUTE
R21
TS1_D3_/_I2S_OUT_BCK
R20
TS1_D2_/_I2S_OUT_D0_/_SPI_CLK
R19
TS1_D1_/_I2S_OUT_WS_/SPI_IRQ
P20
TS1_D0_/_I2S_OUT_D1_/_SPI_CSZ_/_EJ_TDO
P19
TS1_VLD_/_I2S_OUT_D2_/_SPI_MOSI_/_EJ_TDI
N20
TS1_SYNC_/_I2S_OUT_MCK_/_SPI_MISO_/_EJ_T
[8] N19
TS_CLK
TS0_CLK
M21
TS_D7
TS0_D7
M20
TS_D6
TS0_D6
M19
TS_D5
TS0_D5
L20
TS_D4
TS0_D4
L19
TS_D3
TS0_D3
K20
TS_D2 TS0_D2
K21
TS_D1 TS0_D1
[8] K19
TS_D0 TS0_D0
[8] J21
TS_VAL TS0_VLD
J20
[8]
TS_SYNC TS0_SYNC
H20
[3,8]
IIC-SDA
I2CM0_SDA
H19
[3,8]
IIC-SCL I2CM0_SCL
SM/CCIR_IN_OUT/EJ
C
[6] D1
SC0_AUX1 EJ_DINT_/_CIR_D7_/_SM_C4
[6] D2
SC0_AUX2 EJ_RST_/_CIR_D6_/_SM_C8
E2
[6]
EJ_TMS_/_CIR_D4_/_SM_CD
SC0DET
E3
[6]
SC0_5V/3V EJ_TCK_/_CIR_D5_/_SM_GPIO
F3
[6]
SC0RESET EJ_DO_/_CIR_D3_/_SM_RST
F2
[6]
SC0CMDVCC EJ_TDI_/_CIR_D2_/_SMC_VCC
[6] F1
SC0DATAIN EJ_TRSTN_/_CIR_D1_/_SM_IO
[6] G2
SC0CLK CIR_D0_/_SM_CLK
[5] B19
/FLASH_WP PM_GPIO0
[7] C16
RGB/CVBS PM_GPIO1
B16
[7]
16:9/4:3 PM_GPIO2
C15
[7]
TV/AV PM_GPIO3
A15
[10]
PD_CTRL PD_CTRL
B15
[8]
ANT_PWR_CTRL PM_GPIO5
D14
[8]
ANT_OVERLOAD PM_GPIO6
[10] D16
STATE PM_GPIO7
[7] D15
MUTE_CTRL PM_GPIO8
GPIO
[10] E17
POWER_KEY PM_GPIO9
[10] A16
IR IRIN
C20
SAR0
B17
[10]
FP_CLK
SAR1
C17
[10]
FP_DATA
SAR2
D17
[10]
FP_STB SAR3
[9] C10
ETH_RST VSYNC_/_ET_RST
A10
B SPDIF2_/_GPIO
[8] N21
FE_RST S_GPIO4
R18
S_GPIO3
Y10
[6]
/USB_CTRL
S_GPIO2
W10
[6]
USB_OCD S_GPIO1
G3
S_GPIO0_/_CIR_CLK
[3] A19
UART-RX UART_RX UART
[3] C18
UART-TX UART_TX
R420 33R B12
[9]
ET_TXD0 TXD0
R421 33R C11
[9]
ET_TXD1
TXD1
R422 33R B11
[9]
ET_TXEN
TXEN
A12
[9]
ET_TXCLK
TXCLK
C12
[9] ETH/GPIO
ET_RXD1 RXD1
A13
[9]
ET_RXD0 RXD0
[9] B13
ET_COL COL
[9] C13
ET_MDC MDC
[9] B14
ET_MDIO MDIO
B18
[3]
OSC_XIN XTAL_IN
[3] A18
OSC_XOUT
XTAL_OUT
[3] C14
SYS-RST RESET
A
5
U401-A
MSD5043-V60
A7
HDMI_CEC
B8
HSYNC_/_HDMI_HDP
A4
DEMOD HDMI_CH2_P
B4
HDMI_CH2_M
C4
HDMI_CH1_P
HDMI
B5
HDMI_CH1_M
C5
HDMI_CH0_P
B6
HDMI_CH0_M
A6
HDMI_CLK_P
C6
HDMI_CLK_M
B7
HDMI_SCL C7
HDMI_SDA
C2
DAC_B C1
VIDEO DAC_R B1
DAC_G B2
DAC_X
C3 R401
AVSS_DAC_BIAS
A3
AU_LINE_L
A2
AU_LINE_R
AUDIO
D3
TS0
SPDIF_OUT
B3
AU_VRM
I2C
B9
USB_DP_P2
A9
USB_DM_P2
B10
VBUS_P2
USB
W11
USB_DP_P0
Y11
USB_DM_P0
U401-B
MSD5043-V60
CIR_OUT_D7_/_CI_A14
CIR_OUT_D6_/_CI_A13
CIR_OUT_D5_/_CI_A12
CIR_OUT_D4_/_CI_A11
CIR_OUT_D3_/_CI_A10
CIR_OUT_D2_/_CI_A9
CIR_OUT_D1_/_CI_A8
CIR_OUT_D0_/_CI_A7
CIR_OUT_CLK_/_CI_A6
NF_RBZ_/_CI_A5
NF_REZ_/_CI_A2
NF_CEZ W18
NF_CLE_/_CI_A3
NF_ALE_/_CI_A0
NF_WEZ_/_CI_A1
NF_WPZ_/_CI_A4
NF_D0_/_CI_D0
NF_D1_/_CI_D1
NF_D2_/_CI_D2
NF_D3_/_CI_D3
NF_D4_/_CI_D4
NF_D5_/_CI_D5
NF_D6_/_CI_D6
NF_D7_/_CI_D7
CIR_IN_D7_/_CI_IORDN
CIR_IN_D6_/_CI_IOWRN
CIR_IN_D5_/_CI_OEN
CIR_IN_D4_/_CI_WEN
CIR_IN_D3_/_CI_REGN
CIR_IN_D2_/_CI_CEN
CIR_IN_D1_/_CI_IRQAN
CIR_IN_D0_/_CI_WAITN
CIR_IN_CLK_/_CI_RST
CI_CDN
SPI_CK B21
SPI SPI_DI B20
SPI_DO C19
SPI_CZ
4
[6]
HDMI_HPD
[6]
HDMI-TX2P
[6]
HDMI-TX2N
[6]
HDMI-TX1P
[6]
HDMI-TX1N
[6]
HDMI-TX0P
[6]
HDMI-TX0N
[6]
HDMI-TXCLKP
[6]
HDMI-TXCLKN
[6]
HDMI_SCL
[6]
HDMI_SDA
[3,7]
IDAC_OUT_B
[3,7]
IDAC_OUT_R
[3,7]
IDAC_OUT_G
[3,7]
IDAC_OUT_X
0R
[7]
LINE_OUTL
[7]
LINE_OUTR
[7]
SPDIF_OUT
L401 FB/60R
0603
[6]
USB1_DP
[6]
USB1_DM
AA12
W12
AA13
Y13
W13
Y14
W14
Y15
AA15
Y21 [5]
NF_RBZ
AA19 [5]
NF_REZ
W19
[5]
NF_CEZ
[5]
NF_CLE
Y19
[5]
NF_ALE
Y20
[5]
NF_WEZ
AA20
[5]
NF_WPZ
AA18 [5]
NF_D0
Y18 [5]
NF_D1
W17 [5]
NF_D2
Y17 [5]
NF_D3
W16
[5]
NF_D4
Y16
[5]
NF_D5
AA16
[5]
NF_D6
W15
[5]
NF_D7
V17
V18
U18 [3]
CI_OEZ
W20 [3]
CI_WEZ
V19 [3]
CI_REGZ
V16 [3]
CI_CEZ
W21
V21
V20
T18
A20 [5]
SPI_CLK
[5]
SPI_DI
[5]
SPI_DO
[5]
SPI_CZ0
3 2
HISTORY OF MODIFICATIONS
REV.
1
2
EEPROM
VCC3_3V_PD
U413
C412 104
1 8
A0 VCC
2 7
A1 WP
3 6 [3,8]
IIC-SCL
A2 SCL
4 5 [3,8]
GND SDA IIC-SDA
AT24C64N-SC27
Device address
E0/E1/E2=0/0/0
WRITE=A0H
READ=A1H
I2C PULL UP
VCC3_3V_PD
R426 R427
4K7 4K7
[3,8]
IIC-SDA
[3,8]
IIC-SCL
Shenzhen Jiuzhou Electric CO.,LD
MSD5043 GPIO & CONFIG
DESCRIPTION
DOC.NO.:
SCH P/N:
PCB P/N:
THIS DOCUMENT IS THE PROPERTY OF Shenzhen
Jiuzhou Electric CO.,LD. THE CONTENTS OF THIS
DOCUMENT ARECONFIDENTIAL AND CONTSTITUTE
TRADE SECERTSPROPRIETARY TO Shenzhen Jiuzhou
Electric CO.,LD.
NEITHER THIS DOCUMENT NOR ITS CONTENTS SHALL
BE DISCLOSED TO ANY UNAUTHORIZED PERSON.
COPIED OR PUBLISHED WITHOUT Shenzhen Jiuzhou
Electric CO.,LD.'S PRIOR WRITTEN
COPYRIGHT C 2011 Shenzhen Jiuzhou Electric CO.,LD
1
CHECK.BY APP.BY DATE
HW STRAP
close MStar IC
VCC3_3V_PD
R430 NC
[3] R431 1K
CI_OEZ
CHIP_CONFIG[3]
R432 NC
D
[3] R433 1K
CI_WEZ
CHIP_CONFIG[2]
R434 1K
[3] R435 NC
CI_REGZ
CHIP_CONFIG[1]
R436 1K
[3] R437 NC
CI_CEZ
CHIP_CONFIG[0]
CHIP_CONFIG[3~0]
0011: MIPS_no_EJ_NOR8
0100: MIPS_EJ1_NOR8
0101: MIPS_EJ2_NOR8
Debug
VCC3_3V_PM
CN401
1
R414 R415
10K 10K
2
[3] R412 100R 3
UART-RX
[3] R413 100R 4
UART-TX
4PIN 2.0MM
C
System Reset
VCC3_3V_PM
R408 D401
10K BAV99
CE402 47uF/16V
E
Q401
3906
R409 1K
B
HIGH ACTIVE
R411
C
[3]
SYS-RST
100R
C415 R410 C409
10K 2.2nF
10uF
0805
CRYSTAL
R403 33R [3]
OSC_XOUT
R402 1M
R405 0R [3]
OSC_XIN
B
Y401 24MHz
CRYSTAL SPEC:
C410 C411
24MHZ
33P 33P
CL=20PF
RR<30R
20PPM
VIDEO
R416 75R
[3,7]
IDAC_OUT_R
R417
[3,7] 75R
IDAC_OUT_G
R418
[3,7] 75R
IDAC_OUT_B
R419
[3,7] 82R
IDAC_OUT_X
A
MODEL NO.:
PROJECT CODE:
DOC. REV.: V1.1
SIGN
DESIGNED BY: Xuewei 2011-12-19
DATE
SIGN
DRAWN BY:
DATE
SIGN
CHECKED BY:
DATE
SIGN
APPROVED BY:
DATE
CONSENT.
SIZE: A2 SHEET: 3 OF 11