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Cypress CYW43353 Manual

Single-chip 5g mac/baseband/radio with integrated bluetooth 4.1 for automotive and industrial applications
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General Description
®
The Cypress
CYW43353 single-chip device provides the highest level of integration for Automotive and Industrial connectivity
systems with integrated single-stream IEEE 802.11ac MAC/baseband/radio, Bluetooth 4.1. In IEEE 802.11ac mode, the WLAN
operation supports rates of MCS0–MCS9 (up to 256 QAM) in 20 MHz, 40 MHz, and 80 MHz channels for data rates up to 433.3 Mbps.
In addition, all the rates specified in IEEE 802.11a/b/g/n are supported. Included on-chip are 2.4 GHz and 5 GHz transmit amplifiers,
and receive low-noise amplifiers. Optional external PAs, LNAs, and antenna diversity are also supported.
The CYW43353 offers an SDIO v3.0 interface for high speed 802.11ac connectivity. The Bluetooth host controller is interfaced over
a 4-wire high speed UART and includes PCM for audio.
The CYW43353 brings the latest mobile connectivity technology to automotive infotainment, telematics, rear seat entertainment, and
industrial applications. Offering automotive Grade 3 (-40C to +85C) temperature performance, the CYW43353 is tested to AECQ100
environmental stress guidelines and manufactured in ISO9001 and TS16949 certified facilities.
The CYW43353 implements highly sophisticated enhanced collaborative coexistence hardware mechanisms and algorithms, which
ensure that WLAN and Bluetooth collaboration is optimized for maximum performance. In addition, coexistence support for external
radios (such as LTE cellular, GPS, and WiMAX) is provided via an external interface. As a result, enhanced overall quality for
simultaneous voice, video, and data transmission is achieved.
Cypress Part Numbering Scheme
Cypress is converting the acquired IoT part numbers from Cypress to the Cypress part numbering scheme. Due to this conversion,
there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides
Cypress ordering part number that matches an existing IoT part number.
Table 1. Mapping Table for Part Number between Broadcom and Cypress
Broadcom Part Number
BCM43353
BCM43353LIUBG
Cypress Semiconductor Corporation
Document No. 002-14949 Rev. *E
PRELIMINARY
Single-Chip 5G MAC/Baseband/Radio with Integrated
Bluetooth 4.1 for Automotive and Industrial Applications
Cypress Part Number
CYW43353
CYW43353LIUBG
•
198 Champion Court
,
•
San Jose
CA 95134-1709
CYW43353
•
408-943-2600
Revised October 20, 2016

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Summary of Contents for Cypress CYW43353

  • Page 1 Cypress is converting the acquired IoT part numbers from Cypress to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number.
  • Page 2 PRELIMINARY CYW43353 Features IEEE 802.11x Key Features IEEE 802.11ac compliant. ™ ■ Integrated ARMCR4 processor with tightly cou- ■ pled memory for complete WLAN subsystem Single-stream spatial multiplexing up to 433.3 ■ functionality, minimizing the need to wake up the Mbps data rate.
  • Page 3 PRELIMINARY CYW43353 General Features Security: ■ Supports battery voltage range from 3.0V to 4.8 ™ ™ ■ and WPA2 (Personal) support for pow- ❐ supplies with internal switching regulator. erful encryption and authentication AES and TKIP in hardware for faster data ❐...

  • Page 4: Table Of Contents

    PRELIMINARY CYW43353 Contents 1. Overview ............6 5.7 Advanced Bluetooth/WLAN Coexistence ...26 5.8 Fast Connection (Interlaced Page and Inquiry 1.1 Overview ............. 6 Scans) ..............26 1.2 Features .............. 8 6. Microprocessor and Memory Unit for Bluetooth 1.3 Standards Compliance ........8 1.4 Automotive and Industrial Usage Model .....
  • Page 5 PRELIMINARY CYW43353 12. Pinout and Signal Descriptions..... 56 16.4 CLDO ..............90 16.5 LNLDO ...............91 12.1 Ball Maps ............56 12.2 Signal Descriptions ........... 57 17. System Power Consumption ......92 12.3 WLAN GPIO Signals and Strapping Options ..62 17.1 WLAN Current Consumption ......92 12.3.1 Multiplexed Bluetooth GPIO Signals ..

  • Page 6: Overview

    It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for platform flexibility in size, form, and function. The following figure shows the interconnect of all the major physical blocks in the CYW43353 and their associated external interfaces, which are described in greater detail in the following sections.
  • Page 7 PRELIMINARY CYW43353 Figure 1. CYW43353 Block Diagram SECI UART and GCI-GPIOs WL_HOST_WAKE WL_DEV_WAKE JTAG Other GPIOs WLAN RAM RAM768KB Sharing SDIOD ROM640KB SDIO 3.0 BT_HOST_WAKE UART BT_DEV_WAKE UART ARMCM3 ARMCR4 Other GPIOs BT Access WLAN WLAN AXI2AHB Master AHB2AXI Registers...

  • Page 8: Features

    PRELIMINARY CYW43353 1.2 Features The CYW43353 supports the following features: IEEE 802.11a/b/g/n/ac dual-band radio with virtual-simultaneous dual-band operation ■ Bluetooth v4.1 + EDR with integrated Class 1 PA ■ Concurrent Bluetooth and WLAN operation ■ On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality ■...

  • Page 9: Automotive And Industrial Usage Model

    1.4 Automotive and Industrial Usage Model The CYW43353 incorporates a number of unique features to simplify integration into automotive and industrial platforms. Its flexible PCM and UART interfaces enable it to transparently connect with existing platform circuits. In addition, the TCXO and LPO inputs allow the use of existing automotive and industrial features to further minimize the size, power, and cost of the complete system.

  • Page 10: Power Supplies And Power Management

    2.1 Power Supply Topology One buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43353. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs.
  • Page 11 PRELIMINARY CYW43353 Figure 2. Typical Power Topology for CYW43353 Internal LNLDO 1.2V WL RF – AFE Shaded areas are internal to the BCM 43353 80 mA Internal LNLDO 1.2V WL RF – TX (2.4 GHz, 5 GHz) 80 mA 1.2V Internal VCOLDO WL RF – LOGEN (2.4 GHz, 5 GHz) 80 mA Internal LNLDO 1.2V WL RF – RX/LNA (2.4 GHz, 5 GHz) 80 mA XTAL LDO 1.2V WL RF – XTAL 30 mA...

  • Page 12: Wlan Power Management

    All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW43353 integrated RAM is a high Vt memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the CYW43353 includes an advanced WLAN power management unit (PMU) sequencer.

  • Page 13: Power-Off Shutdown

    When the CYW43353 is powered on from this state, it is the same as a normal power-up, and the device does not retain any infor- mation about its state from before it was powered down.

  • Page 14: Frequency References

    In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 3.1 Crystal Interface and Clock Generation The CYW43353 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscil- lator, including all external components, is shown in Figure 3.

  • Page 15: External Frequency Reference

    Figure 4. The internal clock buffer connected to this pin will be turned off when the CYW43353 goes into sleep mode. When the clock buffer turns on and off, there will be a small impedance variation. Power must be supplied to the WRF_XTAL_BUCK_VDD1P5 pin.

  • Page 16: Frequency Selection

    19.2, 19.8, 24, 26, 33.6, 37.4, and 38.4 MHz, but also other frequencies in this range with an approximate resolution of 80 Hz. The CYW43353 must have the reference frequency set correctly in order for any of the UART or PCM interfaces to function correctly, since all bit timing is derived from the reference frequency.

  • Page 17: External 32.768 Khz Low-Power Oscillator

    PRELIMINARY CYW43353 3.4 External 32.768 kHz Low-Power Oscillator The CYW43353 uses a secondary low-frequency clock for low-power-mode timing. An external 32.768 kHz precision oscillator is required. Use a precision external 32.768 kHz clock that meets the requirements listed in Table Table 3.

  • Page 18: Bluetooth Subsystem Overview

    The CYW43353 is the optimal solution for any Bluetooth voice and/or data application. The Bluetooth subsystem presents a stan- dard Host Controller Interface (HCI) via a high-speed UART and PCM for audio. The CYW43353 incorporates all Bluetooth 4.1 fea- tures including Secure Simple Pairing, Sniff Subrating, and Encryption Pause and Resume.

  • Page 19: Bluetooth Radio

    4.2 Bluetooth Radio The CYW43353 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band.

  • Page 20: Receiver Signal Strength Indicator

    CYW43353 4.2.7 Receiver Signal Strength Indicator The radio portion of the CYW43353 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband, so that the control- ler can determine whether the transmitter should increase or decrease its output power.

  • Page 21: Bluetooth Baseband Core

    (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet bound- ary flag (PBF) enhancements. 5.2 Bluetooth Low Energy The CYW43353 supports the Bluetooth Low Energy operating mode. Document No. 002-14949 Rev. *E Page 21 of 113...

  • Page 22: Link Control Layer

    ❐ 5.4 Test Mode Support The CYW43353 fully supports Bluetooth Test mode as described in Part I:1 of the Specification of the Bluetooth System Version 3.0. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence.

  • Page 23: Bluetooth Power Management Unit

    5.5.2 Host Controller Power Management When running in UART mode, the CYW43353 may be configured so that dedicated signals are used for power management hand- shaking between the CYW43353 and the host. The basic power saving functions supported by those handshaking signals include the standard Bluetooth defined power savings modes and standby modes of operation.

  • Page 24: Bbc Power Management

    ■ operational. When the CYW43353 is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This allows the CYW43353 to effectively be off while keeping the I/O pins powered so they do not draw extra current from any other devices connected to the I/O.

  • Page 25: Wideband Speech

    Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system and enables the CYW43353 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes.

  • Page 26: Audio Rate-Matching Algorithms

    5.5.8 Multiple Simultaneous A2DP Audio Streams The CYW43353 has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows a user to share his or her music (or any audio stream) with a friend.

  • Page 27: Microprocessor And Memory Unit For Bluetooth

    6.2 Reset The CYW43353 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT power-on reset (POR) circuit is out of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the POR circuit is held in reset.

  • Page 28: Bluetooth Peripheral Transport Unit

    The CYW43353 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW43353 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to sup- port various data formats on the PCM interface.
  • Page 29 PRELIMINARY CYW43353 Figure 8. Functional Multiplex Data Diagram 1 frame BT SCO 1 Rx BT SCO 2 Rx BT SCO 3 Rx FM right FM left PCM_OUT BT SCO 1 Tx BT SCO 2 Tx BT SCO 3 Tx PCM_IN...

  • Page 30: Pcm Interface Timing

    PRELIMINARY CYW43353 7.1.6 PCM Interface Timing 7.1.6.1. Short Frame Sync, Master Mode Figure 9. PCM Timing Diagram (Short Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE PCM_IN Table 5. PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Ref No.
  • Page 31 PRELIMINARY CYW43353 7.1.6.2. Short Frame Sync, Slave Mode Figure 10. PCM Timing Diagram (Short Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE PCM_IN Table 6. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode) Ref No. Characteristics Minimum Typical Maximum...
  • Page 32 PRELIMINARY CYW43353 7.1.6.3. Long Frame Sync, Master Mode Figure 11. PCM Timing Diagram (Long Frame Sync, Master Mode) PCM_BCLK PCM_SYNC PCM_OUT HIGH IMPEDANCE Bit 0 Bit 1 Bit 0 Bit 1 PCM_IN Table 7. PCM Interface Timing Specifications (Long Frame Sync, Master Mode) Ref No.
  • Page 33 PRELIMINARY CYW43353 7.1.6.4. Long Frame Sync, Slave Mode Figure 12. PCM Timing Diagram (Long Frame Sync, Slave Mode) PCM_BCLK PCM_SYNC PCM_OUT Bit 0 HIGH IMPEDANCE Bit 1 Bit 0 Bit 1 PCM_IN Table 8. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode) Ref No.

  • Page 34: Uart Interface

    Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW43353 UARTs operate correctly with the host UART as long as the combined baud rate error of the two devices is within ±2%.
  • Page 35 PRELIMINARY CYW43353 Figure 13. UART Timing UART_CTS_N UART_TXD Midpoint of STOP bit Midpoint of STOP bit UART_RXD UART_RTS_N Table 10. UART Timing Specifications Ref No. Characteristics Min. Typ. Max. Unit Delay time, UART_CTS_N low to UART_TXD valid – – Bit period Setup time, UART_CTS_N high before midpoint of stop bit –...

  • Page 36: S Interface

    S WS is low, and right-channel data is transmitted when I S WS is high. Data bits sent by the CYW43353 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK.
  • Page 37 PRELIMINARY CYW43353 The system clock period T must be greater than T and T because both the transmitter and receiver have to be able to handle the data transfer rate. 2. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t and t are specified with respect to T.
  • Page 38 PRELIMINARY CYW43353 Figure 15. I S Receiver Timing > 0.35T > 0.35 = 2.0V = 0.8V > 0.2T > 0 SD and WS T = Clock period = Minimum allowed clock period for transmitter T > T Document No. 002-14949 Rev. *E Page 38 of 113...

  • Page 39: Wlan Global Functions

    8.3 GPIO Interface The following number of general-purpose I/O (GPIO) pins are available on the WLAN section of the CYW43353 that can be used to connect to various external devices: WLBGA package – 9 GPIOs ■...

  • Page 40: External Coexistence Interface

    16550 UART, and provides a FIFO size of 64 × 8 in each direction. 8.6 JTAG Interface The CYW43353 supports the IEEE 1149.1 JTAG boundary scan standard for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and character- ization test tools during board bringup.

  • Page 41: Wlan Host Interfaces

    CYW43353 9. WLAN Host Interfaces 9.1 SDIO v3.0 The CYW43353 WLAN section supports SDIO version 3.0, including the new UHS-I modes: DS: Default speed (DS) up to 25 MHz, including 1- and 4-bit modes (3.3V signaling). ■ HS: High speed up to 50 MHz (3.3V signaling).

  • Page 42: Generic Spi Mode

    SDIO host’s internal pull-ups 9.2 Generic SPI Mode In addition to the full SDIO mode, the CYW43353 includes the option of using the simplified generic SPI (gSPI) interface/protocol. Characteristics of the gSPI mode include: Supports up to 48 MHz operation ■...

  • Page 43: Spi Protocol

    PRELIMINARY CYW43353 9.2.1 SPI Protocol The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianness is supported in both modes. Figure 20 Figure 21 show the basic write and write/read commands. Figure 20. gSPI Write Protocol Figure 21. gSPI Read Protocol Document No.
  • Page 44 PRELIMINARY CYW43353 9.2.1.1. Command Structure The gSPI command structure is 32 bits. The bit positions and definitions are as shown in Figure Figure 22. gSPI Command Structure BCM_SPID Command Structure Ad dres s – 17 bits Ad dres s – 17 bits...
  • Page 45 PRELIMINARY CYW43353 9.2.1.5. Status The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information about any packet errors, protocol errors, information about available packet in the RX queue, etc. The status information helps in reducing the number of interrupts to the host.
  • Page 46 PRELIMINARY CYW43353 Figure 24. gSPI Signal Timing with Status (Response Delay = 0; 32-bit Big Endian) Write sclk mosi miso Command 32 bits Write Data 16*n bits Status 32 bits Write‐Read sclk mosi miso Read Data 16*n bits Status 32 bits Command 32 bits Read sclk mosi miso Command 32 bits Read Data 16*n bits Status 32 bits Table 13. gSPI Status Field Details...

  • Page 47: Gspi Host-Device Handshake

    To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW43353 is ready for data trans- fer.
  • Page 48 PRELIMINARY CYW43353 Table 14. gSPI Registers (Cont.) Address Register Access Default Description x0004 Interrupt register Requested data not available; Cleared by writing a 1 to this location F2/F3 FIFO underflow due to last read F2/F3 FIFO overflow due to last write...
  • Page 49 PRELIMINARY CYW43353 Figure 25. WLAN Boot-Up Sequence VBAT* VDDIO WL_REG_ON < 950 µs VDDC (from internal PMU) < 104 ms  Internal POR After a fixed delay following Internal POR and WL_REG_ON going high,  < 4 ms  the device responds to host F0 (address 0x14) reads. Device requests for reference clock 8 ms  After 8 ms the reference clock is  assumed to be up.  Access to PLL  registers is possible. Host Interaction: Host polls F0 (address 0x14) until it reads a  predefined pattern. Host sets wake‐up‐wlan bit and  waits 8 ms, the maximum time for  reference clock availability. After 8 ms, host programs PLL  registers to set crystal frequency Chip active interrupt is asserted after the PLL locks Host downloads  code. *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. Document No. 002-14949 Rev. *E...

  • Page 50: Wireless Lan Mac And Phy

    10. Wireless LAN MAC and PHY 10.1 IEEE 802.11ac MAC The CYW43353 WLAN MAC is designed to support high-throughput operation with low-power consumption. It does so without com- promising the Bluetooth coexistence policies, thereby enabling optimal performance over both networks. In addition, several power saving modes have been implemented that allow the MAC to consume very little power while maintaining network-wide timing syn- chronization.

  • Page 51: Psm

    PRELIMINARY CYW43353 10.1.1 PSM The programmable state machine (PSM) is a micro-coded engine, which provides most of the low-level control to the hardware, to implement the IEEE 802.11 specification. It is a microcontroller that is highly optimized for flow control operations, which are pre- dominant in implementations of communication protocols.

  • Page 52: Ifs

    PSM to configure and control the PHY. 10.2 IEEE 802.11ac PHY The CYW43353 WLAN Digital PHY is designed to comply with IEEE 802.11ac and IEEE 802.11a/b/g/n single-stream specifications to provide wireless LAN connectivity supporting data rates from 1 Mbps to 433.3 Mbps for low-power, high-performance handheld applications.
  • Page 53 PRELIMINARY CYW43353 The key PHY features include: Programmable data rates from MCS0–9 in 20 MHz, 40 MHz, and 80 MHz channels, as specified in IEEE 802.11ac ■ Supports Optional Short GI mode in TX and RX ■ TX and RX LDPC for improved range and power efficiency ■...

  • Page 54: Wlan Radio Subsystem

    11. WLAN Rad io Subs yste m The CYW43353 includes an integrated dual-band WLAN RF transceiver that has been optimized for use in 2.4 GHz and 5 GHz Wireless LAN systems. It has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM or 5 GHz U-NII bands.
  • Page 55 PRELIMINARY CYW43353 Figure 28. Radio Functional Block Diagram W L D AC W L P A W L P AD W L PG A W L TX LP F W L TX G ‐M ixer W L D A C W L A ‐P A W L A ‐PA D W L A‐P G A...

  • Page 56: Pinout And Signal Descriptions

    PRELIMINARY CYW43353 12. Pinout and Signal Descriptions 12.1 Ball Maps Figure 29 shows the WLBGA ball map. Figure 29. 145-Ball WLBGA (Top View) NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT NO CONNECT SR_PVSS...

  • Page 57: Signal Descriptions

    PRELIMINARY CYW43353 12.2 Signal Descriptions The signal name, type, and description of each pin in the CYW43353 is listed in Table 15. The symbols shown under Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any.
  • Page 58 JTAG select. Pull high to select the JTAG interface. If the JTAG interface is not used, this pin may be left floating or connected to ground. Note: See Table 21, “CYW43353 GPIO/SDIO Alternative Signal Functions,” for the JTAG signal pins. Clocks WRF_XTAL_IN XTAL oscillator input.
  • Page 59 BT analog GPIO pin. Miscellaneous WL_REG_ON Used by PMU to power up or power down the internal CYW43353 regulators used by the WLAN section. Also, when deasserted, this pin holds the WLAN section in reset. This pin has an internal 200 kΩ...
  • Page 60 PRELIMINARY CYW43353 Table 15. WLBGA Signal Descriptions (Cont.) WLBGA Ball# Signal Name Type Description LNF_VDD1P2 Connect to VOUT_LNLDO Output (pin E2). LNF_VDD1P2 Connect to VOUT_LNLDO Output (pin E2). WLAN Supplies WRF_WL_LNLDOIN_VDD1P5 LNLDO 1.35V supply. WRF_SYNTH_VBAT_VDD3P3 Synth VDD 3.3V supply. WRF_PADRV_VBAT_VDD3P3 PA Driver VBAT supply.
  • Page 61 PRELIMINARY CYW43353 Table 15. WLBGA Signal Descriptions (Cont.) WLBGA Ball# Signal Name Type Description WRF_PFD_GND1P2 Ground. D7, D11, E3, E8, J5, K4 VSSC Core ground for WLAN and BT. SR_PVSS Power ground. PMU_AVSS Quiet ground. AGND12PLL/HSIC_AGNDPLL PLL ground. BT_PAVSS Bluetooth PA ground.

  • Page 62: Wlan Gpio Signals And Strapping Options

    PRELIMINARY CYW43353 12.3 WLAN GPIO Signals and Strapping Options The pins listed in Table 16 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table.

  • Page 63: Multiplexed Bluetooth Gpio Signals

    BT_GPIO_3 is set to pad function 0). When the Pad Function Control register is set to 0, the BT_GPIOs do not have specific functions assigned to them and behave as generic GPIOs. The A_GPIO_X pins described below are multiplexed behind the CYW43353's PCM and I S interface pins.
  • Page 64 PRELIMINARY CYW43353 Table 20. Multiplexed GPIO Signals Pin Name Type Description UART_CTS_N Host UART clear to send. UART_RTS_N Device UART request to send. UART_RXD Device UART receive data. UART_TXD Host UART transmit data. PCM_IN PCM data input. PCM_OUT PCM data output.

  • Page 65: Gpio/Sdio Alternative Signal Functions

    PRELIMINARY CYW43353 12.4 GPIO/SDIO Alternative Signal Functions Table 21. CYW43353 GPIO/SDIO Alternative Signal Functions Pins WLBGA SDIO GPIO_0 WL_HOST_WAKE GPIO_1 WL_DEV_WAKE GPIO_2 TCK, GCI_GPIO_1, or UART RX GPIO_3 TMS or GCI_GPIO_0 GPIO_4 TDI or SECI_IN GPIO_5 TDO or SECI_OUT GPIO_6...

  • Page 66: I/O States

    PRELIMINARY CYW43353 12.5 I/O States The following notations are used in Table I: Input signal ■ O: Output signal ■ I/O: Input/Output signal ■ PU = Pulled up ■ PD = Pulled down ■ NoPull = Neither pulled up nor pulled down ■...
  • Page 67 PRELIMINARY CYW43353 Table 22. I/O States (Cont.) Power-down Out-of-Reset; (WL_REG_ON High (BT_REG_ON and Before SW Download and BT_REG_ON = Keeper Low Power State/Sleep WL_REG_ON Held (BT_REG_ON High; 0) and VDDIOs Are Name Active Mode (All Power Present) Low) WL_REG_ON High)
  • Page 68 PRELIMINARY CYW43353 Keeper column: N = pad has no keeper. Y = pad has a keeper. Keeper is always active except in Power-down state. If there is no keeper, and it is an input and there is Nopull, then the pad should be driven to prevent leakage due to floating pad (SDIO_CLK, for example).

  • Page 69: Dc Characteristics

    PRELIMINARY CYW43353 13. DC Ch aracteristics 13.1 Absolute Maximum Ratings Caution! The absolute maximum ratings in Table 23 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device.

  • Page 70: Electrostatic Discharge Specifications

    PRELIMINARY CYW43353 13.3 Electrostatic Discharge Specifications Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging.
  • Page 71 – – The CYW43353 is functional across this range of voltages. Optimal RF performance specified in the data sheet, however, is guaranteed only for 3.13V < VBAT < 4.8V. The maximum continuous voltage is 4.8V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative duration over the lifetime of the device are allowed.

  • Page 72: Bluetooth Rf Specifications

    PRELIMINARY CYW43353 14. Bluetooth RF Specifications Unless otherwise stated, limit values apply for the conditions specified in Table 24, “Environmental Ratings,” Table 26, “Recom- mended Operating Conditions and DC Characteristics,”. Typical values apply for the following conditions: VBAT = 3.6V ■...
  • Page 73 PRELIMINARY CYW43353 Table 27. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit C/I image channel GFSK, 0.1% BER – –31 – C/I 1-MHz adjacent to image channel GFSK, 0.1% BER – –46 – /4–DQPSK, 0.1% BER C/I co-channel –...
  • Page 74 PRELIMINARY CYW43353 Table 27. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit 824–849 MHz WCDMA – –11.4 – 880–915 MHz E-GSM – –10.4 – 880–915 MHz WCDMA – –10.2 – 1710–1785 MHz GSM1800 – –15.8 – 1710–1785 MHz WCDMA –...
  • Page 75 PRELIMINARY CYW43353 Table 27. Bluetooth Receiver RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Spurious Emissions 30 MHz–1 GHz – –95 –62 1–12.75 GHz – –70 –47 851–894 MHz – –147 – dBm/Hz 925–960 MHz – –147 – dBm/Hz 1805–1880 MHz...
  • Page 76 PRELIMINARY CYW43353 Table 28. Bluetooth Transmitter RF Specifications (Cont.) Parameter Conditions Minimum Typical Maximum Unit Out-of-Band Noise Floor 65–108 MHz FM RX – –147 – dBm/Hz 776–794 MHz CDMA2000 – –147 – dBm/Hz 869–960 MHz cdmaOne, GSM850 – –147 –...
  • Page 77 PRELIMINARY CYW43353 Table 29. Local Oscillator Performance Parameter Minimum Typical Maximum Unit LO Performance s Lock time – – Initial carrier frequency tolerance – ±25 ±75 Frequency Drift DH1 packet – ±8 ±25 DH3 packet – ±8 ±40 DH5 packet –...

  • Page 78: Wlan Rf Specifications

    15. WLAN RF Sp ecifications 15.1 Introduction The CYW43353 includes an integrated dual-band direct conversion radio that supports the 2.4 GHz and the 5 GHz bands. This sec- tion describes the RF characteristics of the 2.4 GHz and 5 GHz radio.

  • Page 79: Wlan 2.4 Ghz Receiver Performance Specifications

    Note: The specifications in Table 32 are specified at the RF port and include the use of an external FEM with LNA from Cypress’s approved-vendor list (AVL), unless otherwise specified. Results with FEMs that are not on Cypress’s AVL are not guaranteed.
  • Page 80 PRELIMINARY CYW43353 Table 32. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit RX sensitivity IEEE 802.11ac 40 MHz channel spacing for all MCS rates MCS0 – –91.5 – a,5. (10% PER for 4096 octet PSDU)
  • Page 81 PRELIMINARY CYW43353 Table 32. WLAN 2.4 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Adjacent channel rejection—DSSS Desired and interfering signal 30 MHz apart (Difference between interfering and 1 Mbps DSSS –74 dBm – – desired signal at 8% PER for 1024 2 Mbps DSSS –74 dBm...

  • Page 82: Wlan 2.4 Ghz Transmitter Performance Specifications

    CYW43353 15.4 WLAN 2.4 GHz Transmitter Performance Specifications Note: The specifications in Table 33 include the use of the CYW43353's internal PAs and are specified at the chip port. Table 33. WLAN 2.4 GHz Transmitter Performance Specifications Minimu Maximu Parameter...

  • Page 83: Wlan 5 Ghz Receiver Performance Specifications

    Note: The specifications in Table 34 are specified at the RF port and include the use of an external FEM with LNA from Cypress’s approved-vendor list (AVL), unless otherwise specified. Results with FEMs that are not on Cypress’s AVL are not guaranteed.
  • Page 84 PRELIMINARY CYW43353 Table 34. WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit RX sensitivity IEEE 802.11ac 40 MHz channel spacing for all MCS rates (10% PER for 4096 octet PSDU) MCS0 – –90.5 – Defined for default parameters: 800 ns MCS1 –...
  • Page 85 PRELIMINARY CYW43353 Table 34. WLAN 5 GHz Receiver Performance Specifications (Cont.) Parameter Condition/Notes Minimum Typical Maximum Unit Maximum receive level @ 6, 9, 12 Mbps –9.5 – – @ 5.24 GHz @ 18, 24, 36, 48, 54 Mbps –14.5 –...

  • Page 86: Wlan 5 Ghz Transmitter Performance Specifications

    CYW43353 15.6 WLAN 5 GHz Transmitter Performance Specifications Note: The specifications in Table 34 include the use of the CYW43353's internal PAs and are specified at the chip port. Table 35. WLAN 5 GHz Transmitter Performance Specifications Parameter Condition/Notes Minimum...

  • Page 87: General Spurious Emissions Specifications

    PRELIMINARY CYW43353 15.7 General Spurious Emissions Specifications Table 36. General Spurious Emissions Specifications Parameter Condition/Notes Min. Typ. Max. Unit Frequency range – 2400 – 2500 General Spurious Emissions TX emissions 30 MHz < f < 1 GHz RBW = 100 kHz –...

  • Page 88: Ldo (Ldo3P3)

    PRELIMINARY CYW43353 Table 37. Core Buck Switching Regulator (CBUCK) Specifications (Cont.) Specification Notes Min. Typ. Max. Units Input supply voltage ramp-up 0 to 4.3V – – µs time The maximum continuous voltage is 4.8V. Voltage transients up to 6.0V (for up to 10 seconds), cumulative duration over the lifetime of the device, are allowed.

  • Page 89: Ldo (Btldo2P5)

    PRELIMINARY CYW43353 16.3 2.5V LDO (BTLDO2P5) Table 39. BTLDO2P5 Specifications Specification Notes Min. Typ. Max. Units Input supply voltage Min. = 2.5V + 0.2V = 2.7V. Dropout voltage requirement must be met under maximum load for performance specifications. Nominal output voltage Default = 2.5V.

  • Page 90: Cldo

    PRELIMINARY CYW43353 16.4 CLDO Table 40. CLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, V Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement 1.35 must be met under maximum load. Output current – – Output voltage, V Programmable in 25 mV steps.

  • Page 91: Lnldo

    PRELIMINARY CYW43353 16.5 LNLDO Table 41. LNLDO Specifications Specification Notes Min. Typ. Max. Units Input supply voltage, Vin Min. = 1.2V + 0.15V = 1.35V dropout voltage requirement 1.35 must be met under maximum load. Output current – – Output voltage, V Programmable in 25 mV steps.

  • Page 92: System Power Consumption

    17.1 WLAN Current Consumption Table 42 shows the typical, total current consumed by the CYW43353. To calculate total-solution current consumption for designs using external PAs, LNAs, and/or FEMs, add the current consumption of the external devices to the numbers in...
  • Page 93 PRELIMINARY CYW43353 Table 42. Typical WLAN Current Consumption (CYW43353 Current Only) (Cont.) VBAT = 3.6V, VDDIO = 1.8V, T 25°C Bandwidth Band Mode (MHz) (GHz) Vbat, mA , μA Active Modes with External PAs (TX Output Power is –5 dBm at the Chip Port)

  • Page 94: Bluetooth Current Consumption

    PRELIMINARY CYW43353 17.2 Bluetooth Current Consumption The Bluetooth BLE current consumption measurements are shown in Table Note: The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table ■ The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm.

  • Page 95: Interface Timing And Ac Characteristics

    PRELIMINARY CYW43353 18. Interface Ti ming and AC Characteristics 18.1 SDIO/gSPI Timing 18.1.1 SDIO Default Mode Timing SDIO default mode timing is shown by the combination of Figure 32 Table Figure 32. SDIO Bus Timing (Default Mode) SDIO_CLK Input Output...

  • Page 96: Sdio High-Speed Mode Timing

    PRELIMINARY CYW43353 18.1.2 SDIO High-Speed Mode Timing SDIO high-speed mode timing is shown by the combination of Figure 33 Table Figure 33. SDIO Bus Timing (High-Speed Mode) 50% VDD SDIO_CLK Input Output ODLY Table 45. SDIO Bus Timing Parameters (High-Speed Mode)

  • Page 97: Sdio Bus Timing Specifications In Sdr Modes

    PRELIMINARY CYW43353 18.1.3 SDIO Bus Timing Specifications in SDR Modes 18.1.3.1. Clock Timing Figure 34. SDIO Clock Timing (SDR Modes) SDIO_CLK Table 46. SDIO Bus Clock Timing Parameters (SDR Modes) Parameter Symbol Minimum Maximum Unit Comments – – SDR12 mode –...
  • Page 98 PRELIMINARY CYW43353 18.1.3.2. Device Input Timing Figure 35. SDIO Bus Input Timing (SDR Modes) SDIO_CLK CMD input DAT[3:0] input Table 47. SDIO Bus Input Timing Parameters (SDR Modes) Symbol Minimum Maximum Unit Comments SDR104 Mode – = 10 pF, VCT = 0.975V CARD –...
  • Page 99 PRELIMINARY CYW43353 18.1.3.3. Device Output Timing Figure 36. SDIO Bus Output Timing (SDR Modes up to 100 MHz) SDIO_CLK ODLY CMD output DAT[3:0] output Table 48. SDIO Bus Output Timing Parameters (SDR Modes up to 100 MHz) Symbol Minimum Maximum Unit Comments –...

  • Page 100: Sdio Bus Timing Specifications In Ddr50 Mode

    PRELIMINARY CYW43353 Table 49. SDIO Bus Output Timing Parameters (SDR Modes 100 MHz to 208 MHz) Symbol Minimum Maximum Unit Comments Card output phase ∆t –350 +1550 Delay variation due to temp change after tuning 0.60 – =2.88 ns @208 MHz ∆t...
  • Page 101 PRELIMINARY CYW43353 Table 50. SDIO Bus Clock Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments – – DDR50 mode – – 0.2 × tCLK < 4.00 ns (max) @50 MHz, C = 10 pF CARD Clock duty cycle –...
  • Page 102 PRELIMINARY CYW43353 Table 51. SDIO Bus Timing Parameters (DDR50 Mode) Parameter Symbol Minimum Maximum Unit Comments Input CMD Input setup time – < 10pF (1 Card) CARD Input hold time – < 10pF (1 Card) CARD Output CMD Output delay time –...

  • Page 103: Gspi Signal Timing

    PRELIMINARY CYW43353 18.1.5 gSPI Signal Timing The gSPI host and device always use the rising edge of clock to sample data. Figure 41. gSPI Timing Table 52. gSPI Timing Parameters Parameter Symbol Minimum Maximum Units Note Clock period 20.8 –...

  • Page 104: Power-Up Sequence And Timing

    VDDIO in-rush current on the order of 36 mA during the next PMU cold start. The CYW43353 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after ■...

  • Page 105: Control Signal Timing Diagrams

    PRELIMINARY CYW43353 19.1.2 Control Signal Timing Diagrams Figure 42. WLAN = ON, Bluetooth = ON 32.678 kHz  Sleep Clock 90% of VH VBAT* VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high  before VBAT is high. Figure 43. WLAN = OFF, Bluetooth = OFF 32.678 kHz  Sleep Clock VBAT* VDDIO WL_REG_ON...
  • Page 106 PRELIMINARY CYW43353 Figure 44. WLAN = ON, Bluetooth = OFF 32.678 kHz  Sleep Clock 90% of VH VBAT* VDDIO ~ 2 Sleep cycles WL_REG_ON 100 ms BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds.  2. VBAT should be up before or at the same time as VDDIO. VDDIO should NOT be present first or be held high before VBAT is high. 3. Ensure that BT_REG_ON is driven high at the same time as or before WL_REG_ON is driven high.  BT_REG_ON can be driven low 100 ms after WL_REG_ON goes high. Figure 45. WLAN = OFF, Bluetooth = ON 32.678 kHz  Sleep Clock 90% of VH VBAT* VDDIO ~ 2 Sleep cycles WL_REG_ON BT_REG_ON *Notes: 1. VBAT should not rise 10%–90% faster than 40 microseconds or slower than 10 milliseconds. ...

  • Page 107: Package Information

    PRELIMINARY CYW43353 20. Package Information 20.1 Package Thermal Characteristics Table 54. Package Thermal Characteristics Characteristic WLBGA  32.9 (°C/W) (value in still air)  2.56 (°C/W)  0.98 (°C/W)  (°C/W) 3.30  (°C/W) 9.85 Maximum Junction Temperature T (°C) Maximum Power Dissipation (W) 1.119...

  • Page 108: Mechanical Information

    PRELIMINARY CYW43353 21. Mechanical Info rmation Figure 46. 145-Ball WLBGA Package Mechanical Information Document No. 002-14949 Rev. *E Page 108 of 113...
  • Page 109 PRELIMINARY CYW43353 Figure 47. WLBGA Keep-out Areas for PCB Layout—Bottom View with Balls Facing Up Note: No top-layer metal is allowed in keep-out areas. Document No. 002-14949 Rev. *E Page 109 of 113...

  • Page 110: Ordering Information

    Cypress provides a wealth of data at http://www.cypress.com/internet-things-iottto help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of infor- mation, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates.

  • Page 111: Document History Page

    PRELIMINARY CYW43353 Document History Page Document Title: CYW43353 Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and In- dustrial Applications Document Number: 002-14949 Orig. of Submission Revision Description of Change Change Date 07/02/2013 43353-DS100-R Initial release 04/02/2014 43353-DS101-R Updated: •...
  • Page 112 PRELIMINARY CYW43353 Document Title: CYW43353 Single-Chip 5G MAC/Baseband/Radio with Integrated Bluetooth 4.1 for Automotive and In- dustrial Applications Document Number: 002-14949 05/28/2014 43353-DS102-R Updated: • The Features listed in the front matter of the document. • By changing all instances of Bluetooth 4.0 to Bluetooth 4.1 throughout the document.

  • Page 113: Sales, Solutions, And Legal Information

    ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products.

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