Casio TE-7000S Service Manual page 34

Pin Names Type Pin#
WE1# I 78
CS# I 74
BCLK I 71
BS# I 75
RD/WR# I 79
RD# I 76
WAIT# O 2
RESET# I 73
Cell RESET#
State
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the write enable signal for
the upper data byte (WE1#).
• For MC68K #1, this pin inputs the upper data strobe (UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
CS Input • For Generic #1, this pin inputs the write enable signal for the
upper data byte (WE1#).
• For Generic #2, this pin inputs the byte enable signal for the
high data byte (BHE#).
C Input This pin inputs the chip select signal.
C Input This pin inputs the system bus clock.
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the bus start signal (BS#).
• For MC68K #1, this pin inputs the address strobe (AS#).
CS Input • For MC68K #2, this pin inputs the address strobe (AS#).
• For Generic #1, this pin must be tied to V SS.
• For Generic #2, this pin must be tied to IO V DD.
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the RD/WR# signal.
The S1D13705 needs this signal for early decode of the bus cycle.
• For MC68K #1, this pin inputs the R/W# signal.
CS Input • For MC68K #2, this pin inputs the R/W# signal.
• For Generic #1, this pin inputs the read command for the upper
data byte (RD1#).
• For Generic #2, this pin must be tied to IO V DD.
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the read signal (RD#).
• For MC68K #1, this pin must be tied to IO V DD .
• For MC68K #2, this pin inputs the bus size bit 1 (SIZ1).
CS Input • For Generic #1, this pin inputs the read command for the lower
data byte (RD0#).
• For Generic #2, this pin inputs the read command (RD#).
This pin has multiple functions.
• For SH-3 mode, this pin outputs the wait request signal (WAIT#).
• For SH-4 mode, this pin outputs the device ready signal (RDY#).
• For MC68K #1, this pin outputs the data transfer
acknowledge signal (DTACK#).
TS2 Hi-Z • For MC68K #2, this pin outputs the data transfer and size
acknowledge bit 1 (DSACK1#).
• For Generic #1, this pin outputs the wait signal (WAIT#).
• For Generic #2, this pin outputs the wait signal (WAIT#).
CS 0 Active low input to set all internal registers to the default state and
to force all signals to their inactive states.
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Description