Casio TE-7000S Service Manual page 25

5-7-2. Block Diagram
MMU
TLB
CCN
CACHE
H-UDI
INTC
CPG/WDT
Legend:
ADC: A/D converter
AUD: Advanced user debugger
BSC: Bus state controller
CACHE: Cache memory
CCN: Cache memory controller
CMT: Compare match timer
CPG/WDT: Clock pulse generator/watchdog timer
CPU: Central processing unit
DAC: D/A converter
BRIDGE
External bus
interface
DMAC:
H-UDI:
INTC:
MMU:
RTC:
SCI:
SCIF:
TLB:
TMU:
UBC:
— 23 —
CPU
SCI
UBC
TMU
AUD
RTC
BSC
SCIF
DMAC
ADC
CMT
DAC
I/O port
Direct memory access controller
Hitachi user-debugging interface
Interrupt controller
Memory management unit
Realtime clock
Serial communication interface (with smart card interface)
Serial communication interface (with FIFO)
Address translation buffer
Timer unit
User break controller