Signal Timing Diagrams - Siemens SIMATIC SIMOSTEP 1FL3041 Functional Description

4 Signal description
4.3

Signal timing diagrams

4-4
The timing diagrams below illustrate the timing of the input/output signals
of the pulse and signal interfaces.
Figure 4-1 ENABLE/READY timing diagram
Figure 4-2 PULSE/DIR/GATE_N timing diagram
Figure 4-3 PWM or ENABLE and motor phase current timing diagram
GATE_N
MSTILL
100ms
Figure 4-4 GATE_N/MSTILL timing diagram
180ms
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FM-STEPDRIVE/SIMOSTEP (FB)
02.05