NL865H2 Hardware Design Guide SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE NOTICE While reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein.
NL865H2 Hardware Design Guide USAGE AND DISCLOSURE RESTRICTIONS License Agreements The software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement.
NL865H2 Hardware Design Guide 1. INTRODUCTION Scope This document introduces the Telit NL865H2 modules and presents possible and recommended hardware solutions for developing a product based on this module. All the features and solutions detailed in this document are applicable to all NL865H2 variants, where NL865H2 refers to the variants listed in the applicability table.
NL865H2 Hardware Design Guide Text Conventions Danger – This information MUST be followed or catastrophic equipment failure or bodily injury may occur. Caution or Warning – Alerts the user to important points about integrating the module, if these points are not followed, the module and end user equipment may fail or malfunction.
NL865H2 Hardware Design Guide 2. GENERAL PRODUCT DESCRIPTION Overview The NL865H2 is part of a new generation of modules in Telit’s NBIoT module portfolio. With its compact LGA footprint, it is designed for those m2m applications requiring miniature foot print. It is a multi band LTE NBIoT communication product based on the market’...
NL865H2 Hardware Design Guide Target market NL865H2 can be used for telematics applications where tamper-resistance, confidentiality, integrity, and authenticity of end-user information are required, for example: • Telematics services • Road pricing • Pay-as-you-drive insurance • Stolen vehicles tracking • Internet connectivity Main features Function...
NL865H2 Hardware Design Guide Temperature Range Condition Range Note The module is fully functional(*) within this 3GPP temperature Operating Temperature Range -20°C to +55°C range and meets 3GPP specifications. The module is fully functional(*) within this temperature range. The RF Performance may deviate from 3GPP requirements in this extended range.
NL865H2 Hardware Design Guide 3. PINS ALLOCATION Warning: NL865H2 is adopting a modified 56-pin xL865 Form Factor, pin to pin compatible with the previous 48-pin xL865 FF and with 8 additional pads. The numbering of the pins has been changed accordingly and attention has to be paid when comparing with previous 48-pin xL865 FF design.
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NL865H2 Hardware Design Guide USB 1.1 (Debug Port) USB_D+ USB differential Data (+) USB_D- USB differential Data (-) Compliant to VUSB VUSB Power sense for the internal USB transceiver. from USB V1.1 specification (from 4.4 V to 5.5V) SIM card interface External SIM signal –...
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NL865H2 Hardware Design Guide ADC_IN1 Analog To Digital converter Input #1 10-bit, range 0-1.4V ADC_IN2 Analog To Digital converter Input #2 10-bit, range 0-1.4V RF Section MAIN ANTENNA Main Antenna (50 ohm) Miscellaneous Functions WAKE* Input Command for PSM Wake Up CMOS 1.8V Falling edge trigger RESET*...
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NL865H2 Hardware Design Guide If not used, almost all pins should be left disconnected. The only exceptions are the following pins: Signal Note VBATT VBATT_PA 21, 23, 27, 35, 38, 39, 41, 42, 54 MAIN ANTENNA C103/TXD C104/RXD C105/RTS C106/CTS SIMVCC SIMRST SIMCLK...
NL865H2 Hardware Design Guide 4. POWER SUPPLY The power supply circuitry and board layout are a very important part in the full product design and they strongly reflect on the product overall performances, hence read carefully the requirements and the guidelines that will follow for a proper design. Power Supply Requirements The external power supply must be connected to VBATT &...
NL865H2 Hardware Design Guide Operating Modes This module has three operating modes, which can determine availability of functions for different levels of power-saving. Mode Function Active In active mode, all functions of the module are available and all processors are active.
NL865H2 Hardware Design Guide Power Consumption The table below shows the operating power consumption of the NL865H2-W1 in different operating modes. Status Description Average Max. value Unit AT+CFUN=0 Turn off radio and SIM power PSM mode Power Save Mode 4.238 IDLE Idle mode Band1,Pout=23dBm...
NL865H2 Hardware Design Guide Band66,Pout=23dBm Band71,Pout=23dBm Band85,Pout=23dBm General Design Rules The principal guidelines for the Power Supply Design embrace three different design steps: • the electrical design • the thermal design • the PCB layout. 4.4.1. Electrical Design Guidelines The electrical design of the power supply depends strongly from the power source where this power is drained.
NL865H2 Hardware Design Guide The reference circuit is as follow: 4.4.1.2. Battery Source Power Supply Design Guidelines The desired nominal output for the power supply is 3.3V and the maximum voltage allowed is 3.63V. • A Bypass low ESR capacitor of adequate capacity must be provided in order to cut the current absorption peaks, a 100μF tantalum capacitor is usually suited.
NL865H2 Hardware Design Guide 4.4.2. Thermal Design Guidelines The thermal design for the power supply heat sink should be done considering the values described in the “Power Consumption” chapter. Considering the very low current during idle, especially if Power Saving function is enabled, it is possible to consider from the thermal point of view that the device absorbs current significantly only during calls.
NL865H2 Hardware Design Guide 4.4.3. Power Supply PCB layout Guidelines As seen on the electrical design guidelines the power supply shall have a low ESR capacitor on the output to cut the current peaks and a protection diode on the input to protect the supply from spikes and polarity inversion.
NL865H2 Hardware Design Guide VAUX Power Output A regulated power supply output is provided in order to supply small devices from the module. The signal is in common with the PWRMON (module powered ON indication) function. This output is always active when the module is powered ON. The operating range characteristics of the supply are: Item Typical...
NL865H2 Hardware Design Guide 5. DIGITAL SECTION Logic Levels ABSOLUTE MAXIMUM RATINGS: Parameter Input level on any digital pin (CMOS 1.8) with respect -0.3V 2.1V to ground OPERATING RANGE – INTERFACE LEVELS (1.8V CMOS): Parameter Input high level 1.35V 1.98V Input low level -0.3V 0.63V...
NL865H2 Hardware Design Guide Power On The NL865H2-W1 module is automatically powering on itself when supplied. NOTE: To check if the device has powered on, the hardware line VAUX/PWRMON should be monitored. The power-off duration is required to be at least 5s before the module is powered on.
NL865H2 Hardware Design Guide The RST timing is shown in the following figure below: 5.3.2. Operating levels RESET* line is connected to VBATT with a Pull Up so the electrical levels on this pin are aligned to the main supply level. WARNING: The hardware unconditional Reset must not be used during normal operation of the device since it does not detach the device from the network.
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NL865H2 Hardware Design Guide The non-1.8V RST reference circuit design is shown below. NOTE: In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the NE865H2 when the module is powered off or during a reboot transition.
NL865H2 Hardware Design Guide WAKEUP from PSM 5.1.1. Pin Description The module is provided by an input line named WAKE* used to wakeup the module from the deep power saving state (PSM). The signal is active LOW. The following figure is the signal waveform: 5.1.2.
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NL865H2 Hardware Design Guide When the WAKEUP on the MCU side is 3.3V or other level domain, the reference circuit design is shown below. The resistor and capacitance in Figure are only the recommended value and they need to be tuned according to the specific customer’s application. After the module is woken up by the WAKEUP key, it will sleep again after 5 seconds without doing other services.
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NL865H2 Hardware Design Guide The following flowchart is describing the WAKE procedure: “Modem Wake Proc” START VBATT>3V? PWMRON = ON? WAKE * =Low GOTO “HW SHUTDOWN Delay = 4 ms unconditional” WAKE*=High PWMRON = ON? Delay 1s GOTO “Start AT CMD.” “Modem Wake Proc”...
NL865H2 Hardware Design Guide Communication ports The NL865H2-W1 module is provided with by 2 Asynchronous serial ports: • MODEM SERIAL PORT 1 (Main) • MODEM SERIAL PORT 2 (Auxiliary) Several configurations can be designed for the serial port on the OEM hardware, but the most common are: •...
In order to avoid a back powering effect it is recommended to avoid having any HIGH logic level signal applied to the digital pins of the NL865H2 when the module is powered off or during an ON/OFF transition. Refer to NL865H2 series AT command reference guide for port configuration. 1VV0301616 Rev. 7...
NL865H2 Hardware Design Guide 5.2.1.3. RS232 LEVEL TRANSLATION In order to interface the module with a PC com port or a RS232 (EIA/TIA-232) application a level translator is required. This level translator must: • invert the electrical signal in both directions; •...
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NL865H2 Hardware Design Guide Second solution could be done using a MAXIM transceiver TXS0104E. In this case, there is no need to use a single chip level translator: NOTE: In this case has to be taken in account the length of the lines on the application to avoid problems in case of High-speed rates on RS232.
NL865H2 Hardware Design Guide 5.2.2. 3.3V/5V UART level translation If the customer’s application uses a microcontroller with a serial port (UART) that works at a voltage different from 1.8V, then a circuitry has to be provided to adapt the different levels of the two set of signals.
NL865H2 Hardware Design Guide General purpose I/O The NL865H2-W1 module is provided by a set of Configurable Digital Input / Output pins (CMOS 1.8) Input pads can only be read; they report the digital value (high or low) present on the pad at the read time.
NL865H2 Hardware Design Guide NOTE: The internal GPIO’s pull up/pull down could be set to the preferred status for the application using the AT#GPIO command. Please refer for the AT Commands User Guide for the detailed command Syntax. 5.3.1. Using a GPIO as INPUT The GPIO pads, when used as inputs, can be connected to a digital output of another device and report its status, provided this device has interface levels compatible with the 1.8V CMOS levels of the GPIO.
NL865H2 Hardware Design Guide 5.3.3. Indication of network service availability The STAT LED status shows information on the network service availability and Call status. In the NL865H2-W1 modules, the STAT LED needs an external transistor to drive an external LED. Therefore, the status indicated in the following table is reversed with respect to the pin status.
NL865H2 Hardware Design Guide External SIM Holder SIM circuit reference design is as follows. The minimum value of Capacitor on SIMVCC is 1uF. ADC Converter The NL865H2-W1 is provided by two AD converters. They are able to read a voltage level in the range of 0÷1.4 volts applied on the ADC pin input, store and convert it into 10 bit word.
NL865H2 Hardware Design Guide 6. RF SECTION Antenna requirements 6.1.1. Main Antenna The antenna connection and board layout design are the most important aspect in the full product design as they strongly affect the product overall performances, hence read carefully and follow the requirements and the guidelines for a proper design. The antenna and antenna transmission line on PCB for a Telit NL865H2-W1 device shall fulfil the following requirements: Item...
NL865H2 Hardware Design Guide 6.1.2. PCB Design guidelines When using the NL865H2-W1, since there’s no antenna connector on the module, the antenna must be connected to the NL865H2-W1 antenna pad by means of a transmission line implemented on the PCB. In the case the antenna is not directly connected at the antenna pad of the NL865H2-W1, then a PCB line is needed in order to connect with it or with its connector.
NL865H2 Hardware Design Guide • If you don’t have EM noisy devices around the PCB of NL865H2-W1, by using a micro strip on the superficial copper layer for the antenna line, the line attenuation will be lower than a buried one; 6.1.2.1.
NL865H2 Hardware Design Guide 6.1.2.2. Transmission Line Measurements An HP8753E VNA (Full-2-port calibration) has been used in this measurement session. A calibrated coaxial cable has been soldered at the pad corresponding to RF output; a SMA connector has been soldered to the board in order to characterize the losses of the transmission line including the connector itself.
NL865H2 Hardware Design Guide Insertion Loss of G-CPW line plus SMA connector is shown below: 6.1.2.3. Antenna Installation Guidelines • Install the antenna in a place covered by the LTE signal. • The Antenna must be installed to provide a separation distance of at least 20 cm from all persons and must not be co-located or operating in conjunction with any other antenna or transmitter;...
NL865H2 Hardware Design Guide 7. MECHANICAL DESIGN NOTE: Dimensions in mm. General Tolerance ±0.15mm, The tolerance is not cumulative. 1VV0301616 Rev. 7 Page 49 of 67 2020-04-20...
NL865H2 Hardware Design Guide 8. APPLICATION PCB DESIGN General The NL865H2 modules have been designed to be compliant with a standard lead-free SMT process. Footprint 1VV0301616 Rev. 7 Page 50 of 67 2020-04-20...
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NL865H2 Hardware Design Guide In order to easily rework the NL865H2 is suggested to consider on the application a 1.5 mm placement inhibit area around the module. It is also suggested, as common rule for an SMT component, to avoid having a mechanical part of the application in direct contact with the module.
NL865H2 Hardware Design Guide PCB pad design Non solder mask defined (NSMD) type is recommended for the solder pads on the PCB. Copper Pad Solder Mask NSMD (Solder Mask Defined) (Non Solder Mask Defined) PCB pad dimensions It is not recommended to place via or micro-via not covered by solder resist in an area of 0.3 mm around the pads unless it carries the same signal of the pad itself (see following figure).
NL865H2 Hardware Design Guide Holes in pad are allowed only for blind holes and not for through holes. Recommendations for PCB pad surfaces: Finish Layer thickness [µm] Properties 3 –7 / 0.03 – 0.15 Electro-less Ni / good solder ability protection Immersion Au The PCB must be able to resist the higher temperatures which are occurring at the lead- free process.
NL865H2 Hardware Design Guide Solder paste Item Lead Free Solder Paste Sn/Ag/Cu We recommend using only “no clean” solder paste in order to avoid the cleaning of the modules after assembly. Solder Reflow Recommended solder reflow profile: Warning: The above solder reflow profile represents the typical SAC reflow limits and does not guarantee adequate adherence of the module to the customer application throughout the temperature range.
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NL865H2 Hardware Design Guide Profile Feature Pb-Free Assembly Average ramp-up rate (T to T 3°C/second max Preheat – Temperature Min (Tsmin) 150°C – Temperature Max (Tsmax) 200°C – Time (min to max) (ts) 60-180 seconds Tsmax to TL – Ramp-up Rate 3°C/second max Time maintained above: –...
NL865H2 Hardware Design Guide PACKAGING Is possible to order in two packaging system: • Package on tray • Package on reel Tray The NL865H2 modules are packaged on trays of 40 pieces each. These trays can be used in SMT processes for pick & place handling. 1VV0301616 Rev.
NL865H2 Hardware Design Guide Reel The NL865H2 can be packaged on reels of 200 pieces each. See figure for module positioning into the carrier. 1VV0301616 Rev. 7 Page 58 of 67 2020-04-20...
NL865H2 Hardware Design Guide Moisture sensitivity The moisture sensitivity level of the Product is “3” according with standard IPC/JEDEC J-STD-020, take care of all the relative requirements for using this kind of components. Moreover, the customer has to take care of the following conditions: a) The shelf life of the Product inside of the dry bag is 12 months from the bag seal date, when stored in a non-condensing atmospheric environment of <...
NL865H2 Hardware Design Guide SAFETY RECOMMENDATIONS READ CAREFULLY Be sure the use of this product is allowed in the country and in the environment required. The use of this product may be dangerous and has to be avoided in the following areas: •...
NL865H2 Hardware Design Guide CONFORMITY ASSESSMENT ISSUES Approvals RoHS and REACH Declaration of Conformity The DoC is available here: https://www.telit.com/RED/ 1VV0301616 Rev. 7 Page 61 of 67 2020-04-20...
NL865H2 Hardware Design Guide SAFETY RECOMMENDATIONS READ CAREFULLY Be sure the use of this product is allowed in the country and in the environment required. The use of this product may be dangerous and has to be avoided in the following areas: •...
NL865H2 Hardware Design Guide ACRONYMS TTSC Telit Technical Support Centre Universal Serial Bus High Speed Data Terminal Equipment UMTS Universal Mobile Telecommunication System WCDMA Wideband Code Division Multiple Access HSDPA High Speed Downlink Packet Access HSUPA High Speed Uplink Packet Access UART Universal Asynchronous Receiver Transmitter HSIC...
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NL865H2 Hardware Design Guide Master Input – Slave Output MISO Clock MRDY Master Ready SRDY Slave Ready Chip Select Real Time Clock Printed Circuit Board Equivalent Series Resistance VSWR Voltage Standing Wave Radio Vector Network Analyzer TTFF Time to First Fix 1VV0301616 Rev.
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