Quectel EG21-G Reference Design page 23

6
D
C
B
Connector
Notes:
1. Test points for both USB and debug UART interfaces are reserved for software debugging.
A
2. Test points for USB interface also can be reserved for firmware upgrade.
3. Junction capacitance of ESD protection devices on USB data lines should be less than 2pF.
4. The module's debug UART interface supports 1.8V power domain,
A level translator should be used if the power domain of customers' application is 3.3V.
6
5
VBAT
D1312
R1307
2.2K
[3] STATUS
Notes:
1. The STATUS is an open drain output pin, and its drive current is less than 1mA.
2. For more details about NET_MODE and NET_STATUS, please refer to
3. If the current consumption is required as low as possible when the device is in sleep, replace the power supply of indicators with controllable one.
Turn off the power when the module enters sleep mode.
Reserved Test Points
J1302
1
2
3
4
5
6
7
8
9
D1305 D1306 D1307 D1309
SD12
5
4 3
Other Designs
Indicators
DC_5V
D1301
R1303
2.2K
Q1302
[3] NET_MODE
[3] NET_STATUS
DTC043ZEBTL
Quectel_EG21-G_Hardware_Design.
[3,5,14]
VBAT
[3,4]
PWRKEY
USB_VBUS [3,4]
USB_DM_TEST [3]
[3]
USB_DP_TEST
[3]
DBG_RXD
[3]
DBG_TXD
DBG_TXD_FC20
Notes:
D1310
D1311
1. It is recommended to reserve USB_BOOT design.
2. USB_BOOT is kept open by default.
3
4
2
DC_5V
D1302
R1304
2.2K
Q1303
DTC043ZEBTL
USB_BOOT Interface
J1301
4.7K
R1306
[3,4,5,6,11,13]
VDD_EXT
When it is at high level, the module will enter download mode.
Quectel Wireless Solutions
DRAWN BY
Lorry XU
CHECKED BY
Woody WU
2
1
[3]
USB_BOOT
D1304
ESD9X3.3ST5G
PROJECT TITLE
EG21-G Reference Design
VER
SIZE
A2 1.0
SHEET 14 OF 14 DATE 2019/12/5
1
D
C
B
A