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3.5.8 JP41, JP42 (USB interface OCI0, OCI1 jumpers)
Leave JP41 and JP42 open for normal use.
JP41
Short
Inputs low level to OCI0 (overcurrent state).
Open
Normal state (connects to high-side switch).
JP42
Short
Inputs low level to OCI1 (overcurrent state).
Open
Normal state (connects to high-side switch).
3.5.9 JP43 (FPGA DONE signal pull-up setting jumper)
Short JP43 when using the PFESiP EP-1 Evaluation Board by itself.
The PFESiP EP-1 Evaluation Board can be stacked with another board.
by asserting all DONE signals of the FPGA.
the pull-up processing of the PFESiP EP-1 Evaluation Board may have to be canceled, because these DONE
signals are connected by wired OR.
JP43
Short
Pulls up with this board.
Open
Does not pull up with this board.
3.5.10 JP44 (FPGA configuration ROM selection jumper)
When only one configuration ROM for the on-board FPGA is used (JP44 1-2), Virtex-4 XC4VLX40 to
XC4VLX100 can be used as the FPGA.
Any FPGA up to XC4VLX160 can be mounted on the PFESiP EP-1 Evaluation Board.
XCF08PFSG48C will be additionally mounted as a configuration ROM and 2-3 of JP44 will be shorted.
JP44
1-2
When only one FPGA configuration ROM is mounted (supported with XC4VLX40 to XC4VLX100)
2-3
When two FPGA configuration ROMs are mounted (supported with XC4VLX40 to XC4VLX160)
Open
Setting prohibited
CHAPTER 3
SWITCH SETTINGS
Position
Figure 1-1 (Appearance) B-3
USB Host Interface OCI0 Pin Selection
USB Host Interface OCI1 Pin Selection
Position
Figure 1-1 (Appearance) C-6
To combine the PFESiP EP-1 Evaluation Board with another board,
Position
Figure 1-1 (Appearance) B-6
FPGA ROM2 Use Selection
User's Manual
At this time, system reset is released
Pulls-up Process
A19350EJ1V1UM
In this case,
49
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