Siemens 3VF Series Communications Manual page 108

Communication System Manual
The parameterization message from the master to the interface module is structured as
follows:
Table 17: Parameterization message
SD LE
68H x
Octet
7 6 5 4 3 2 1 0
1
x
0 0
0 1
1 0
1 1
2
3
4
5
6
7
8 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0 1
* The time base for the watchdog time is specified as 10 ms in octets 2 and 3. Nothing lower than the digit "2" should ever
be entered in one octet and nothing lower than the digit "1" in the other, in order to ensure that the watchdog time does not
elapse too quickly. A time base of 1 ms is specified in the user parameters of some ASICs due to the 12 Mbaud technology.
** 11 Tbits minimum are specified as standard. This value must be less than the maximum TSDR.
*** The structure of the parameterization message is partly specified as is the case with ASICs LSPM2/SPM2. The SPC3
evaluates the first 7 (without user_prm_data) or the first 8 (with user_prm_data) data bytes. The first seven bytes are defined in
accordance with the standard. The eighth byte is used for SPC3-specific properties and the other bytes are available for the
application.
Response from slave
The slave responds to a parameterization message with "E5H" (short acknowledge). The slave does not
report parameterization errors until later when it receives a diagnostic request from the master.
108
LEr SD DA SA
x x 8x 8x
Bit no. Description
x x x Reserved
Response monitoring active
1
1 Operate slave in Freeze mode.
Operate slave in Sync mode.
1
x
Min. TSDR and slave-specific parameters can be
overwritten.
DP slave is enabled for other masters.
DP slave is disabled for other masters. All parameters are
transferred.
DP slave is enabled for other masters.
Time base for watchdog time *
(TWS (s) = 10ms*WD_Fact_1 * WD_Fact_2)
Time in Tbit which must elapse before the slave
responds. **
High ID number
Low ID number
Parameterization byte for PROFIBUS
controller SPC3
This bit disables start bit monitoring in the receiver.
1
This bit disables stop bit monitoring in the receiver.
1
Time base for watchdog = 10 ms
Time base for watchdog = 1 ms
© Copyright Siemens AG 1998. All rights reserved.
3WN1, 3WS1 Circuit-Breakers
FC DSAP SSAP
x 61/3D 62/3E
DU.. FCS ED
x .. x 16H
Designation
WD_On = 0
Freeze_req
Sync_req
Unlock
Lock
WD_Fact_1
WD_Fact_2
min_TSDR
Vendor_ID_high
Vendor_ID_low
Group_Ident
User_Prm_data
***
Dis_Startbit
Dis_Stopbit
WD_Base
Version 1.0 (08/98)