Seco COMe-C55-CT6 User Manual page 32

Com express type 6 module with the intel 8 th generation core and celeron 4000 cpus

Table of Contents

3.2.5.4

PCI Express interface signals

On COMe-C55-CT6 module, the SoC's embedded PCH can manage eight PCI Express lane, one of which is used to manage the optional Gigabit Ethernet controller.

PCI express Gen3 (8GT/s) is supported.

These PCI-express lanes can be switched to support single PCI-e lanes, the third SATA port and the PCI-e Graphics interface.

Please also be aware that these groupings cannot be changed dynamically, it is a factory option.

When ordering a COMe-C55-CT6 module, please take care of specifying which are the desired PCI-e and SATA groupings.

Possible groupings are as follows

•

PCI-e x1 ports #[0..7] + SATA #[0..1]

•

PCI-e x1 ports #[0..6] + PEG ports #[0..1] + SATA #[0..1]

•

PCI-e x1 ports #[0..4] + PEG ports #[0..3] + SATA #[0..1]

•

PCI-e x1 ports #[0..3] + PEG ports #[0..3] + SATA #[0..2]

Here following the signals involved in PCI express management (lanes #6 and #7 are available on connector CD, the other lanes are available on connector AB).

PCIE_TX0+/PCIE_TX0-: PCI Express lane #0, Transmitting Output Differential pair.

PCIE_RX0+/PCIE_RX0-: PCI Express lane #0, Receiving Input Differential pair

PCIE_TX1+/PCIE_TX1-: PCI Express lane #1, Transmitting Output Differential pair

PCIE_RX1+/PCIE_RX1-: PCI Express lane #1, Receiving Input Differential pair

PCIE_TX2+/PCIE_TX2-: PCI Express lane #2, Transmitting Output Differential pair

PCIE_RX2+/PCIE_RX2-: PCI Express lane #2, Receiving Input Differential pair

PCIE_TX3+/PCIE_TX3-: PCI Express lane #3, Transmitting Output Differential pair

PCIE_RX3+/PCIE_RX3-: PCI Express lane #3, Receiving Input Differential pair

PCIE_TX4+/PCIE_TX4-: PCI Express lane #4, Transmitting Output Differential pair

PCIE_RX4+/PCIE_RX4-: PCI Express lane #4, Receiving Input Differential pair

PCIE_TX5+/PCIE_TX5-: PCI Express lane #5, Transmitting Output Differential pair

PCIE_RX5+/PCIE_RX5-: PCI Express lane #5, Receiving Input Differential pair