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Summary of Contents for Texas Instruments TPS70151 Series
- Page 1 Low Dropout, Dual Output Linear Regulator EVM Using the TPS70151 User’s Guide April 2000 Mixed-Signal Products SLVU025A...
- Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability.
- Page 3 A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments TPS70151 data sheets (literature number SLVS222) Read This First...
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Page 5: Table Of Contents
Running Title—Attribute Reference Contents Introduction ..............1–1 Low Dropout Voltage Linear Regulator Circuit Operation . - Page 6 Running Title—Attribute Reference Figures 1–1 Typical LDO Application ............1–2 SLVP152 EVM Universal LDO Tester Schematic Diagram .
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Page 7: Introduction
Chapter 1 Introduction This user’s guide describes the TPS70151EVM–152 low dropout, dual-output evaluation module (SLVP152). LDOs provide ideal power supplies for rapidly transitioning DSP loads. The TPS701xx family of devices is designed to provide a complete power management solution for DSP, processor power, ASIC, FPGA, and digital applications where dual output voltage regulators are required. -
Page 8: Low Dropout Voltage Linear Regulator Circuit Operation
Low Dropout Voltage Linear Regulator Circuit Operation 1.1 Low Dropout Voltage Linear Regulator Circuit Operation In TI’s low dropout voltage linear regulator topology, a PMOS transistor acts as the pass element. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low and is directly proportional to the output current. -
Page 9: Design Strategy
Design Strategy 1.2 Design Strategy The TI SLVP152 EVM provides a convenient method for evaluating the performance of TPS701xx dual-output linear regulators. The EVM provides proven, demonstrated reference designs and test modes to aid in evaluation. The board contains a power supply along with an onboard transient generator. The transient slew rate can be modified by changing two resistors. -
Page 10: Schematic
Schematic 1.3 Schematic Figure1–2 shows the SLVP152 EVM schematic diagram. Figure 1–2. SLVP152 EVM Universal LDO Tester Schematic Diagram TP16 TP14 Sense 2 kΩ 2 kΩ Green 33 µF 0.1 µF 10 kΩ TPS70151PWP VIN1 100 µF 0.1 µF PG_1 Sense VIN1 VOUT1... -
Page 11: Bill Of Materials
Bill of Materials 1.4 Bill of Materials Table 1–2 lists materials required for the SLVP152 EVM. Table 1–2. SLVP152 EVM Bill of Materials Ref Des Qty Part Number Description Size ECJ-2VF1C105Z Capacitor, ceramic, 1.0 uF, 16 V, Panasonic 80% – 20%, Y5V C4 –... - Page 12 Bill of Materials Table 1–2. SLVP152 EVM Bill of Materials (Continued) Ref Des Qty Part Number Description Size EG1218 Switch, 1P2T, slide, PC-mount E–Switch 0.1” TP1, 2, 131–4244–00 Adaptor, 3.5-mm probe clip (or Tektronix 16, 17 131–5031–00) TP3 – 15 240–345 Test point, red Farnell...
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Page 13: Board Layout
Board Layout 1.5 Board Layout Figures 1–3 through 1-5 show the board layout for the SLVP125 EVM. Figure 1–3. Top Layer Top Layer Figure 1–4. Bottom Layer (top view) Bottom Layer (Top View) Introduction... -
Page 14: Assembly Drawing (Top Assembly)
Board Layout Figure 1–5. Assembly Drawing (top assembly) Dual – Output LDO EVM SLVP152 Top Assembly Introduction... -
Page 15: Evm Adjustments And Test Points
Chapter 2 EVM Adjustments and Test Points This chapter explains the following EVM adjustment modes: Adjustment by switch and jumper Adjustment through changing components Figure 2–1 shows the locations of the adjustment points on the board. Topic Page Adjustment by Switch and Jumpers . -
Page 16: Jumper Functions
Adjustment by Switch and Jumpers 2.1 Adjustment by Switch and Jumpers S1 switches the transient generator on or off. Table 2–1 lists adjustments that can be made by jumpers. Table 2–1. Jumper Functions Jumper Setting Functional Description Short 1-2 – MR2 tied to GND RESET follows MR2 Short 2-3 –... -
Page 17: Adjustment Through Component Changes
Adjustment Through Component Changes 2.2 Adjustment Through Component Changes Through minor soldering work, the DUT can be changed to any of the fixed- voltage members of the TPS701xx LDO family. In addition, Table 2–2 summa- rizes the most common components which a user might wish to replace in or- der to more fully characterize the LDO. -
Page 18: Test Setup
Test Setup 5) Verify that the output voltage (measured at the V and V pins re- OUT1 OUT2 spectively) has the desired value. 6) Table 2–4 shows the three recommended options for loading each regula- tor. Table 2–4. Regulator Loading Options JP5–Regulator 1 Type JP6–Regulator 2... -
Page 19: Circuit Design
Chapter 3 Circuit Design This chapter describes the LDO circuit design procedure. Topic Page Temperature Considerations ........3–2 ESR and Transient Response . -
Page 20: Temperature Considerations
Temperature Considerations 3.1 Temperature Considerations To protect the device and assure the specifications, the maximum junction temperature should not exceed 125 C. If the temperature exceeds 150 C, thermal shutdown will turn off the device. This restriction limits the power dissipation the regulator can handle in any given application. -
Page 21: Ldo Output Stage With Parasitic Resistances Esr
ESR and Transient Response Figure 3–2 shows the output capacitor and its parasitic impedances in a typical LDO output stage. Figure 3–2. LDO Output Stage With Parasitic Resistances ESR – LOAD – In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across the capacitor is the same as the output voltage (V(C ) = V... - Page 22 ESR and Transient Response Figure 3–3. Correlation of Different ESRs and Their Influence to the Regulation of V at a Load Step From Low-to-High Output Current ESR 1 ESR 2 ESR 3 Circuit Design...
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Page 23: Test Results
Chapter 4 Test Results This chapter presents laboratory test results for the TPS70151 LDO design. Topic Page Test Results ..........4–2 Test Results... -
Page 24: Test Results
Test Results 4.1 Test Results Figures 4–1 through 4–9 show the results of various test conditions using the TPS70151 device. In figures 4–1 through 4–3, channel 1 is regulator 1 output voltage and channel 4 is the load current. In figures 4–4 through 4–9, channel 1 is regulator 1 output, channel 2 is regulator 2 output, and channel 4 is RESET. -
Page 25: Timing When Sequence = Low
Test Results = 33 µ F POSCAP – Figure 4–3. No Load – Full Load (500 mA) Transition With C Maximum Transient Droop Voltage The maximum transient droop voltage is 56 mV. Figure 4–4. Timing When SEQUENCE = Low at 5V and both V (CH1) and V (CH2) have no load. -
Page 26: Timing When Sequence = Low, Including Reset
Test Results Figure 4–5. Timing When SEQUENCE = Low, Including RESET at 5V and both V (CH1) and V (CH2) have no load. EN IN1 = OUT1 OUT2 is pulsed with a fast pulse. V powers up before V when SEQUENCE OUT1 OUT2 = low. -
Page 27: Timing When Sequence = High And
Test Results Figure 4–7. Timing When SEQUENCE = High and V Faults Out OUT1 When SEQUENCE = high, V (CH2) remains on even after V (CH1) OUT2 OUT1 faults out due to current limit. The V fault causes PG_1 (CH3), tied to OUT1 MR1, to go low. -
Page 28: Timing When Mr Is Toggled
Test Results Figure 4–9. Timing When MR Is Toggled MR1 (CH3)is taken low and RESET (CH4) follows MR1. V (CH1) and OUT1 (CH2) are unaffected. OUT2 All results are consistent with those reported in the SLVS222 datasheet. Test Results...
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