Texas Instruments SLVP125 EVM User Manual
  1. Manuals
  2. Brands
  3. Texas Instruments Manuals
  4. Motherboard
  5. SLVP125 EVM
  6. User manual
Texas Instruments SLVP125 EVM User Manual

Texas Instruments SLVP125 EVM User Manual

Ldo linear regulator design
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
LDO Linear Regulator Design
Using the Universal SOT23
EVM
User's Guide
August 1999
Mixed Signal Products
SLVU019

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SLVP125 EVM and is the answer not in the manual?

Questions and answers

Related Manuals for Texas Instruments SLVP125 EVM

Summary of Contents for Texas Instruments SLVP125 EVM

  • Page 1 LDO Linear Regulator Design Using the Universal SOT23 User’s Guide August 1999 Mixed Signal Products SLVU019...
  • Page 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
  • Page 3 Information About Cautions and Warnings Preface Read This First About This Manual This user’s guide describes techniques for designing low dropout voltage lin- ear regulators (LDO) using TI’s SLVP125 evaluation modules (EVM) and TPS 76933 LDOs. How to Use This Manual This document contains the following chapters: Chapter 1 Introduction Chapter 2 EVM Adjustments and Test Points...
  • Page 4 Related Documentation From Texas Instruments The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments TPS760xx, TPS761xx, TPS763xx, TPS764xx, TPS769xx, TPS770xx data sheets (literature numbers SLVS144B, SLVS178A, SLVS181D,...

  • Page 5: Table Of Contents

    Running Title—Attribute Reference Contents Introduction ..............Low Dropout Voltage Linear Regulator Circuit Operation .
  • Page 6 ............1–2 SLVP125 EVM Universal LDO Tester Schematic Diagram ......

  • Page 7: Introduction

    TI’s SLVP125 evaluation module (EVM) and TPS76933 LDO. LDOs provide ideal power supplies for rapidly transitioning DSP loads such as the Texas Instruments TMS320C54x and similar processors, and fast memory. Low quiescent current and very low dropout voltage compared to standard LDOs makes the TPS76933 particularly suitable in battery applications requiring extended lifetime and low cost.

  • Page 8: Low Dropout Voltage Linear Regulator Circuit Operation

    Low Dropout Voltage Linear Regulator Circuit Operation 1.1 Low Dropout Voltage Linear Regulator Circuit Operation In the low dropout voltage linear regulator topology, a PMOS transistor acts as a pass element that reduces the normal 1.5-V to 2.5-V collector-to-emitter drop to about 0.3 V or less. This improvement results in lower power dissipation and higher efficiency when compared to other regulator designs.

  • Page 9: Design Strategy

    Design Strategy 1.2 Design Strategy The TI SLVP125 EVM provides a circuit to simultaneously compare the performance of two LDOs in a SOT23 package. The EVM provides proven, demonstrated reference designs and test modes to aid in choosing and evaluating LDOs. A programmable high speed transient generator generates either line or load transients.

  • Page 10: Schematic

    Schematic 1.3 Schematic Figure1–2 shows the SLVP125 EVM Universal LDO Tester (3.3 V output with TPS76933 as U1) schematic diagram. Figure 1–2. SLVP125 EVM Universal LDO Tester Schematic Diagram...
  • Page 11 Schematic Figure 1–2. SLVP125 EVM Universal LDO Tester Schematic Diagram (Continued) Introduction...

  • Page 12: Bill Of Materials

    Bill of Materials 1.4 Bill of Materials Table 1–2 lists materials required for the SLVP125 EVM. Table 1–2. SLVP125 EVM Bill of Materials Description Size Capacitor, OS-Con, 470 µF, 16 V, 20-mΩ, 20% 16SA470M Sanyo Capacitor, OS-Con, 470 µF, 16 V, 10-mΩ, 20%...
  • Page 13 Bill of Materials Table 1–2. SLVP125 EVM Bill of Materials (Continued) Description Size Resistor, Chip, user option, 1/8 W, 1% 1206 Resistor, chip, 10.0 MΩ, 1/8 W, 1% 1206 Trim Pot, cermet, 10 Ω vertical, top adjust, 1/2 W, 10%...

  • Page 14: Board Layout

    Board Layout 1.5 Board Layout Figures 1–3 through 1-6 show the board layout for the SLVP125 EVM. Figure 1–3. Top Layer Figure 1–4. Bottom Layer (top view)

  • Page 15: Assembly Drawing (Top Assembly)

    Board Layout Figure 1–5. Assembly Drawing (top assembly) Introduction...
  • Page 16 1-10...

  • Page 17: Evm Adjustments And Test Points

    Chapter 2 EVM Adjustments and Test Points This chapter explains the following four EVM adjustment modes: Adjustment by switch Adjustment by jumper Adjustment by trimmer Adjustment by programming header Figure 2–1 shows the locations of the adjustment points on the board. Topic Page Adjustment by Switch...

  • Page 18: Adjustment By Switch

    Adjustment by Switch 2.1 Adjustment by Switch S1 toggles between high (direction labelling) or low transient generator frequency. S2 switches the transient generator on (direction labelling) and off. S3 toggles between slower (direction labelling) and faster transients. S4 directs transients either to DUT1 (direction labelling) or DUT2. 2.2 Adjustment by Jumper Table 2–1 lists adjustments that can be made by jumpers.

  • Page 19: Test Setup

    Test Setup Table 2–3. Timing Equations Timing Equations With Diode DH1 Timing Equations Without Diode for Low Duty Cycles (2 D– 1) RH 1 RH 1 0.693 0.693 (1 –D ) (1 –D ) RH 2 RH 2 0.693 0.693 Note: t on = desired load on-time [s] D = on-time duty cycle...

  • Page 20: Test Setup

    Test Setup 3) Connect a 2 lab power supply (at least capable to supply 2 A) to the J1 and J3 connector at Vin and GND. The polarity is printed on the board. Verify that the output voltage limit is set to 13.5 V and that the output is set to 0 V.

  • Page 21: Circuit Design

    Chapter 3 Circuit Design This chapter describes the LDO circuit design procedure. Topic Page Adjusting the TPS76xx01/TPS77001 Output Voltage ... . . 3–2 Temperature Considerations ........3–6 External Capacitor Requirements –...

  • Page 22: Adjusting The Tps76X01/Tps77001 Output Voltage

    Adjusting the TPS76x01/TPS77001 Output Voltage 3.1 Adjusting the TPS76x01/TPS77001 Output Voltage All voltage regulators of the TPS76x01/TPS77001 families use the same inter- nal bandgap voltage, see also Figure 1–1. In the adjustable version, the resis- tors R1 and R2 are external resistors. Due to the virtual short circuit between the input pins of an op amp, the voltage V applies to both the +input pin and the –input pin.

  • Page 23: Resistor Values

    Adjusting the TPS76x01/TPS77001 Output Voltage Figure 3–2. Resistor Values 1800 1600 max Value for R1+R2[kΩ] R1/R2 1400 1200 1000 Output Voltage [V] Table 3–1. Exact Resistor Values V out R1/R2 Maximum Value for R1+R2[kΩ] 0.018676 171.429 0.103565 185.714 0.188455 200.000 0.273345 214.286 0.358234...
  • Page 24 Adjusting the TPS76x01/TPS77001 Output Voltage Table 3–1. Exact Resistor Values(Continued) V out R1/R2 Maximum Value for R1+R2[kΩ] 1.886248 485.714 1.971138 500.000 2.056027 514.286 2.140917 528.571 2.225806 542.857 2.310696 557.143 2.395586 571.429 2.480475 585.714 2.565365 600.000 2.650255 614.286 2.735144 628.571 2.820034 642.857 2.904924 657.143...

  • Page 25: E96 Resistor Series

    Adjusting the TPS76x01/TPS77001 Output Voltage For 3 V, one gets: I) R 1 1.546689 II) R1 428.571 k å I ) R1 1.546689 å I ) in II) : 1.546689 428.571 k å 428.571 k 168.286 k 2.546689 Make R2 = 169 kΩ and calculate R1: Derived from equation I), one gets for R1: 1.546689 169 k...

  • Page 26: Temperature Considerations

    Temperature Considerations 3.2 Temperature Considerations To protect the device and assure the specifications, the maximum junction temperature should not exceed 125 C. This restriction limits the power dis- sipation the regulator can handle in any given application. To ensure the junc- tion temperature is within acceptable limits, calculate the maximum allowable dissipation, P , and the actual dissipation, P...

  • Page 27: External Capacitor Requirements - Esr

    External Capacitor Requirements – ESR Figure 3–3. Calculated and Measured Maximum Output Current vs Input Voltage Without Cooling for TPS76933 in Test Setup 3% V out – Tolerance Area 300 mA Current limit I out , max vs. Input Voltage, calculated Values I out , max vs.

  • Page 28: Ldo Output Stage With Parasitic Resistances Esr And Esl

    External Capacitor Requirements – ESR Figure 3–5. LDO Output Stage With Parasitic Resistances ESR and ESL LOAD Cout In steady state (dc state condition) the load is supplied by the LDO (solid arrow) and V . This means no current is flowing into the C branch.

  • Page 29: Correlation Of Different Esrs And Their Influence To The Regulation Of

    External Capacitor Requirements – ESR Figure 3–6. Correlation of Different ESRs and Their Influence to the Regulation of V at a Load Step From Low to High Output Current I out V out ESR 1 ESR 2 ESR 3 In order to get a good performing system, an LDO with short response time and an output capacitor with low ESR are required.
  • Page 30 3-10...
  • Page 31 Chapter 4 Test Results This chapter presents laboratory test results for the LDO design. Topic Page Test Results 4–2 Test Results...

  • Page 32: Rise Time Of Function Generator At Gate Of Mosfet Q1 (High Speed)

    Test Results 4.1 Test Results Figures 4–1 through 4–7 show the results of various tests and test conditions for the circuit using the TPS76933 device. Figure 4–1. Rise Time of Function Generator at Gate of MOSFET Q1 (high speed) Figure 4–2. Rise Time of Function Generator at Gate of MOSFET Q1 (low speed)

  • Page 33: Transient At Input (Ch1); 4.3 V Input, 3.3 V Output (Ch2) At 100 Ma Load

    Test Results Figure 4–3. Transient at Input (Ch1); 4.3 V Input, 3.3 V Output (Ch2) at 100 mA Load, = 10 µ F Spike Output Voltage Figure 4–4. Delay Time EN Output High Enable Pulse Output Voltage Test Results...

  • Page 34: Out , Whole Period

    Test Results Figure 4–5. Full Load (100 mA) – No Load Transition, ∆ V , Whole Period Output Voltage (see Note 2) Load Transition (see Note 1) = 10 µ F Electrolytic Figure 4–6. Full Load (100 mA) – No Load Transition With C Output Voltage (see Note 2) Load Transition...
  • Page 35 Test Results = 10 µ F Electrolytic Figure 4–7. No Load – Full Load (100 mA) Transition With C Output Voltage (see Note 2) Load Transition (see Note 1) Notes: 1) The load transition was measured as the voltage drop at the drain of Q1 (see Figure 1–2).
  • Page 37 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments TPS76XXXEVM-125...

This manual is also suitable for:

Tps76933

Table of Contents