Summary of Contents for Texas Instruments SLVP125 EVM
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LDO Linear Regulator Design Using the Universal SOT23 User’s Guide August 1999 Mixed Signal Products SLVU019...
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IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
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Information About Cautions and Warnings Preface Read This First About This Manual This user’s guide describes techniques for designing low dropout voltage lin- ear regulators (LDO) using TI’s SLVP125 evaluation modules (EVM) and TPS 76933 LDOs. How to Use This Manual This document contains the following chapters: Chapter 1 Introduction Chapter 2 EVM Adjustments and Test Points...
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Related Documentation From Texas Instruments The information in a caution or a warning is provided for your protection. Please read each caution and warning carefully. Related Documentation From Texas Instruments TPS760xx, TPS761xx, TPS763xx, TPS764xx, TPS769xx, TPS770xx data sheets (literature numbers SLVS144B, SLVS178A, SLVS181D,...
TI’s SLVP125 evaluation module (EVM) and TPS76933 LDO. LDOs provide ideal power supplies for rapidly transitioning DSP loads such as the Texas Instruments TMS320C54x and similar processors, and fast memory. Low quiescent current and very low dropout voltage compared to standard LDOs makes the TPS76933 particularly suitable in battery applications requiring extended lifetime and low cost.
Low Dropout Voltage Linear Regulator Circuit Operation 1.1 Low Dropout Voltage Linear Regulator Circuit Operation In the low dropout voltage linear regulator topology, a PMOS transistor acts as a pass element that reduces the normal 1.5-V to 2.5-V collector-to-emitter drop to about 0.3 V or less. This improvement results in lower power dissipation and higher efficiency when compared to other regulator designs.
Design Strategy 1.2 Design Strategy The TI SLVP125 EVM provides a circuit to simultaneously compare the performance of two LDOs in a SOT23 package. The EVM provides proven, demonstrated reference designs and test modes to aid in choosing and evaluating LDOs. A programmable high speed transient generator generates either line or load transients.
Board Layout 1.5 Board Layout Figures 1–3 through 1-6 show the board layout for the SLVP125 EVM. Figure 1–3. Top Layer Figure 1–4. Bottom Layer (top view)
Chapter 2 EVM Adjustments and Test Points This chapter explains the following four EVM adjustment modes: Adjustment by switch Adjustment by jumper Adjustment by trimmer Adjustment by programming header Figure 2–1 shows the locations of the adjustment points on the board. Topic Page Adjustment by Switch...
Adjustment by Switch 2.1 Adjustment by Switch S1 toggles between high (direction labelling) or low transient generator frequency. S2 switches the transient generator on (direction labelling) and off. S3 toggles between slower (direction labelling) and faster transients. S4 directs transients either to DUT1 (direction labelling) or DUT2. 2.2 Adjustment by Jumper Table 2–1 lists adjustments that can be made by jumpers.
Test Setup 3) Connect a 2 lab power supply (at least capable to supply 2 A) to the J1 and J3 connector at Vin and GND. The polarity is printed on the board. Verify that the output voltage limit is set to 13.5 V and that the output is set to 0 V.
Adjusting the TPS76x01/TPS77001 Output Voltage 3.1 Adjusting the TPS76x01/TPS77001 Output Voltage All voltage regulators of the TPS76x01/TPS77001 families use the same inter- nal bandgap voltage, see also Figure 1–1. In the adjustable version, the resis- tors R1 and R2 are external resistors. Due to the virtual short circuit between the input pins of an op amp, the voltage V applies to both the +input pin and the –input pin.
Adjusting the TPS76x01/TPS77001 Output Voltage Figure 3–2. Resistor Values 1800 1600 max Value for R1+R2[kΩ] R1/R2 1400 1200 1000 Output Voltage [V] Table 3–1. Exact Resistor Values V out R1/R2 Maximum Value for R1+R2[kΩ] 0.018676 171.429 0.103565 185.714 0.188455 200.000 0.273345 214.286 0.358234...
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Adjusting the TPS76x01/TPS77001 Output Voltage Table 3–1. Exact Resistor Values(Continued) V out R1/R2 Maximum Value for R1+R2[kΩ] 1.886248 485.714 1.971138 500.000 2.056027 514.286 2.140917 528.571 2.225806 542.857 2.310696 557.143 2.395586 571.429 2.480475 585.714 2.565365 600.000 2.650255 614.286 2.735144 628.571 2.820034 642.857 2.904924 657.143...
Adjusting the TPS76x01/TPS77001 Output Voltage For 3 V, one gets: I) R 1 1.546689 II) R1 428.571 k å I ) R1 1.546689 å I ) in II) : 1.546689 428.571 k å 428.571 k 168.286 k 2.546689 Make R2 = 169 kΩ and calculate R1: Derived from equation I), one gets for R1: 1.546689 169 k...
Temperature Considerations 3.2 Temperature Considerations To protect the device and assure the specifications, the maximum junction temperature should not exceed 125 C. This restriction limits the power dis- sipation the regulator can handle in any given application. To ensure the junc- tion temperature is within acceptable limits, calculate the maximum allowable dissipation, P , and the actual dissipation, P...
External Capacitor Requirements – ESR Figure 3–3. Calculated and Measured Maximum Output Current vs Input Voltage Without Cooling for TPS76933 in Test Setup 3% V out – Tolerance Area 300 mA Current limit I out , max vs. Input Voltage, calculated Values I out , max vs.
External Capacitor Requirements – ESR Figure 3–5. LDO Output Stage With Parasitic Resistances ESR and ESL LOAD Cout In steady state (dc state condition) the load is supplied by the LDO (solid arrow) and V . This means no current is flowing into the C branch.
External Capacitor Requirements – ESR Figure 3–6. Correlation of Different ESRs and Their Influence to the Regulation of V at a Load Step From Low to High Output Current I out V out ESR 1 ESR 2 ESR 3 In order to get a good performing system, an LDO with short response time and an output capacitor with low ESR are required.
Test Results 4.1 Test Results Figures 4–1 through 4–7 show the results of various tests and test conditions for the circuit using the TPS76933 device. Figure 4–1. Rise Time of Function Generator at Gate of MOSFET Q1 (high speed) Figure 4–2. Rise Time of Function Generator at Gate of MOSFET Q1 (low speed)
Test Results Figure 4–3. Transient at Input (Ch1); 4.3 V Input, 3.3 V Output (Ch2) at 100 mA Load, = 10 µ F Spike Output Voltage Figure 4–4. Delay Time EN Output High Enable Pulse Output Voltage Test Results...
Test Results Figure 4–5. Full Load (100 mA) – No Load Transition, ∆ V , Whole Period Output Voltage (see Note 2) Load Transition (see Note 1) = 10 µ F Electrolytic Figure 4–6. Full Load (100 mA) – No Load Transition With C Output Voltage (see Note 2) Load Transition...
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Test Results = 10 µ F Electrolytic Figure 4–7. No Load – Full Load (100 mA) Transition With C Output Voltage (see Note 2) Load Transition (see Note 1) Notes: 1) The load transition was measured as the voltage drop at the drain of Q1 (see Figure 1–2).
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