Memory; Emmc Storage; Table 4 - Emmc Signal Description - TechNexion PICO-IMX8M Product Manual

PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019

3.3. Memory

The PICO-IMX8M integrates Low Power Double Data Rate IV (LPDDR4) Synchronous DRAM is
connected with a 32 bit dual channel configuration. (16 bit per channel).
The following memory chip manufacturers have been validated and tested on the PICO-IMX8M
Compute Module:
•
SKHynix
•
Kingston
•
Micron
•
Samsung
•
ISSI

3.4. eMMC Storage

The PICO-IMX8M can be ordered with onboard eMMC storage in different configurations and
capacity. The onboard eMMC device is connected on the SD1 pins of the i.MX8M processor in an 8-
bit width configuration.
The following eMMC chip manufacturers have been validated and tested on the PICO-IMX8M
System-on-Module:
•
Kingston eMMC
•
Micron eMMC
•
Sandisk iNAND
Table 4 – eMMC Signal Description
CPU
CPU PAD NAME
BALL
SD1_DATA0
M25
M24 SD1_DATA1
N25 SD1_DATA2
P25 SD1_DATA3
SD1_DATA4
N24
P24 SD1_DATA5
R25 SD1_DATA6
T25 SD1_DATA7
L24 SD1_CMD
L25 SD1_CLK
SD1_DS
T24
Signal V
eMMC_DATA0
1V8
eMMC_DATA1 1V8
eMMC_DATA2 1V8
eMMC_DATA3 1V8
eMMC_DATA4
1V8
eMMC_DATA5 1V8
eMMC_DATA6 1V8
eMMC_DATA7 1V8
eMMC_CMD 1V8
eMMC_CLK 1V8
eMMC_STROBE
1V8
I/O Description
I/O MMC/SDIO Data bit 0
I/O MMC/SDIO Data bit 1
I/O MMC/SDIO Data bit 2
I/O MMC/SDIO Data bit 3
I/O MMC/SDIO Data bit 4
I/O MMC/SDIO Data bit 5
I/O MMC/SDIO Data bit 6
I/O MMC/SDIO Data bit 7
I/O MMC/SDIO Command
O MMC/SDIO Clock
This signal is generated by the device
O
and used for output in HS400 Mode
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