Page 1
PICO-IMX8M SYSTEM ON MODULE PRODUCT MANUAL (WITH NXP i.MX8M SoC) VER. 0.99 January 14, 2019...
Page 2
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 REVISION HISTORY Revision Date Originator Notes November 6, 2018 TechNexion Preliminary 0.99 January 14, 2019 TechNexion Updated PCIe Signals and general release edits Page 2 of 44...
The PICO-IMX8M is a high performance highly integrated PICO Compute Module designed around the NXP i.MX8M Dual/QuadLite/Quad core ARM Cortex-A53 + Cortex-M4 applications processor. The PICO-IMX8M provides an ideal building block that easily integrates with a wide range of target markets requiring compact, cost effective with low power consumption.
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 3. Core Components 3.1. NXP i.MX8M ARM Cortex-A53 + Cortex-M4 Processor The NXP i.MX 8M family of applications processors based on Arm® Cortex®-A53 and Cortex-M4 cores provide industry-leading audio, voice and video processing for applications that scale from consumer home audio, embedded digital signage to industrial building automation control applications.
WDOG_B WDOG_B signal of PMIC To perform a hard-reset of the PICO-IMX8M an external circuit (for example a button or external watchdog IC) can be integrated on the carrier board. Table 3 – PMIC Reset Signal Description Connector Signal...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 3.3. Memory The PICO-IMX8M integrates Low Power Double Data Rate IV (LPDDR4) Synchronous DRAM is connected with a 32 bit dual channel configuration. (16 bit per channel). The following memory chip manufacturers have been validated and tested on the PICO-IMX8M Compute Module: •...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 3.5. Wi-Fi/Bluetooth The PICO-IMX8M has an optional pre-certified high-performance TechNexion PIXI-9377 dual band 2.4/5Ghz Wi-Fi / Bluetooth 4.1 Qualcomm Atheros QCA9377 chipset based module on board. The PIXI-9377 Wi-Fi / Bluetooth module is designed to operate with a single antenna for Wi-Fi and Bluetooth by using the MHF4 connector.
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 Table 5 – Wi-Fi Signal Description i.MX8M PAD NAME Signal Description BALL SD2_DATA0 SD2_DATA0 MMC/SDIO Data bit 0 SD2_DATA1 SD2_DATA1 MMC/SDIO Data bit 1 SD2_DATA2 SD2_DATA2 MMC/SDIO Data bit 2...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 Table 6 – Bluetooth Signal Description i.MX8M PAD NAME Signal Description BALL UART2_TXD UART2_TXD Bluetooth UART Serial Input. Serial data input for the HCI UART Interface UART2_RXD UART2_RXD Bluetooth UART Serial Output. Serial data output for the HCI UART Interface.
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 4. PICO Compute Module Pin Assignment The PICO-IMX8M has three 70-pin Hirose board-to-board connectors. Figure 8 – PICO-IMX8M Board-to-Board Connectors Table 7 – PICO Compute Module Pin Assignment CPU PAD NAME...
Page 15
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 Over current detect input E1_19 SAI3_RXFS GPIO4_IO28 pin to monitor USB power over current E1_20 USB1_VBUS USB_VBUS Universal Serial Bus power Universal Serial Bus power E1_21 NAND_DQS GPIO3_IO14 enable Universal Asynchronous...
Page 16
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 Integrated Interchip Sound E1_50 SAI3_RXD SAI3_RXD (I2S) channel receive data line Serial Peripheral Interface E1_51 NAND_CE1_B ECSPI1_SS1 Chip Select 1 signal Integrated Interchip Sound E1_52 SAI3_TXC SAI3_TXC (I2S) channel word clock...
Page 17
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 CPU PAD NAME Signal Description BALL X1_1 Ground X1_2 Ground MIPI Camera 2 Serial X1_3 CSI2_D3_N CSI_P2_DN3 Interface data pair 3 negative signal General Purpose Input X1_4 UART3_TXD GPIO5_IO27 Output for MIPI...
Page 18
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 Management data clock X1_33 ENET_MDC ENET_MDC reference X1_34 Not Connected X1_35 NET_MDIO ENET_MDIO Management data X1_36 Not Connected X1_37 GPIO1_IO09 GPIO1_IO09 Ethernet reset X1_38 Not Connected Ethernet interrupt X1_39 GPIO1_IO11...
Page 19
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 CPU PAD NAME Signal Description BALL X2_1 Ground X2_2 Ground SAI1_RXD4 BT_CFG4 Boot Select pin X2_3 SAI1_TXD2 BT_CFG10 Boot Select pin SAI1_TXD4 BT_CFG12 Boot Select pin MIPI Display Serial X2_4...
Page 20
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 HDMI differential pair 2 X2_30 HDMI_TX_M_LN_2 HDMI_TXN2 negative signal MIPI Camera 1 Serial X2_31 CSI1_CLK_N CSI_P1_CKN Interface clock pair negative signal X2_32 Ground MIPI Camera 1 Serial X2_33 CSI1_CLK_P CSI_P1_CKP...
Page 21
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 (low = overcurrent detected) MIPI Display Serial X2_53 DSI_D0_P DSI_DP0 Interface data pair 0 positive signal X2_54 Ground MIPI Display Serial X2_55 DSI_D0_N DSI_DN0 Interface data pair 0 negative signal...
5. PICO Compute Module Connector Interfaces 5.1. Ethernet The PICO-IMX8M provides a 10/100/1000-Mbit/s MAC ethernet interface which, implements layer 3 network acceleration functions. These functions are designed to accelerate the processing of various common networking protocols, such as IP, TCP, UDP, and ICMP, providing wire speed services to client applications.
• eDP 1.4 NOTE : Display Port and eDP interfaces are not validated on TechNexion carrier board and awaits NXP formal documentation and software release. For additional details, please refer to the “HD Display Transmitter Controller (HDMI TX)” chapter of the “i.MX8M Reference Manual”.
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.2. MIPI Display The Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) controller is a flexible, high-performance, and easy-to-use digital core that implements all protocol functions defined in the MIPI DSI Specification.
Page 25
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 MIPI Display Serial X2_57 DSI_D1_P DSI_DP1 Interface data pair 1 positive signal MIPI Display Serial X2_59 DSI_D1_N DSI_DN1 Interface data pair 1 negative signal MIPI Display Serial X2_61 DSI_CLK_N DSI_CKN...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.3. MIPI Camera This section introduces the MIPI CSI-2 RX subsystem with the CSI-2 RX PHY and host controller. This subsystem handles the sensor/image input and process for all the input imaging devices.
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 Table 12 – MIPI Camera 1 Signal Description CPU PAD NAME Signal Description BALL MIPI Camera 1 Serial X2_31 CSI1_CLK_N CSI_P1_CKN Interface clock pair negative signal MIPI Camera 1 Serial...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 Table 13 – MIPI Camera 2 Signal Description CPU PAD NAME Signal Description BALL MIPI Camera 2 Serial Interface data X1_3 CSI2_D3_N CSI_P2_DN3 pair 3 negative signal General Purpose Input Output for...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.4. Audio Interface The PICO-IMX8M provides multiple I S (or I S) interfaces that support fullduplex serial interfaces with frame synchronization such as I2S, AC97, TDM, and codec/DSP interfaces. The I S Interface supports the following features: •...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.5. PCI Express This block provides information regarding PCIe PHY and its features. PCIe PHY supports 6.0 Gbps data rate and complies to PCI Express base specification 2.1. The functions that are performed by the transceiver include serializing the 8B/10B encoded data for transmission, de-serializing received code groups, and word alignment.
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.6. Universal Serial Bus (USB) Interface The PICO-IMX8M incorporates a single USB Host controller and an additional USB Host/OTG controller. Each of the USB controllers provides the following main features: USB 2.0 Host/OTG Controller...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 Table 18 - USB OTG Signal Description CPU PAD NAME Signal Description BALL E1_3 USB1_ID USB1_ID USB OTG ID Pin Universal Serial Bus E1_16 USB1_DP USB1_DP differential pair positive signal...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.7. SDIO/MMC Interface The PICO-IMX8M features a MMC / SD / SDIO host interfaces connected to the NXP i.MX8M integrated “Ultra Secured Digital Host Controller” (uSDHC). The following main features are supported by uSDHC: •...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.8. Universal Asynchronous Receiver/Transmitter (UART) Interface The PICO-IMX8M Universal Asynchronous Receiver/Transmitter (UART) provides serial communication capability with external devices through a level converter. The UART includes the following features: •...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.9. Serial Peripheral Interface (SPI) The PICO-IMX8M has an onboard SPI interface that can operate in either master or SPI slave mode. The SPI Interface includes the following features : •...
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.10. I C Bus The PICO-IMX8M incorporates several I C interfaces. I C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices.
5.11. General Purpose Input / Output (GPIO) The PICO-IMX8M has 10 dedicated GPIO pins at 1.8V. Many of the other pins used on the PICO Compute Module can be put in GPIO module however doing so might break scalability with other PICO Compute Modules.
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.12. Pulse Width Modulation (PWM) The Pulse Width Modulation (PWM) has a 16-bit counter, and is optimized to generate sound from stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4 x 16 data FIFO.
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.13. Manufacturing and Boot Control The PICO-IMX8M has a number of pins to override the default boot media present on the PICO- IMX8M Compute Module or enable debug serial loader functionality.
PICO-IMX8M HARDWARE MANUAL – VER 0.99 – JAN 14 2019 5.13.3. SD Card Boot Mode For configurations of the PICO-IMX8M that do not incorporate a Wi-Fi / Bluetooth option can boot from a SD cardslot on the carrierboard by setting the bootmode control pins as follow:...
(4pin) 5.15.1. Power Management Signals The PICO-IMX8M has the following set of signals to control the system power states such as the power-on and reset conditions. This enables the system designer to implement a fully ACPI compliant system supporting system states.
The PICO-IMX8M is available in a number of standard configurations. Custom tailored versions with other memory configuration, de-population of interfaces or extended and industrial temperature options are available upon request. Standard part numbers can be easily found on the PICO-IMX8M product page on the TechNexion corporate homepage. 6.2. Custom Part Number Rule The PICO-IMX8M can be ordered in custom tailored configuration to meet special application requirements and conditions according to the following custom part number creation rules.
Information published by TechNexion regarding third-party products or services does not constitute a license from TechNexion to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TechNexion under the patents or other intellectual property of TechNexion.
To the extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by TechNexion Ltd., its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or inaccuracies in this document.
Need help?
Do you have a question about the PICO-IMX8M and is the answer not in the manual?
Questions and answers