NXP Semiconductors K32 L2A Series Reference Manual

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K32 L2A Reference Manual

K32L2A41VLL1A, K32L2A31VLL1A, K32L2A41VLH1A,

K32L2A31VLH1A

Document Number: K32L2AxRM

Rev. 2, 01/2020

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Page 1 K32 L2A Reference Manual K32L2A41VLL1A, K32L2A31VLL1A, K32L2A41VLH1A, K32L2A31VLH1A Document Number: K32L2AxRM Rev. 2, 01/2020...
Page 2 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 3: Table Of Contents
3.3.2 Analog reference options..........................52 Core Modules................................53 3.4.1 Introduction..............................53 3.4.2 Arm Cortex M0+ core ...........................53 3.4.3 Debug facilities.............................. 54 3.4.4 Buses, interconnects, and interfaces......................54 3.4.5 System tick timer............................54 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 4 Low Power Timer (LPTMR)......................... 78 3.8.4 RTC configuration............................79 Communication interfaces............................80 3.9.1 Universal Serial Bus (USB) FS Subsystem....................80 3.9.2 LPSPI configuration............................86 3.9.3 LPI2C................................87 3.9.4 LPUART configuration..........................88 3.9.5 EMVSIM Configuration..........................89 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 5 AIPS1 Peripheral Slot Assignments......................103 Chapter 5 Clock Distribution Introduction...................................107 Clock Sources................................108 SCG Output Clocks..............................109 5.3.1 DIVCORE_CLK............................109 5.3.2 DIVSLOW_CLK............................109 5.3.3 Peripheral functional clocks...........................109 Peripheral Clock Summary............................112 DIV3 Peripheral Clocking............................114 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 6 RESET_b pin ..............................128 6.2.5 Debug resets..............................129 Boot....................................129 6.3.1 Boot sources..............................129 6.3.2 FOPT boot options............................130 6.3.3 Boot sequence..............................131 Chapter 7 Power Management Introduction...................................135 Clocking modes................................135 7.2.1 Partial Stop..............................135 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 7 Debug resets..................................155 Micro Trace Buffer (MTB)............................156 Debug in low-power modes............................156 Debug and security............................... 157 Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................159 10.2 Pinout.................................... 159 10.2.1 Package types..............................159 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 8 11.3.2 ADC Configuration Register 1 (ADCx_CFG1).....................184 11.3.3 ADC Configuration Register 2 (ADCx_CFG2).....................185 11.3.4 ADC Data Result Register (ADCx_Rn)......................186 11.3.5 Compare Value Registers (ADCx_CVn)....................... 188 11.3.6 Status and Control Register 2 (ADCx_SC2)....................189 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 9 Conversion control............................204 11.4.5 Automatic compare function..........................212 11.4.6 Calibration function............................213 11.4.7 User-defined offset function.......................... 215 11.4.8 Temperature sensor............................216 11.4.9 MCU wait mode operation..........................217 11.4.10 MCU Normal Stop mode operation....................... 217 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 10 13.4 Application information..............................244 Chapter 14 Kinetis ROM Bootloader 14.1 Chip-Specific Information............................247 14.1.1 Kinetis Bootloader Peripheral Pinmux......................247 14.1.2 Bootloader Memory Access...........................248 14.2 Introduction...................................248 14.3 Functional Description..............................250 14.3.1 Memory Maps..............................250 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 11 Kinetis Bootloader Status Error Codes......................... 319 Chapter 15 Cryptographic Acceleration Unit (CAU) 15.1 Introduction...................................323 15.2 CAU Block Diagram..............................323 15.3 Overview..................................325 15.4 Features..................................326 15.5 Memory map/Register definition..........................326 15.5.1 Status Register (CAUx_CASR)........................328 15.5.2 Accumulator (CAUx_CAA).......................... 329 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 12 DAC Control Register (CMPx_DACCR)...................... 354 16.2.6 MUX Control Register (CMPx_MUXCR)....................355 16.3 Functional description..............................356 16.3.1 CMP functional modes...........................356 16.3.2 Power modes..............................366 16.3.3 Startup and operation............................. 367 16.3.4 Low-pass filter............................... 368 16.4 CMP interrupts................................370 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 13 Functional description..............................379 17.3.1 CRC initialization/reinitialization........................379 17.3.2 CRC calculations............................380 17.3.3 Transpose feature............................381 17.3.4 CRC result complement..........................383 Chapter 18 12-bit Digital-to-Analog Converter (DAC) 18.1 Introduction...................................385 18.2 Features..................................385 18.3 Block diagram................................385 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 14 DMA channels with periodic triggering capability..................399 19.4.2 DMA channels with no triggering capability....................401 19.4.3 Always-enabled DMA sources........................401 19.5 Initialization/application information........................... 403 19.5.1 Reset................................403 19.5.2 Enabling and configuring sources........................403 Chapter 20 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 15 20.3.18 Error Register (DMAx_ERR)........................435 20.3.19 Hardware Request Status Register (DMAx_HRS)..................437 20.3.20 Enable Asynchronous Request in Stop Register (DMAx_EARS)..............439 20.3.21 Channel n Priority Register (DMAx_DCHPRIn)..................440 20.3.22 TCD Source Address (DMAx_TCDn_SADDR)................... 441 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 16 Fault reporting and handling.......................... 458 20.4.3 Channel preemption............................461 20.4.4 Performance..............................461 20.5 Initialization/application information........................... 465 20.5.1 eDMA initialization............................465 20.5.2 Programming errors............................467 20.5.3 Arbitration mode considerations........................468 20.5.4 Performing DMA transfers..........................468 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 17 21.5.14 Transmitter Guard ETU Value Register (EMVSIMx_TX_GETU)............... 507 21.5.15 Character Wait Time Value Register (EMVSIMx_CWT_VAL)..............508 21.5.16 Block Wait Time Value Register (EMVSIMx_BWT_VAL)................ 508 21.5.17 Block Guard Time Value Register (EMVSIMx_BGT_VAL)............... 509 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 18 FLEXIO Register Descriptions........................535 22.3 Functional description..............................565 22.3.1 Shifter operation.............................565 22.3.2 Timer operation..............................571 22.3.3 Pin operation..............................573 22.4 Application Information..............................575 22.4.1 UART Transmit............................. 575 22.4.2 UART Receive............................... 576 22.4.3 SPI Master..............................578 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 19 Introduction...................................603 24.1.1 Features................................604 24.1.2 Block Diagram............................... 604 24.1.3 Glossary................................. 605 24.2 External Signal Description............................606 24.3 Memory Map and Registers............................607 24.3.1 Flash Configuration Field Description......................607 24.3.2 Program Flash IFR Map..........................607 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 20 25.2.2 Channel n Vector Number Register (INTMUXx_CHn_VEC)..............660 25.2.3 Channel n Interrupt Enable Register (INTMUXx_CHn_IER_31_0)............661 25.2.4 Channel n Interrupt Pending Register (INTMUXx_CHn_IPR_31_0)............661 25.3 Functional Description..............................662 25.3.1 Configuring Output Channels........................662 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 21 26.4.2 VLLS modes..............................691 26.4.3 Initialization..............................692 Chapter 27 Low Power Inter-Integrated Circuit (LPI2C) 27.1 Introduction...................................693 27.1.1 Overview................................ 693 27.1.2 Features................................693 27.1.3 Block Diagram............................... 694 27.1.4 Modes of operation............................695 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 22 27.2.23 Slave Configuration Register 2 (LPI2Cx_SCFGR2)..................726 27.2.24 Slave Address Match Register (LPI2Cx_SAMR)..................727 27.2.25 Slave Address Status Register (LPI2Cx_SASR)................... 728 27.2.26 Slave Transmit ACK Register (LPI2Cx_STAR)................... 729 27.2.27 Slave Transmit Data Register (LPI2Cx_STDR).................... 729 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 23 Timer Value Register (LPITx_TVALn)......................755 28.3.9 Current Timer Value (LPITx_CVALn)......................756 28.3.10 Timer Control Register (LPITx_TCTRLn)....................756 28.4 Functional description..............................758 28.4.1 Initialization..............................758 28.4.2 Timer Modes..............................759 28.4.3 Trigger Control for Timers..........................760 28.4.4 Channel Chaining............................760 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 24 29.2.14 Transmit Command Register (LPSPIx_TCR)....................780 29.2.15 Transmit Data Register (LPSPIx_TDR)......................783 29.2.16 Receive Status Register (LPSPIx_RSR)......................784 29.2.17 Receive Data Register (LPSPIx_RDR)......................785 29.3 Functional description..............................785 29.3.1 Clocking and Resets............................785 29.3.2 Master Mode..............................786 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 25 LPTMR counter............................. 803 30.4.6 LPTMR hardware trigger..........................804 30.4.7 LPTMR interrupt............................804 Chapter 31 Low Power Universal Asynchronous Receiver/Transmitter (LPUART) 31.1 Introduction...................................807 31.1.1 Features................................807 31.1.2 Modes of operation............................808 31.1.3 Signal Descriptions............................808 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 26 Chapter 32 Memory-Mapped Divide and Square Root (MMDVSQ) 32.1 Introduction...................................851 32.1.1 Features................................851 32.1.2 Block diagram..............................852 32.1.3 Modes of operation............................853 32.2 External signal description............................854 32.3 Memory map and register definition..........................854 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 27 34.3 Chip Configuration and Boot............................877 34.4 MSCM Memory Map/Register Definition........................878 34.4.1 CPU Configuration Memory Map and Registers...................878 34.4.2 Processor X Type Register (MSCM_CPxTYPE)..................879 34.4.3 Processor X Number Register (MSCM_CPxNUM)..................880 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 28 Peripheral Clock Control (PCC) 36.1 Introduction...................................923 36.1.1 Features................................923 36.2 Memory map and register definition..........................924 36.2.1 PCC Register Descriptions..........................924 36.2.2 PCC Register Descriptions..........................957 36.3 Functional description..............................975 Chapter 37 Power Management Controller (PMC) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 29 38.2.1 Overview................................ 992 38.2.2 Features................................992 38.2.3 Modes of operation............................993 38.3 External signal description............................994 38.4 Detailed signal description............................994 38.5 Memory map and register definition..........................994 38.5.1 Pin Control Register n (PORTx_PCRn)......................1001 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 30 Mode Register (RCM_MR)........................... 1022 39.2.6 Force Mode Register (RCM_FM)........................1023 39.2.7 Sticky System Reset Status Register (RCM_SSRS)..................1024 39.2.8 System Reset Interrupt Enable Register (RCM_SRIE)................. 1026 Chapter 40 General-Purpose Input/Output (GPIO) 40.1 Introduction...................................1029 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 31 Chapter 41 Real Time Clock (RTC) 41.1 Introduction...................................1041 41.1.1 Features................................1041 41.1.2 Modes of operation............................1041 41.1.3 RTC signal descriptions..........................1042 41.2 Register definition.................................1042 41.2.1 RTC Time Seconds Register (RTC_TSR)..................... 1043 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 32 VLPR Clock Control Register (SCG_VCCR)....................1064 42.2.6 HSRUN Clock Control Register (SCG_HCCR)....................1066 42.2.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG)..............1067 42.2.8 System OSC Control Status Register (SCG_SOSCCSR)................1069 42.2.9 System OSC Divide Register (SCG_SOSCDIV)..................1071 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 33 43.2.6 Unique Identification Register Mid-High (SIM_UIDMH)................1103 43.2.7 Unique Identification Register Mid Low (SIM_UIDML)................1104 43.2.8 Unique Identification Register Low (SIM_UIDL)..................1104 43.2.9 Peripheral Clock Status Register (SIM_PCSR)..................... 1105 43.3 Functional description..............................1106 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 34 Memory Map and Registers............................1133 45.2.1 Register file register (RFSYS_REGn)......................1133 Chapter 46 Timer/PWM Module (TPM) 46.1 Introduction...................................1135 46.1.1 TPM Philosophy............................1135 46.1.2 Features................................1135 46.1.3 Modes of operation............................1136 46.1.4 Block diagram..............................1136 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 35 Counter................................1160 46.4.4 Input Capture Mode............................1163 46.4.5 Output Compare Mode...........................1164 46.4.6 Edge-Aligned PWM (EPWM) Mode......................1165 46.4.7 Center-Aligned PWM (CPWM) Mode......................1167 46.4.8 Combine PWM mode.............................1169 46.4.9 Combine Input Capture mode........................1172 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 36 Another TRNG usage example........................1264 Chapter 49 Touch Sensing Input (TSI) 49.1 Introduction...................................1265 49.1.1 Features................................1265 49.1.2 Modes of operation............................1266 49.1.3 Block diagram..............................1266 49.2 External signal description............................1267 49.2.1 TSI[15:0]................................ 1267 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 37 50.2.1 Time Stamp Timer Register Low (TSTMRx_L)................... 1288 50.2.2 Time Stamp Timer Register High (TSTMRx_H)..................1288 50.3 Functional description..............................1289 Chapter 51 Universal Serial Bus Full Speed OTG Controller (USBFSOTG) 51.1 Introduction...................................1291 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 38 51.4.10 Interrupt Enable register (USBx_INTEN)..................... 1314 51.4.11 Error Interrupt Status register (USBx_ERRSTAT)..................1315 51.4.12 Error Interrupt Enable register (USBx_ERREN)...................1316 51.4.13 Status register (USBx_STAT)........................1317 51.4.14 Control register (USBx_CTL)........................1318 51.4.15 Address register (USBx_ADDR)........................1319 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 39 OTG dual role A device operation......................... 1337 51.7.2 OTG dual role B device operation......................... 1338 51.8 Device mode FIRC operation............................1340 Chapter 52 USB Voltage Regulator (VREG) 52.1 Introduction...................................1341 52.1.1 Overview................................ 1341 52.1.2 Features................................1342 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 40 Memory map and register definition..........................1359 54.2.1 Watchdog Control and Status Register (WDOGx_CS)................. 1359 54.2.2 Watchdog Counter Register (WDOGx_CNT)....................1361 54.2.3 Watchdog Timeout Value Register (WDOGx_TOVAL)................1362 54.2.4 Watchdog Window Register (WDOGx_WIN)....................1363 54.3 Functional description..............................1363 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 41 Configuring the Watchdog Once........................1365 54.3.3 Clock source..............................1367 54.3.4 Using interrupts to delay resets........................1368 54.3.5 Backup reset..............................1368 54.3.6 Functionality in debug and low-power modes....................1369 54.3.7 Fast testing of the watchdog...........................1369 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 42 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 43: About This Document
Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In some cases, hexadecimal numbers are shown with the prefix 0x. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 44: Typographic Notation
In some cases, deasserted signals are described as negated. reserved Refers to a memory space, register, or field that is either reserved for future use or for which, when written to, the module or chip behavior is unpredictable. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 45: Introduction
• Ambient operating temperature ranges from –40 °C to 105 °C. 2.3 Feature Summary The following table lists the features of this device. Table 2-1. Feature Summary Feature Details Hardware Characteristics Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 46 Cyclic Redundancy Check module (CRC) Memory Flash memory 512 KB flash Random-access memory (RAM) 128 KB Read-Only Memory (ROM) 32 KB System Register File 32 bytes Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 47 16 x 12-bit data buffer, true FIFO mode available Timers 16-bit timer/pwm module 0 (TPM0) 6 channels, basic TPM function supporting input filter, dead-time insertion and quadrature decode Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 48 1 standalone module supporting ISO 7816 smart card communications Interface Module (EMVSIM) FlexIO 1 FlexIO Support a wide range of protocols including, but not limited to: UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform generation K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 49: Block Diagram
Details 8 Shift registers and 8 Timers 8/16/24-bit smart LCD drive Functional in STOP/VLPS modes DMA support 2.4 Block Diagram The below figure shows a top-level block diagram of the device. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 50 Bus Components Platform Domain AHB32 AIPS0 IPBUS Core Memory- CM0+ Platform Reference Mapped Module AIPS1 IPBUS Memory protection Other Module such Analog Domain Gaskets as test/analog exsc Figure 2-1. Block Diagram K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 51: Chip Configuration
AIPS1 bridges. • The core and DMA0 can freely access all peripherals. 3.2 Clock gating Peripherals on the AIPS0/AIPS1 bridges have clock gating capability via a Peripheral Clock Control module (PCC). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 52: Module To Module Interconnects
2 - VDDA 3 - Reserved 12-bit DAC 1 - VDDA Selected by DACx_C0[DACRFS] bit 2 - VREFH/VREFO CMP with 6-bit DAC Vin1 - VDD Selected by CMPx_DACCR[VRSEL] Vin2 - VREFH/VREFO K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 53: Core Modules
Do not force all registers to be async reset Multiplier SMUL 0 = Fast Mul Implements single-cycle multiplier Multi-drop Support SWMD 0 = Absent Do not include serial wire support for multi- drop Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 54: Debug Facilities
CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS field in the SysTick Calibration Value Register is always 0. 3.4.6 Caches This device does not include any processor cache memories. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 55: Interrupt Connections
Peripheral int INTMUX1 INTMUX0 Peripheral int Peripheral int Figure 3-1. Interrupt Routing Block Diagram The CPU can mask off any interrupt connected to the 32-slot NVIC0 module. The INTMUX0 module allows: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 56 DMA0 channel 3 or 7 transfer complete 0x0000_0050 CTI0, DMA0_error Cross Trigger Interface 0 and DMA0 channel errors Off Platform vectors — — — — Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 57 0x0000_00AC RTC Secs Real Time Clock Seconds 0x0000_00B0 INTMUX0-0 Selectable peripheral interrupt INTMUX0-0 0x0000_00B4 INTMUX0-1 Selectable peripheral interrupt INTMUX0-1 0x0000_00B8 INTMUX0-2 Selectable peripheral interrupt INTMUX0-2 0x0000_00BC INTMUX0-3 Selectable peripheral interrupt INTMUX0-3 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 58 Peripheral Interrupt Source LPTMR1 Reserved Reserved Reserved LSPI2 LPUART2 EMVSIM LPI2C2 FTFA WDOG0 DAC0 TRNG CMP0 CMP1 RTC Alarm Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 59: Asynchronous Wake-Up Interrupt Controller (Awic)
Port control module—any enabled pin interrupt is capable of waking the system. The ADC is functional when using internal clock source. Interrupt in normal or trigger mode Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 60: System Modules
The slaves connected to the crossbar switch are assigned as follows: AXBS0 Slave module Slave port number Flash memory controller and Boot ROM Core 0 SRAM controller Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 61: Low-Leakage Wake-Up Unit (Llwu)
PTC3 LLWU_P8 PTC4 LLWU_P9 PTC5 LLWU_P10 PTC6 LLWU_P11 PTC11 LLWU_P12 PTD0 LLWU_P13 PTD2 LLWU_P14 PTD4 LLWU_P15 PTD6 LLWU_P16 PTE6 LLWU_P17 Reserved LLWU_P18 Reserved LLWU_P19 PTE17 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 62: Dmamux
Source module Source description Async DMA capable — Channel disabled — FlexIO0 Shifter 0 FlexIO0 Shifter 1 FlexIO0 Shifter 2 FlexIO0 Shifter 3 FlexIO0 Shifter 4 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 63 TPM0 Overflow TPM1 Channel 0 TPM1 Channel 1 TPM1 Overflow TPM2 Channel 0 TPM2 Channel 1 TPM2 Overflow Reserved — — EMVSIM Receive EMVSIM Transmit Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 64: Watchdog (Wdog)
• bus clock • 8 MHz or 2 MHz internal reference clock • external crystal 3.5.5 System Register File Configuration This section summarizes how the module has been configured in the chip. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 65: Peripheral Clock Control (Pcc) Configuration
3.5.6 Peripheral Clock Control (PCC) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 66: System Register File Configuration
Figure 3-4. System Register file configuration Table 3-11. Reference links to related information Topic Related module Reference Full description Register file Register file System memory map System memory map Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 67: Security
Figure 3-5. CAU configuration 3.6.1.1 CAU Overview The CAU provides security encrypt/decrypt acceleration to allow users to share secure data with external devices via a serial communication port (such as an LPUART module). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 68: Analog
This device contains one 16-bit successive approximation ADC with up to ~30 to 38 channels. The ADC supports both software and hardware triggers. The number of ADC channels present on the device is determined by the pinout of the specific device package. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 69 ADC0_SE13 01110 AD14 Reserved ADC0_SE14 01111 AD15 Reserved ADC0_SE15 10000 AD16 Reserved ADC0_SE16 10001 AD17 Reserved ADC0_SE17 10010 AD18 Reserved ADC0_SE18 10011 AD19 Reserved ADC0_SE19 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 70: Cmp Configuration
The ADC module clock is sourced from the Peripheral Clock Control (PCC) module. 3.7.2 CMP configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 71 CMP. The CMPs can be optionally on in all modes except VLLS0. 3.7.2.2 CMP connections The following table shows the fixed internal connections to the CMPs. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 72: Vref
PTB21, PTC4 3.7.3 VREF 3.7.3.1 VREF Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 73 For either an internal or external reference if the VREF_OUT functionality is being used, VREF_OUT signal must be connected to an output load capacitor. Refer to the device data sheet for more details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 74: 12-Bit Dac Configuration
Port control Signal multiplexing 3.7.4.1 12-bit DAC instantiation information This device contains one 12-bit digital-to-analog converter (DAC) with programmable reference generator output. The DAC includes a 16-word FIFO for DMA support. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 75: Timers
Other Signal peripherals multiplexing Figure 3-10. TPM configuration Table 3-18. Reference links to related information Topic Related module Reference Full description Timer/PWM module Timer/PWM module Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 76 (synchronized to the TPM clock source). The external clock can be either TPM0_CLKIN or TPM1_CLKIN. NOTE The selected external clock must be less than half the frequency of the TPM clock source. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 77: Lpit
DMAMUX trigger is configured in the Trigger MUX module (TRGMUX). Table 3-21. LPIT0 channel assignments for periodic DMA triggering LPIT0 channel DMA channel number LPIT0 Channel 0 DMA0 Channel 0 LPIT0 Channel 1 DMA0 Channel 1 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 78: Low Power Timer (Lptmr)
LPTMRx_CSR[TPS] Pulse counter input LPTMR0 input source LPTMR1 input source number CMP0 output LPTMR0 trigger LPTMR0_ALT1 pin LPTMR1_ALT1 pin LPTMR0_ALT2 pin LPTMR1_ALT2 pin LPTMR0_ALT3 pin LPTMR1_ALT3 pin K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 79: Rtc Configuration
3.8.4 RTC configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 80: Communication Interfaces
USB device mode only. NOTE USB OTG is not functional in VLPx, VLLSx, and any Stop modes. NOTE For the USB FS OTG controller to operate, the minimum system clock frequency is 20 MHz. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 81 Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting the USBx_USBTRC0[USBRESMEN] bit enables this function. The following wakeup feature is also supported: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 82 USB regulator is enabled to power the USB transceiver. 2 AA Cells To PMC and Pads VOUT33 Cstab Chip TYPE A VREGIN VBUS Regulator USB0_DP USB0_DM Controller XCVR Figure 3-13. USB regulator AA cell usecase K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 83 The chip can also be powered by the USB bus directly. In this case, VOUT33 is connected to VDD. The USB regulator must be enabled by default to power the MCU, then to power USB transceiver or external sensor. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 84 GPIO pin does not directly support a 5V input. 3.9.1.5 USB controller configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 85 3.9.1.6 USB Voltage Regulator Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 86: Lpspi Configuration
USB SRAM. 3.9.2 LPSPI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 87: Lpi2C
Table 3-25. Reference links to related information Topic Related module Reference Full description LPI2C LPI2C System memory map — System memory map Clocking — Clock distribution Signal multiplexing Port control Signal multiplexing K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 88: Lpuart Configuration
Port control Signal multiplexing 3.9.4.1 LPUART overview The LPUART modules support the basic UART with DMA interface function and x4 to x32 oversampling of baud-rate. This module supports LIN slave operation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 89: Emvsim Configuration
Table 3-27. Reference links to related information Topic Related module Reference Full description FlexIO FlexIO System memory map — System memory map Clocking — Clock distribution Trigger Input Selection TRGMUX TRGMUX Signal multiplexing Port control Signal multiplexing K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 90: Human-Machine Interfaces (Hmi)
Full description GPIO GPIO System memory map — System memory map Clocking — Clock distribution Power management — Power management Crossbar switch Crossbar switch Crossbar switch Signal multiplexing Port control Signal multiplexing K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 91: Tsi Configuration
GPIO space can be accomplished referencing the address 0x4000_F000. 3.10.2 TSI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 92 The number of TSI channels present on the device is determined by the pinout of the specific device package, and is shown in the following table. Table 3-30. Number of TSI channels Device TSI channels 100 LQFP, 64 LQFP K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 93: Signal Multiplexing Integration
Reference Full description Port control Port control System memory map System memory map Clocking Clock Distribution Register access Peripheral bus Peripheral bridge controller 3.11.1.1 Clock gating See the Clock distribution chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 94 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 95: Memory Map
64 KB located at 0x2000_0000-0x2000_FFFF VLLS0/VLLS1 None - All System SRAM powered down All other power modes All 128 KB retained 4.3 System Memory Map There is 1 memory map: • Memory Map K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 96 Reserved 0x4120_0000 0x43FF_FFFF Reserved 0x4400_0000 0x5FFF_FFFF BME (AIPS0 and AIPS1) (448 External RAM 0x6000_0000 0xDFFF_FFFF Reserved 0xE000_0000 0xE0FF_FFFF PPB - Arm SYS Modules 0xE100_0000 0xE1FF_FFFF Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 97: Flash Memory Maps
Reserved 0xF120_0000 0xF7FF_FFFF Reserved 0xF800_0000 0xF80F_FFFF SYS IOPORT 0xF810_0000 0xF8FF_FFFF Reserved 0xF900_0000 0xF90F_FFFF Reserved 0xF910_0000 0xFFFF_FFFF Reserved 4.4 Flash Memory Maps There is 1 flash memory map: • Flash Memory Map K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 98: Sram Memory Map
2 KB 4010 07FF Figure 4-2. SRAM Memory Map 4.6 Bit Manipulation Engine The Bit Manipulation Engine (BME2) provides hardware support for atomic read- modify-write memory operations to the peripheral address space. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 99: Peripheral Bridge (Aips-Lite) Memory Map
AIPS0 (no overlap of peripherals) System 32-bit base address Slot Source Module 0x4000_0000 Reserved 0x4000_1000 Miscellaneous System Control Module (MSCM) 0x4000_2000 Reserved 0x4000_3000 Reserved 0x4000_4000 Reserved 0x4000_5000 Reserved Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 100 Flash Memory Unit 0x4002_1000 DMA0 channel multiplexer 0 (DMAMUX0) 0x4002_2000 Reserved 0x4002_3000 Reserved 0x4002_4000 INTMUX0 0x4002_5000 Reserved 0x4002_6000 Reserved 0x4002_7000 TRGMUX 0x4002_8000 Reserved 0x4002_9000 Reserved Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 101 Reserved 0x4004_4000 Reserved 0x4004_5000 Reserved 0x4004_6000 LPUART2 0x4004_7000 Reserved 0x4004_8000 Reserved 0x4004_9000 Reserved 0x4004_A000 Reserved 0x4004_B000 Reserved 0x4004_C000 Reserved 0x4004_D000 Reserved 0x4004_E000 EVMSIM0 0x4004_F000 Reserved Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 102 0x4006_A000 DAC0 0x4006_B000 Reserved 0x4006_C000 Reserved 0x4006_D000 Reserved 0x4006_E000 CMP0 0x4006_F000 Reserved 0x4007_0000 Reserved 0x4007_1000 Reserved 0x4007_2000 VREF 0x4007_3000 Reserved 0x4007_4000 0x4007_5000 SIM / TSTMR0 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 103: Aips1 Peripheral Slot Assignments
Reserved 0x4008_8000 Reserved 0x4008_9000 Reserved 0x4008_A000 Reserved 0x4008_B000 Reserved 0x4008_C000 Reserved 0x4008_D000 Reserved 0x4008_E000 Reserved 0x4008_F000 Reserved 0x4009_0000 Reserved 0x4009_1000 Reserved 0x4009_2000 Reserved 0x4009_3000 Reserved Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 104 0x400A_D000 TPM1 0x400A_E000 Reserved 0x400A_F000 Reserved 0x400B_0000 Reserved 0x400B_1000 Reserved 0x400B_2000 Reserved 0x400B_3000 Reserved 0x400B_4000 Reserved 0x400B_5000 Low-power Timer 1 (LPTMR1) 0x400B_6000 Reserved 0x400B_7000 Reserved Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 105 Reserved 0x400D_1000 Reserved 0x400D_2000 Reserved 0x400D_3000 Reserved 0x400D_4000 Reserved 0x400D_5000 Reserved 0x400D_6000 Reserved 0x400D_7000 Reserved 0x400D_8000 Reserved 0x400D_9000 Reserved 0x400D_A000 Reserved 0x400D_B000 Reserved 0x400D_C000 Reserved Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 106 0x400F_0000 Reserved 0x400F_1000 Reserved 0x400F_2000 Reserved 0x400F_3000 Reserved 0x400F_4000 Reserved 0x400F_5000 Reserved 0x400F_6000 Reserved 0x400F_7000 Reserved 0x400F_8000 Reserved 0x400F_9000 Reserved 0x400F_A000 0x400F_B000 Reserved 0x400F_C000 Reserved 0x400F_D000 Reserved 0x400F_E000 Reserved 0x400F_F000 Reserved K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 107: Clock Distribution
The second peripheral functional clock is selected via the Peripheral Clock Control (PCC) module. The SCG provides additional peripheral functional clocks with optional dividers via the PCC module The following diagram shows the various clock sources and clock trees for K32 L2A. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 108: Clock Sources
• FIRC – output of the fast ( 48-60MHZ) internal RC oscillator • SPLL – output of the PLL, which is multiple of the SOSC or FIRC clock source. The configuration of these clock sources are detailed in the chapter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 109: Scg Output Clocks
Each of the four clock sources can provide three additional output clocks that are generally used as alternative peripheral functional clocks. This provides flexible clocking in a SoC, and allows groups of peripherals to be clocked by one specific functional clock, K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 110 This output clock is fed from the SIRC, and is an optional functional clock for peripherals. For K32 L2A the SIRCDIV1_CLK is an optional peripheral functional clock for the USB0 module only. It is selectable via the PCCUSB0 register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 111 This output clock is fed from the FIRC, and is an optional functional clock for peripherals. For K32 L2A the FIRCDIV3_CLK is an optional peripheral functional clock for various timers and serial communication peripherals. It is selectable via the peripherals PCCn register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 112: Peripheral Clock Summary
Bus Interface Peripheral PCCn Functional Clock Clock Gating Functional Clock Clock Divider Control System Coretex M0+ Core Chip Reset DIVCORE_CLK controller DMA controller Chip Reset DIVCORE_CLK Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 113 System Register DIVSLOW_CLK File Analog Chip Reset not DIVSLOW_CLK VLLS Chip Reset DIVSLOW_CLK SCG DIV3 VREF Chip Reset DIVSLOW_CLK Chip Reset DIVSLOW_CLK Chip Reset DIVSLOW_CLK Timers Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 114: Div3 Peripheral Clocking
DIVSLOW_CLK output. The PCC can then choose one of four optional peripheral functional clocks from the existing four clock sources within the SCG. The PCC can also provide inputs for clock sources external to the SCG. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 115: Div1 Peripheral Clocking
DIVCORE_CLK output providing a direct 1:1 interface to the CPU. The PCC can then choose one of four optional clocks from the existing four clock sources within the SCG. The PCC can also provide inputs for clock sources external to the SCG. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 116: Programming Model
SCG. These xxxxDIVy_CLK outputs are fed to the PCC module where the peripheral can select one of these alternative clock sources to clock the timing function of that peripheral. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 117: Other Clock Sources
SCG. It is controlled via the PMC module. It provides an optional clock input for peripherals that are required to operate in low power modes 5.9 Clock definitions The following table describes the clocks in this device. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 118: Clocking Details
Clock Frequency Clock Frequency disabled when… DIVCORE_CLK Up to 72 MHz Up to 8 MHz Up to 96 MHz When both CPUs are in any stop Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 119: Internal Clocking Requirements
DIVSLOW_CLK should not exceed 24 MHz for reliable flash memory operation • The DIVCORE_CLK should not exceed 96MHz in High Speed RUN mode. The DIVSLOW_CLK should not exceed 24 MHz for reliable flash memory operation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 120: Clock Divider Values After Reset
The PLL, FIRC and SOSC are disabled out of reset. All peripheral clocks xxxDIVy_CLK’s are disabled out of reset. The speed of the DIVCORE_CLK and DIVSLOW_CLK out of reset can be modified by programming NVM(IFR) register bits. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 121: Clock Gating
5.14 Flash Memory Clock The embedded Flash memory has a maximum operating frequency of 25Mhz. This device uses the DIVSLOW_CLK from the SCG. This clock output should not exceed 25MHz for reliable flash operation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 122 Flash Memory Clock K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 123: Reset And Boot
The microcontroller can exit and reset in functional mode where the Core is executing code (default) or the Core is in a debug halted state. There are several boot options that can be configured. See Boot for more details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 124: Reset
The pins with analog functions assigned to them default to their analog function after reset. During and following a reset, the SWD pins have their associated input pins configured • SWD_CLK in pulldown (PD) • SWD_DIO in pullup (PU) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 125 PMC_LVDSC1[LVDV]. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold. RCM_SRS[LVD] is set following either an LVD reset or POR. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 126 The SCG module contains a clock monitor with reset and interrupt request capability for SPLL and SOSC clocks. NOTE To prevent unexpected reset events, all clock monitors must be disabled before entering any low-power modes, including VLPR and VLPW. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 127: Mcu Resets
To hold the core in reset as the rest of the chip comes out of system reset, set the Core Hold Reset field in the MDM-AP control register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 128: Reset_B Pin
When the RESET pin is disabled and configured as a GPIO output, it operates as a pseudo open drain output. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 129: Debug Resets
This device supports booting from internal flash and RAM. 1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available during System Reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 130: Fopt Boot Options
When this option is selected, there could be a short period of contention during a POR ramp where the device drives the pin low prior to establishing the Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 131 Device is configured for RUN mode on exit from reset. Core and system clock divider (SCG_RCCR[DIVCORE]) is 0x0 (divide by 1). Device is configured for RUN mode on exit from reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 132: Boot Sequence
Exception Entry and reads the NMI interrupt handler address from vector-table offset 8. The CPU begins execution at the NMI interrupt handler. • When FTFA_FOPT[BOOTPIN_OPT] = 0, it forces boot from ROM if NMI/ BOOTCFG0 pin asserted. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 133 If the NMI function is not required, either for an interrupt or wake up source, it is recommended that the NMI function be disabled by clearing NMI_DIS in the FOPT register. Subsequent system resets follow this same reset flow. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 134 FAST_INIT cleared? CPU begins execution at NMI Interrupt Handler Slower Clock Faster Clock is used is used for Flash init for Flash init Figure 6-1. Boot Sequence K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 135: Power Management
If configured, a DMA request (using the asynchronous DMA wakeup) can also be used to exit Partial Stop for the duration of a DMA transfer before the device is transitioned back into PSTOP2. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 136: Dma Wakeup
Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes the SCG and PMC would then also enter their appropriate modes. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 137: Compute Operation
VLPS mode. The SCG, PMC, SRAM, and Flash read port are not affected by Compute Operation, although the Flash register interface is disabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 138: Peripheral Doze
• The CPU is in Stop mode, including the entry sequence and for the duration of a DMA wakeup. • The CPU is in Compute Operation, including the entry sequence and for the duration of a DMA wakeup. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 139: Clock Gating
GPIO port pads are powered directly from VDD. 7.4 Power modes The System Mode Controller (SMC) provides multiple power options to allow the user to optimize power consumption for the level of functionality needed . K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 140 • TPM and UART can optionally be enabled if their clock source is enabled. • NVIC is disabled (FCLK = OFF); AWIC is used to wake up from interrupt. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 141 • The 16-byte system register file remains powered for customer- critical data • LPO disabled, optional POR brown-out detection 1. Resumes Normal Run mode operation by executing the LLWU interrupt service routine. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 142: Entering And Exiting Power Modes
FF. • Async = Fully functional with alternate clock source, provided the selected clock source remains enabled • SR = Module state is retained but not functional. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 143 SR in LLS3, partial SR in VLLS3, SR in LLS2. partial SR in VLLS2 , OFF in VLLS0/1. System Register File Communication interfaces Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 144 FF in PSTOP2 6-bit DAC SR, OFF in VLLS0 SR in CPO FF in PSTOP2 12-bit DAC SR in CPO FF in PSTOP2 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 145 8. CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS or VLLSx only supports low speed external pin to pin or external pin to DAC compares. 9. TSI wake-up from all low-power modes is limited to a single selectable pin. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 146 Module operation in low-power modes K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 147: Security
Both Flash0 and Flash1 are available to the user for application code. The Flash security follows the structure for other L series devices. The FTFx module (using FTFx_FSEC register) provides security features: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 148 (SWD) or from user code execution. When the flash is secured (FTFA_FSEC[SEC] = 00, 01, or 11), the programmer interfaces are only allowed to launch mass erase operations. Additionally, in this mode, the debug port has no access to memory locations. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 149: Debug
This pin is pulled down internally. SWD_DIO Input / Output Serial Wire Debug Data Input/Output The SWD_DIO pin is used by an external debug tool for communication and device control. This pin is pulled up internally. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 150: Debug And Trace Block Diagram
• The device has 1 Arm based Debug Port (DP) that supports the SWD interface. The DP module connects to a Miscellaneous Debug Module Access Port (MDM-AP) and 2 AHB Access Ports (AHB-AP0 and AHB-AP1). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 151: Swd Status And Control Registers
Table 9-3. MDM-AP register summary Address Register Description 0x0100_0000 Status MDM-AP Status Register 0x0100_0004 Control MDM-AP Control Register 0x0100_00FC Read-only identification register that always reads as 0x001C_0020 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 152: Mdm-Ap Control Register
Set to disable debug. Clear to allow debug operation. When set, it overrides the C_DEBUGEN bit within the DHCSR and force disables Debug logic. Debug Request Set to force the core to halt. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 153: Mdm-Ap Status Register
This bit is used by the debugger to clear the sticky LLS and VLLSx mode entry status bits. This bit is asserted and cleared by the debugger. 8– Reserved for future use 1. Command available in secure mode K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 154 LLS was exited, and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 155: Debug Resets
• SYSRESETREQ field in the NVIC Application Interrupt and Reset control register • A system reset in the DAP control register which allows the debugger to hold the core in reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 156: Micro Trace Buffer (Mtb)
Stop or VLPS, FCLK continues to run to support core register access. In these modes in which FCLK is left active the debug modules have access to core registers but not to system memory resources accessed via the crossbar. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 157: Debug And Security
(FSEC[MEEN] = 10), attempts to mass erase via the debug interface are blocked. When mass erase is disabled (FSEC[MEEN]= 10), the debugger does not have the capability of performing a mass erase operation via writes to MDM-AP Control Register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 158 Debug and security K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 159: Signal Multiplexing And Signal Descriptions
The following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. The Port Control Module is responsible for selecting which ALT function is available on each pin. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 160 PTE6/ DISABLED PTE6/ LPSPI1_PCS2 USB_SOF_ LLWU_P16 LLWU_P16 USB0_DP USB0_DP USB0_DP USB0_DM USB0_DM USB0_DM VOUT33 VOUT33 VOUT33 VREGIN VREGIN VREGIN — PTE16 ADC0_DP1/ ADC0_DP1/ PTE16 LPSPI0_PCS0 LPUART2_TX TPM0_CLKIN LPSPI1_PCS3 FXIO0_D0 ADC0_SE1 ADC0_SE1 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 161 TPM0_CH0 LPUART0_ SWD_DIO RTS_b PTA4/ NMI0_b TSI0_CH5 PTA4/ LPI2C1_SDA TPM0_CH1 NMI0_b LLWU_P3 LLWU_P3 PTA5 DISABLED PTA5 USB_CLKIN TPM0_CH2 LPI2C2_HREQ — PTA6 DISABLED PTA6 TPM0_CH3 — PTA7 DISABLED PTA7 LPSPI0_PCS3 TPM0_CH4 LPI2C2_SDAS K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 162 ADC0_SE14/ PTC0 LPSPI2_PCS1 USB_SOF_ CMP0_OUT TSI0_CH13 TSI0_CH13 PTC1/ ADC0_SE15/ ADC0_SE15/ PTC1/ LPI2C1_SCL LPUART1_ TPM0_CH0 LLWU_P6 TSI0_CH14 TSI0_CH14 LLWU_P6 RTS_b PTC2 ADC0_SE11/ ADC0_SE11/ PTC2 LPI2C1_SDA LPUART1_ TPM0_CH1 CMP1_IN0/ CMP1_IN0/ CTS_b TSI0_CH15 TSI0_CH15 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 163 TPM0_CH4 LPUART0_ FXIO0_D4 LLWU_P14 LLWU_P14 RTS_b PTD5 ADC0_SE6b ADC0_SE6b PTD5 LPSPI1_SCK LPUART2_TX TPM0_CH5 LPUART0_ FXIO0_D5 CTS_b PTD6/ ADC0_SE7b ADC0_SE7b PTD6/ LPSPI1_SOUT LPUART0_RX FXIO0_D6 LLWU_P15 LLWU_P15 PTD7 DISABLED PTD7 LPSPI1_SIN LPUART0_TX FXIO0_D7 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 164: K32 L2A Pinouts
The below figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous section. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 165 PTB17 PTE16 PTB16 PTE17/LLWU_P19 PTB11 PTB10 PTE18/LLWU_P20 PTB9 PTE19 PTB8 PTE20 PTB7 PTE21 PTB3 PTE22 PTB2 PTE23 PTB1 VDDA PTB0/LLWU_P5 VREFH/VREF_OUT PTA20 VREFL PTA19 VSSA Figure 10-1. 100 LQFP Pinout Diagram K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 166: Module Signal Description Tables
VOUT33 PTB19 VREGIN PTB18 PTE20 PTB17 PTE21 PTB16 PTE22 PTB3 PTE23 PTB2 VDDA PTB1 VREFH/VREF_OUT PTB0/LLWU_P5 VREFL PTA20 VSSA PTA19 Figure 10-2. 64 LQFP Pinout Diagram 10.3 Module Signal Description Tables K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 167: Core Modules
MCU ground 10.3.3 Clock modules Table 10-3. OSC signal descriptions Chip signal name Module signal Description name EXTAL0 EXTAL External clock/Oscillator input XTAL0 XTAL Oscillator output 10.3.4 Memories and memory interfaces K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 168: Analog
TPM0_CLKIN TPM_EXTCLK External clock. TPM external clock can be selected to increment the TPM counter on every rising edge synchronized to the counter clock. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 169 LPTMR0_ALTn Pulse Counter Input pin LPTMR1_ALT[3:1] LPTMR1_ALTn Pulse Counter Input pin Table 10-11. RTC signal descriptions Chip signal name Module signal Description name RTC_CLKOUT RTC_CLKOUT 1 Hz square-wave output or OSC32KCLK K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 170: Communication Interfaces
LPSPI1_SIN SIN / DATA[1] Serial Data Input. Can be configured as serial data output signal. Used as data pin 1 in quad-data and dual-data transfers. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 171 Secondary I2C clock line. In 4-wire mode, this is the SCL output pin. If LPI2C master/slave are configured to use separate pins, then this is the LPI2C slave SCL pin. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 172 LPI2C slave SDA pin. Table 10-20. LPUART0 signal descriptions Chip signal name Module signal Description name LPUART0_TX Transmit data LPUART0_RX Receive data LPUART0_ CTS_b LPUART_CTS Clear to send. LPUART0_ RTS_b LPUART_RTS Request to send. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 173: Human-Machine Interfaces (Hmi)
Table 10-24. TSI Signal Descriptions Chip signal name Module signal Description name TSI0_CH[15:0] TSI[15:0] TSI capacitive pins. Switches driver that connects directly to the electrode pins TSI[15:0] can operate as GPIO pins. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 174 Module Signal Description Tables K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 175: Analog-To-Digital Converter (Adc)
• differential 16-bit, 13-bit, 11-bit, and 9-bit modes • single-ended 16-bit, 12-bit, 10-bit, and 8-bit modes • Output format in 2's complement 16-bit sign extended for differential modes • Output in right-justified unsigned format for single-ended K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 176: Block Diagram
• Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 11.1.2 Block diagram The following figure is the ADC module block diagram. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 177: Adc Signal Descriptions
The ADC module supports up to 4 pairs of differential inputs and up to 24 single-ended inputs. Each differential pair requires two inputs, DADPx and DADMx. The ADC also requires four supply/reference/ground connections. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 178: Analog Power (Vdda)
, and a ground reference that must be at the same potential as . The two pairs are external (V and V ) and alternate (V and V REFH REFL ALTH ALTL These voltage references are selected using SC2[REFSEL]. The alternate V ALTH K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 179: Analog Channel Inputs (Adx)
11.3.1/180 4006_6008 ADC Configuration Register 1 (ADC0_CFG1) 0000_0000h 11.3.2/184 4006_600C ADC Configuration Register 2 (ADC0_CFG2) 0000_0000h 11.3.3/185 4006_6010 ADC Data Result Register (ADC0_RA) 0000_0000h 11.3.4/186 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 180: Adc Status And Control Registers 1 (Adcx_Sc1N)
(ADC0_CLM1) ADC Minus-Side General Calibration Value Register 4006_606C 0000_0020h 11.3.24/201 (ADC0_CLM0) 11.3.1 ADC Status and Control Registers 1 (ADCx_SC1n) SC1A is used for both software and hardware trigger modes of operation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 181 SC1B–SC1n registers do not initiate a new conversion. Address: 4006_6000h base + 0h offset + (4d × i), where i=0d to 1d Reset AIEN DIFF ADCH Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 182 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 183 Voltage reference selected is determined by SC2[REFSEL]. 11110 When DIFF=0,V is selected as input; when DIFF=1, it is reserved. Voltage reference REFSL selected is determined by SC2[REFSEL]. 11111 Module is disabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 184: Adc Configuration Register 1 (Adcx_Cfg1)
When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample time. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 185: Adc Configuration Register 2 (Adcx_Cfg2)
Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: 4006_6000h base + Ch offset = 4006_600Ch Reset ADLSTS Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 186: Adc Data Result Register (Adcx_Rn)
The data result registers (Rn) contain the result of an ADC conversion of the channel selected by the corresponding status and channel control register (SC1A:SC1n). For every status and channel control register, there is a corresponding data result register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 187 Address: 4006_6000h base + 10h offset + (4d × i), where i=0d to 1d Reset ADCx_Rn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Data result K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 188: Compare Value Registers (Adcx_Cvn)
Address: 4006_6000h base + 18h offset + (4d × i), where i=0d to 1d Reset ADCx_CVn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compare Value. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 189: Status And Control Register 2 (Adcx_Sc2)
Conversion not in progress. Conversion in progress. Conversion Trigger Select ADTRG Selects the type of trigger used for initiating a conversion. Two types of trigger are selectable: Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 190 . This pair may be additional external pins or ALTH ALTL internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU Reserved Reserved K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 191: Status And Control Register 3 (Adcx_Sc3)
ADC register is written, or any stop mode is entered before the calibration sequence completes. Writing 1 to CALF clears it. Calibration completed normally. Calibration failed. ADC accuracy specifications are not guaranteed. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 192: Adc Offset Correction Register (Adcx_Ofs)
For more information regarding the calibration procedure, please refer to the Calibration function section. Address: 4006_6000h base + 28h offset = 4006_6028h Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 193: Adc Plus-Side Gain Register (Adcx_Pg)
MG[15] and MG[14]. This register must be written by the user with the value described in the calibration procedure. Otherwise, the gain error specifications may not be met. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 194: Adc Plus-Side General Calibration Value Register (Adcx_Clpd)
Address: 4006_6000h base + 34h offset = 4006_6034h CLPD Reset ADCx_CLPD field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLPD Calibration Value Calibration Value K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 195: Adc Plus-Side General Calibration Value Register (Adcx_Clps)
Address: 4006_6000h base + 3Ch offset = 4006_603Ch CLP4 Reset ADCx_CLP4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP4 Calibration Value Calibration Value K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 196: Adc Plus-Side General Calibration Value Register (Adcx_Clp3)
Address: 4006_6000h base + 44h offset = 4006_6044h CLP2 Reset ADCx_CLP2 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP2 Calibration Value Calibration Value K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 197: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Address: 4006_6000h base + 4Ch offset = 4006_604Ch CLP0 Reset ADCx_CLP0 field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP0 Calibration Value Calibration Value K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 198: Adc Minus-Side General Calibration Value Register (Adcx_Clmd)
This read-only field is reserved and always has the value 0. CLMD Calibration Value Calibration Value 11.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS) For more information, see CLMD register description. Address: 4006_6000h base + 58h offset = 4006_6058h CLMS Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 199: Adc Minus-Side General Calibration Value Register (Adcx_Clm4)
Address: 4006_6000h base + 60h offset = 4006_6060h CLM3 Reset ADCx_CLM3 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 200: Adc Minus-Side General Calibration Value Register (Adcx_Clm2)
Address: 4006_6000h base + 68h offset = 4006_6068h CLM1 Reset ADCx_CLM1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLM1 Calibration Value Calibration Value K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 201: Adc Minus-Side General Calibration Value Register (Adcx_Clm0)
The ADC module has the capability of automatically comparing the result of a conversion with the contents of the CV1 and CV2 registers. The compare function is enabled by setting SC2[ACFE] and operates in any of the conversion modes and configurations. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 202: Clock Select And Divide Control
If the available clocks are too fast, the clock must be divided to the appropriate frequency. This divider is specified by CFG1[ADIV] and can be divide-by 1, 2, 4, or 8. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 203: Voltage Reference Selection
ADHWT signal to trigger a new conversion. The channel and status fields selected for the conversion depend on the active trigger select signal: • ADHWTSA active selects SC1A. • ADHWTSn active selects SC1n. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 204: Conversion Control
SC2[ADTRG]=1, and a hardware trigger select event, ADHWTSn, has occurred. The channel and status fields selected depend on the active trigger select signal: • ADHWTSA active selects SC1A. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 205 SC1n[COCO] sets only if the last of the selected number of conversions is completed and the compare condition is true. An interrupt is generated if the respective SC1n[AIEN] is high at the time that the respective SC1n[COCO] is set. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 206 CFG2[ADACKEN]=1, it remains active regardless of the state of the ADC or the MCU power mode. Power consumption when the ADC is active can be reduced by setting CFG1[ADLPC]. This results in a lower maximum value for f ADCK K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 207 2. When sampling is completed, the converter is isolated from the input channel and a successive approximation algorithm is applied to determine the digital value of the analog signal. 3. The result of the conversion is transferred to Rn upon completion of the conversion algorithm. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 208 9b differential 27 ADCK cycles 10b single-ended 20 ADCK cycles 11b differential 30 ADCK cycles 12b single-ended 20 ADCK cycles 13b differential 30 ADCK cycles Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 209 • 10-bit mode, with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 8 MHz • Long sample time disabled • High-speed conversion disabled K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 210 Equation 1 on page 208. Table 11-9. Typical conversion time Variable Time SFCAdder 3 ADCK cycles + 5 bus clock cycles AverageNum 34 ADCK cycles LSTAdder 20 ADCK cycles HSCAdder K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 211 After the selected input is sampled and converted, the result is placed in an accumulator from which an average is calculated once the selected number of conversions have been completed. When hardware averaging is selected, the completion of a single conversion will not set SC1n[COCO]. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 212: Automatic Compare Function
CV1 And the result is less than or equal to CV2. Greater than Outside range, inclusive Compare true if the result is greater than or equal to CV1 Or the result is less than or equal to CV2. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 213: Calibration Function
Prior to calibration, the user must configure the ADC's clock source and frequency, low power configuration, voltage reference selection, sample time, and high speed configuration according to the application's clock source availability and needs. If the K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 214 7. Repeat the procedure for the minus-side gain calibration value. When calibration is complete, the user may reconfigure and use the ADC as desired. A second calibration may also be performed, if desired, by clearing and again setting SC3[CAL]. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 215: User-Defined Offset Function
ADC error specifications may not be met. Storing the value generated by the calibration function in memory before overwriting with a user- specified value is recommended. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 216: Temperature Sensor
• m is referred as temperature sensor slope in the device data sheet. It is the hot or cold voltage versus temperature slope in V/°C. For temperature calculations, use the V and temperature sensor slope values from TEMP25 the ADC Electricals table. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 217: Mcu Wait Mode Operation
11.4.10 MCU Normal Stop mode operation Stop mode is a low-power consumption Standby mode during which most or all clock sources on the MCU are disabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 218: Initialization Information
16-bit, 13-bit, 11-bit, or 9-bit differential resolution, single or continuous conversion, and a polled or interrupt approach, among many other options. For information used in this example, refer to Table 11-6, Table 11-7, and Table 11-8. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 219: Adc Module Initialization Example
Sets the ADCK to the input clock ÷ 1. Bit 4 ADLSMP Configures for long sample time. Bit 3:2 MODE Selects the single-ended 10-bit conversion, differential 11- bit conversion. Bit 1:0 ADICLK Selects the bus clock. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 220 Holds compare value when compare function enabled. Reset Initialize ADC CFG1 = 0x98 SC2 = 0x00 SC1n = 0x41 Check SC1n[COCO]=1? Read Rn to clear SC1n[COCO] Continue Figure 11-2. Initialization flowchart example K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 221: Application Information
. Each pair contains a positive reference and a ground reference. The two pairs are REFSL external, V and V and alternate, V and V . These voltage references are REFH REFL ALTH ALTL K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 222 0x000. Input voltages between V and V REFH REFL straight-line linear conversions. There is a brief current associated with V when the REFL sampling capacitor is charging. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 223: Sources Of Error
× 2 ) for less than 1/4 LSB leakage error, where N = 8 in REFH LEAK 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode, or 16 in 16-bit mode. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 224 1 LSB, one-time error. • Reduce the effect of synchronous noise by operating off the asynchronous clock, that is, ADACK, and averaging. Noise that is synchronous to ADCK cannot be averaged out. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 225 0x3FE code width and its ideal (1 LSB) is used. • Differential non-linearity (DNL): This error is defined as the worst-case difference between the actual code width and the ideal code width for all conversions. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 226 • Missing codes: Missing codes are those values never converted for any input value. In 8-bit or 10-bit mode, the ADC is guaranteed to be monotonic and have no missing codes. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 227: Crossbar Switch Lite (Axbs-Lite)
• Symmetric crossbar bus switch implementation • Allows concurrent accesses from different masters to different slaves • Up to single-clock 32-bit transfer • Programmable configuration for fixed-priority or round-robin slave port arbitration (see the chip-specific information). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 228: Memory Map / Register Definition
This is done to save the initial clock of arbitration delay that otherwise would be seen if the same master had to arbitrate to gain control of the slave port. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 229: Bit Manipulation Engine2 (Bme2)
BME decorated references are only available on system bus transactions generated by the processor core and DMA, and targeted at the 1024 KB peripheral address space based at 0x4000_0000. The decoration semantic is embedded into address bits[28:20], creating a K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 230: Features
13.2 Memory map and register definition The BME module provides a memory-mapped capability and does not include any programming model registers. The exact set of functions supported by the BME are detailed in the Functional description. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 231: Functional Description
AHB data phase, and then the write is performed in the second AHB data phase. A generic timing diagram of a decorated store showing a peripheral bit field insert operation is shown as follows: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 232 NOTE Any wait states inserted by the slave device are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 233 Table 13-1. Cycle definitions of decorated store: logical AND Pipeline stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 234 & 0xE00FFFFF, size] // memory read tmp | wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write The cycle-by-cycle BME operations are detailed in the following table. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 235 & 0xE00FFFFF, size] // memory read tmp ^ wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write The cycle-by-cycle BME operations are detailed in the following table. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 236 "b", the LSB identifier, addr[22:20] is "w", the bit field width minus 1 identifier, and addr[19:0] specifies the address offset into the peripheral space based at 0x4000_0000. The "-" indicates an address bit "don't care". K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 237 Capture address, attributes BME AHB_dp <previous> Perform memory read; Form Perform write sending bit mask; Form bitwise registered data to memory ((mask) ? wdata : rdata)) and capture destination data in register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 238: Bme Decorated Loads
AHB data phase. This is the only decorated transaction that is not an atomic read-modify-write, as it is a simple data read. A generic timing diagram of a decorated load showing a peripheral load-and-set 1-bit operation is shown as follows. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 239 4. Cycle x+2, second AHB data phase: The selected original 1-bit is right-justified, zero-filled and then driven onto the input read data bus, while the registered write data is sourced onto the output write data bus K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 240 • Cycle x, 1st AHB address phase: Read from input bus is translated into a read operation on the output bus with the actual memory address (with the decoration removed) and then captured in a register • Cycle x+1, 2nd AHB address phase: Idle cycle K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 241 // decorated load-and-clear 1 mem[accessAddress & 0xE00FFFFF, size] // memory read mask 1 << b // generate bit mask rdata = (tmp & mask) >> b // read data returned to core K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 242 0x2000_0000 for SRAM_U, and 0x4000_0000 for peripherals. The "-" indicates an address bit "don't care". The decorated Load-and-Set 1 Bit read operation is defined in the following pseudo-code K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 243 0, indicating a bit field width of 1. ioubfxb 0 mem_addr ioubfxh 0 mem_addr ioubfxw 0 mem_addr Figure 13-10. Decorated load address: unsigned bit field extract K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 244: Application Information
BFI and the decorated loads are more complex and available in the complete BME header file. These macros use the same function names presented in Functional description. #define IOANDW(ADDR,WDATA) __asm("ldr r3, =(1<<26);" "orr r3, %[addr];" K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 245 :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORB(ADDR,WDATA) __asm("ldr r3, =(3<<26);" "orr r3, %[addr];" "mov r2, %[wdata];" "strb r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 246 Application information K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 247: Kinetis Rom Bootloader
PTC4, LPUART1_TX PTD2, LPUART2_RX PTD3, LPUART2_TX PTE24, I2C0_SCL PTE25, I2C0_SDA PTE1, I2C1_SCL PTE0, I2C1_SDA PTA14, SPI0_PCS0 PTA15, SPI0_SCK PTA16, SPI0_MOSI PTA17, SPI0_MISO PTD4, SPI1_PCS0 PTD5, SPI1_SCK Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 248: Bootloader Memory Access
PC or an embedded host communicating with the Kinetis Bootloader. Regardless of the host/master (PC or embedded host), the Kinetis Bootloader always uses a command protocol to communicate with that host/master. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 249 Not supported FlashEraseRegion Erase a range of sectors in flash Not supported WriteMemory Write data to memory Not supported ReadMemory Read data from memory Not supported Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 250: Functional Description
Erase the entire flash array, including protected Supported sectors 14.3 Functional Description The following sub-sections describe the Kinetis Bootloader in ROM functionality. 14.3.1 Memory Maps While executing, the Kinetis Bootloader uses ROM and RAM memory. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 251: The Kinetis Bootloader Configuration Area (Bca)
CRC check. If the bits are all set then Kinetis bootloader by default will not perform any CRC check. 0x10 enabledPeripherals Bitfield of peripherals to enable. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 252 0x30 - 0x33 Reserved 0x34 - 0x3F Reserved NOTE The flash sector containing the BCA should not be located in the execute-only region, because the Kinetis bootloader cannot read an execute-only region. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 253: Start-Up Process
Regardless of whether the NMI pin is enabled or not, the NMI functionality is disabled if the ROM is executed out of reset, for as long as the ROM is running. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 254 NOTE The flash sector containing the vector table should not be located in the execute-only region, because the Kinetis bootloader cannot read the PC and SP addresses in an execute-only region. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 255 ROM? activity direct boot detected on USB? valid? Is user application valid? Enable Timeout Check and enable Timeout value Disable Timeout detection Figure 14-2. Kinetis Bootloader Start-up Flowchart K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 256: Clock Configuration
//!< Bootloader version number. const char *copyright; //!< Copyright string. const bootloader_context_t *runtimeContext; //!< Pointer to the bootloader's runtime context. const flash_driver_interface_t *flashDriver; //!< Flash driver API. const aes_driver_interface_t *aesDriver; //!< AES driver API. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 257: Bootloader Protocol
The next section describes various packet types used in a transaction. Each command sent from the host is replied to with a response command. Commands may include an optional data phase: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 258 The protocol for a command with an incoming data phase contains: • Command packet (from host) • Generic response command packet (to host) • Incoming data packets (from host) • Generic response command packet (to host) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 259 • Data phases may be aborted by the receiving side by sending the final Generic Response early with a status of K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 260 The protocol for a command with an outgoing data phase contains: • Command packet (from host) • ReadMemory Response command packet (to host) (kCommandFlag_HasDataPhase set) • Outgoing data packets (to host) • Generic response command packet (to host) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 261 • If the ReadMemory Response command packet prior to the start of the data phase does not contain the kCommandFlag_HasDataPhase flag, then the data phase is aborted. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 262: Bootloader Packet Types
A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 14-6. Ping Packet Format Byte # Value Name 0x5A start byte 0xA6 ping K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 263 Table 14-7. Ping Response Packet Format Byte # Value Parameter 0x5A start byte 0xA7 Ping response code Protocol bugfix Protocol minor Protocol major Protocol name = 'P' (0x50) Options low Options high CRC16 low CRC16 high K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 264 Data phase is being aborted. 0xA4 kFramingPacketType_Command The framing packet contains a command packet payload. 0xA5 kFramingPacketType_Data The framing packet contains a data packet payload. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 265 ^= byte << 8; for (i = 0; i < 8; ++i) uint32_t temp = crc << 1; if (crc & 0x8000) temp ^= 0x1021; crc = temp; return crc; K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 266 FlashEraseAll 0x02 FlashEraseRegion 0x03 ReadMemory 0x04 WriteMemory 0x05 FillMemory 0x06 FlashSecurityDisable 0x07 GetProperty 0x08 ReceiveSBFile 0x09 Execute 0x0A Call 0x0B Reset 0x0C SetProperty 0x0D FlashEraseAllUnsecure Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 267 The contents of a data packet are simply the data itself. There are no other fields, so that the most data per packet can be transferred. Framing packets are responsible for ensuring that the correct packet data is received. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 268 Table 14-16. GetPropertyResponse Parameters Byte # Value Parameter 0 - 3 Status code 4 - 7 Property value Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 269 Table 14-18. FlashReadOnceResponse Parameters Byte # Value Parameter 0 – 3 Status Code 4 – 7 Byte count to read … … Can be up to 20 bytes of requested read data. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 270: Bootloader Command Api
Although the command supports a stack address, at this time the call will still take place using the current stack pointer. After execution of the function, a 32-bit return value will be returned in the generic response message. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 271 Data Phase: The Receive SB file command has a data phase; the host will send data packets until the number of bytes of data specified in the byteCount parameter of the Receive SB File command are received by the target. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 272 GenericResponse packet with a status code either set to kStatus_Success or an appropriate error status code. 14.3.8.4 Reset command The Reset command will result in bootloader resetting the chip. The Reset command requires no parameters. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 273 Each supported property has a unique 32-bit tag associated with it. The tag occupies the first parameter of the command packet. The target returns a GetPropertyResponse packet with the property values for the property identified with the tag in the GetProperty command. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 274 Value Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x08 0x00 crc16 0x73 0xD4 Command packet commandTag 0x07 – GetProperty flags 0x00 reserved 0x00 parameterCount 0x01 propertyTag 0x00000001 - CurrentVersion K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 275 The property tag and the new value to set are the 2 parameters required for the SetProperty command. Table 14-27. Parameters for SetProperty Command Byte # Command 0 - 3 Property tag 4 - 7 Property value K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 276 The SetProperty command has no data phase. Response: The target (Kinetis Bootloader) will return a GenericResponse packet with one of following status codes: Table 14-29. SetProperty Response Status Codes Status Code kStatus_Success kStatus_ReadOnly kStatus_UnknownProperty kStatus_InvalidArgument K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 277 0xC4 0x2E Command packet commandTag 0x01 - FlashEraseAll flags 0x00 reserved 0x00 parameterCount 0x00 MemoryID • If MemoryID = 0x00h, then internal flash. • If MemoryID = 0x01h, then QSPI0 memory. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 278 Command Generic Response 0x5A A4 0C 00 BA 55 A0 00 00 02 00 00 00 00 02 00 00 00 ACK: 0x5A A1 Figure 14-12. Protocol Sequence for FlashEraseRegion Command K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 279 FSEC byte in the flash configuration field at address 0x40C is programmed to 0xFE. However, if the mass erase enable option in the FSEC field is disabled, then the FlashEraseAllUnsecure command will fail. The FlashEraseAllUnsecure command requires no parameters. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 280 The FlashProgramOnce command writes data (that is provided in a command packet) to a specified range of bytes in the program once field. Special care must be taken when writing to the program once field. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 281 Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x10 0x00 crc16 0x7E4 0x89 Command packet commandTag 0x0E – FlashProgramOnce flags reserved parameterCount index 0x0000_0000 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 282 0x5A A4 10 00 3F 6F AF 00 00 03 00 00 00 00 04 00 00 00 78 56 34 12 ACK: 0x5A A1 Figure 14-15. Protocol Sequence for FlashReadOnce Command K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 283 The FlashReadResource command returns the contents of the IFR field or Flash Version ID, by given offset, byte count, and option. The FlashReadResource command uses 3 parameters: start address, byteCount, option. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 284 Table 14-41. FlashReadResource Command Packet Format (Example) FlashReadResource Parameter Value Framing packet start byte 0x5A packetType 0xA4 length 0x10 0x00 0xB3 0xCC Command packet commandTag 0x10 – FlashReadResource flags 0x00 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 285 The backdoor low and high words are the only parameters required for FlashSecurityDisable command. Table 14-43. Parameters for FlashSecurityDisable Command Byte # Command 0 - 3 Backdoor key low word Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 286 0x43 0x7B Command packet commandTag 0x06 - FlashSecurityDisable flags 0x00 reserved 0x00 parameterCount 0x02 Backdoorkey_low 0x04 0x03 0x02 0x01 Backdoorkey_high 0x08 0x07 0x06 0x05 The FlashSecurityDisable command has no data phase. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 287 • If the VerifyWrites property is set to true, then writes to flash will also perform a flash verify program operation. When writing to RAM, the start address need not be aligned, and the data will not be padded. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 288 The WriteMemory command writes data provided in the data phase to a specified range of bytes in memory (flash or RAM). However, if flash protection is enabled, then writes to protected sectors will fail. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 289 The start address and number of bytes are the 2 parameters required for WriteMemory command. Table 14-47. Parameters for WriteMemory Command Byte # Command 0 - 3 Start address 4 - 7 Byte count K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 290 Value Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x06 0x5A Command packet commandTag 0x04 - writeMemory flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x20000400 byteCount 0x00000064 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 291 The start address and number of bytes are the 2 parameters required for ReadMemory command. Table 14-49. Parameters for ReadMemory command Byte Parameter Description Start address Start address of memory to read from Byte count Number of bytes to read and return to caller K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 292 Value Framing packet Start byte 0x5A 0xA4 packetType kFramingPacketType_Command length 0x0C 0x00 crc16 0x1D 0x23 Command packet commandTag 0x03 - readMemory flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x20000400 byteCount 0x00000064 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 293: Bootloader Exit State
• If high speed clocking is selected in the Bootloader Configuration Area, then high speed clocks will be retained after exiting from the bootloader. • Upon exit from the bootloader, the bootloader restores the VTOR register to its default value (0x0). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 294: Peripherals Supported
• 0x00 will be sent as the response to host if the target is busy with processing or preparing data. The following flow charts demonstrate the communication flow of how the host reads ping packet, ACK and response from the target. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 295 Process NAK received? from target Reached 0x5A Read 1 byte 0xA1 maximum received? from target received? retries? Report a timeout error Figure 14-22. Host reads ACK packet from target via LPI2C K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 296: Lpspi Peripheral
• Received bytes should be ignored when host is sending out bytes to target • Host starts reading bytes by sending 0x00s to target • The byte 0x00 will be sent as response to host if target is under the following conditions: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 297 1 byte of ping response from target Send 0x00 to 0x5A 0xA7 Report Error shift out 1 byte received? received? from target Figure 14-24. Host reads ping packet from target via LPSPI K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 298 Report a timeout out payload length 0xA4 out CRC checksum received? part from target from target error (End) (2 bytes) (2 bytes) Figure 14-26. Host reads response from target via LPSPI K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 299: Quadspi Peripheral
1 DQS loopback is enabled, the DQS loopback mode is determined by subsequent ‘dqs_loopback_internal’ field 0x24 – 0x27 write_cmd_ipcr IPCR pointed to LUT index for quad mode enablement Value = index << 24 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 300 1 Dual mode 2 Quad mode 3 Octal mode 0x50 – 0x53 sflash_port Port enablement for QuadSPI module 0 Only pins for QSPI0A are enabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 301 Enable additional configuration command 0 Additional configuration command is not needed 1 Additional configuration command is needed 0x17c – 0x18b config_cmds IPCR arrays for each connected SPI flash Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 302 Sector size of external SPI flash. Sector size of all SPI flash devices must be the same. 0x1cc - 0x1cf timeout_milliseconds Timeout in terms of milliseconds. 0 Timeout check is disabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 303 5 can be used for enabling the Quad mode of SPI flash devices. 1. If these LUT entries are are not required, then these LUT entries can be used for other purposes. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 304 BCA to 0x3c0. 4. Update BOOTSRC_SEL field (bits [7:6]) in FOPTregister at the address 0x40D to “0b’10”, which means "boot from ROM with QuadSPI configured". 5. Reset the target. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 305 MCGFLL clock is selected as the clock source for QuadSPI module 14.4.3.4 Access external SPI flash devices using QuadSPI module The Kinetis Bootloader supports access to external SPI flash devices using the following commands: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 306 “0’b10”, which means "boot from ROM with QuadSPI configured". • User application is valid. • QuadSPI configuration block (QCB) is valid • CRC check passed if the CRC check feature is enabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 307: Lpuart Peripheral
• How the host detects an ACK from the target • How the host detects a ping response from the target • How the host detects a command response from the target K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 308 Wait for 1 byte of ping response from target packet 0x5A 0xA7 Wait for 1 byte Report Error received? received? from target Figure 14-28. Host reads a ping response from target via LPUART K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 309: Usb Peripheral
ROM enables the 48-MHz . The ROM also enables the USB clock recovery feature (by setting USBx_CLK_RECOVER_CTRL[CLOCK_RECOVER_EN] to 1 ). 14.4.5.2 Device descriptor The Kinetis ROM configures the default USB VID/PID/Strings as below: Default VID/PID: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 310 • PID = 0x0073 Default Strings: • Manufacturer [1] = "Freescale Semiconductor Inc." (Note that Freescale Semiconductor is now NXP Semiconductors.) • Product [2] = "Kinetis Bootloader" You can customize the USB VID/PID/Strings with the Bootloader Configuration Area (BCA) of the flash. See Table 14-3.
Page 311 'E',0, 'V',0, 'I',0, 'C',0, 'E',0 USB_STR_3[] = sizeof(USB_STR_3), USB_STRING_DESCRIPTOR, 'M',0, 'C',0, 'U',0, ' ',0, 'H',0, 'I',0, 'D',0, ' ',0, 'G',0, 'E',0, 'N',0, 'E',0, 'R',0, 'I',0, 'C',0, ' ',0, 'D',0, 'E',0, 'V',0, K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 312 Each report has a maximum size of 34 bytes. This is derived from the minimum bootloader packet size of 32 bytes, plus a 2-byte report header that indicates the length (in bytes) of the packet sent in the report. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 313: Get/Setproperty Command Properties
The set of commands supported by the bootloader. VerifyWrites Controls whether the bootloader will verify writes to flash. VerifyWrites feature is enabled by default. 0 - No verification is done. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 314 FlashReadMargin The margin level setting for flash erase and program verify commands. 0 = Normal 1 = User (default) 2 = Factory TargetVersion SoC target build version number K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 315: Property Definitions
1. 1 is subtracted from the command tag because the lowest command tag value is 0x01. To get the bit mask for a given command, use this expression: mask = 1 << (tag - 1) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 316: Sb File Decryption Support
• FlashProgramOnce to index 0x30 with 4 bytes of 0x03020100 • FlashProgramOnce to index 0x31 with 4 bytes of 0x07060504 • FlashProgramOnce to index 0x32 with 4 bytes of 0x0B0A0908 • FlashProgramOnce to index 0x33 with 4 bytes of 0x0F0E0D0C K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 317: Decryption Using Mmcau
K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 318: Verifying The Application In Flash Using Crc-32
• If the given address range of the application is valid (true), then the CRC check is performed. The CRC32 algorithm in ROM uses a polynomial (0x04C1_1DB7), and the initial seed is 0xFFFF_FFFF. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 319: Kinetis Bootloader Status Error Codes
The key provided does not match the programmed flash key. kStatus_FlashRegionExecuteOnly The area of flash is protected as execute only. kStatus_I2C_SlaveTxUnderrun I2C Slave TX Underrun error. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 320 The specified property value is invalid. kStatus_AppCrcCheckPassed 10400 CRC check is valid and passed. kStatus_AppCrcCheckFailed 10401 CRC check is valid but failed. kStatus_AppCrcCheckInactive 10402 CRC check is inactive. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 321 10403 CRC check is invalid, because the BCA is invalid or the CRC parameters are unset (all 0xFF bytes). kStatus_AppCrcCheckOutOfRange 10404 CRC check is valid but addresses are out of range. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 322 Kinetis Bootloader Status Error Codes K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 323: Cryptographic Acceleration Unit (Cau)
NXP provides an optimized C-function library that provides the appropriate software building blocks to implement higher-level security functions. 15.2 CAU Block Diagram A simplified block diagram is given below that illustrates the CAU and a table to show its parts. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 324 CAU 3-terminal block with a command and optional input operand and a result bus. More details in following figure. The following figure shows the CAU block in more detail. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 325: Overview
The cryptographic algorithms are implemented partially in software with only functions critical to increasing performance implemented in hardware. The CAU allows for efficient, fine-grained partitioning of functions between hardware and software: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 326: Features
SHA-256 CAU Status — — — — — Register (CASR) — — Accumulator (CAA) General- — Purpose Register 0 (CA0) General- Purpose Register 1 (CA1) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 327 CAU memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F000_5000 Status Register (CAU0_CASR) 2000_0000h 15.5.1/328 F000_5001 Accumulator (CAU0_CAA) 0000_0000h 15.5.2/329 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 328: Status Register (Caux_Casr)
This read-only field is reserved and always has the value 0. DES Parity Error Indicates whether the DES parity error is detected. No error detected. DES key parity error detected. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 329: Accumulator (Caux_Caa)
Address: F000_5000h base + 2h offset + (1d × i), where i=0d to 8d Reset CAUx_CAn field descriptions Field Description General Purpose Registers Used by the CAU commands. Some cryptographic operations work with specific registers. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 330: Functional Description
• Accesses to the reserved space in the direct load space are terminated with an error, while accesses to the reserved space in the indirect load/store space are detected as an illegal CAU command. See CAU integrity checks details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 331 32-bit PPB write. The following figure illustrates the accepted formats for the 32-bit CAU write data value: 1 command CAU_CMD1 2 commands CAU_CMD1 CAU_CMD2 3 commands CAU_CMD1 CAU_CMD2 CAU_CMD3 Figure 15-4. Direct loads K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 332: Cau Integrity Checks
The results of these checks are logically summed together and, if appropriate, a PPB error termination is generated. 15.6.2.1 Address integrity checks The CAU address checking includes the following. See Figure 15-3 for the CAU memory map details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 333 • Bit 9 is the valid bit for the third command The direct write data check validates the combination of these three valid bits. The following table presents the three legal states associated with these bits: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 334: Cau Commands
AES Inv Sub Bytes 0x0B InvSubBytes(CAx) → CAx Indirect load AESC AES Column Op 0x0C MixColumns(CAx)^Op1→ Indirect load AESIC AES Inv Column Op 0x0D InvMixColumns(CAx^Op1) → Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 335 CAU FIFO, but has no effect on any CAU register. 15.6.3.2 Load Register (LDR) The LDR command loads CAx with the source data specified by the write data. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 336 ROTL rotates the CAx bits to the left with the result stored back to CAx. The number of bits to rotate is the value specified by the write data modulo 32. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 337 CAx. 15.6.3.15 AES Shift Rows (AESR) The AESR command performs the AES shift rows operation on registers CA0, CA1, CA2, and CA3. The table below shows an example. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 338 CA3=R. If the IP bit is set, DES initial permutation performs on CA2 and CA3 before the round operation. If the FP bit is set, DES final permutation, that is, inverse initial permutation, performs on CA2 and CA3 after the round operation. The round operation K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 339 (CA1 & CA3) | (CA2 & CA3) Table continues on the next page... 1. The DES algorithm numbers the most significant bit of a block as bit 1 and the least significant as bit 64. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 340 The MDS command does a set of parallel register-to-register move operations for implementing MD5. The following source and destination assignments are made: Register Value prior to command Value after command executes K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 341: Application/Initialization Information
• FP points to the CAU indirect command address space • IP points to the CAU direct command space movw fp, #:lower16:MMCAU_PPB_INDIRECT @ fp -> MMCAU_PPB_INDIRECT movt fp, #:upper16:MMCAU_PPB_INDIRECT movw ip, #:lower16:MMCAU_PPB_DIRECT @ ip -> MMCAU_PPB_DIRECT movt ip, #:upper16:MMCAU_PPB_DIRECT K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 342: Assembler Equate Values
; key schedule left 2 bits .set KSR1,0x02 ; key schedule right 1 bit .set KSR2,0x03 ; key schedule right 2 bits ; DESK Field .set DC,0x01 ; decrypt key schedule K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 343 ; SHA-256 Maj() CA0&CA1 ^ CA0&CA2 ^ CA1&CA2 .set HF2S,0x8 ; SHA-256 Sigma 0 ROTR2(CA0)^ROTR13(CA0)^ROTR22(CA0) .set HF2T,0x9 ; SHA-256 Sigma 1 ROTR6(CA4)^ROTR11(CA4)^ROTR25(CA4) .set HF2U,0xA ; SHA-256 sigma 0 ROTR7(CA8)^ROTR18(CA8)^SHR3(CA8) .set HF2V,0xB ; SHA-256 sigma 1 ROTR17(CA8)^ROTR19(CA8)^SHR10(CA8) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 344 Application/initialization information K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 345: Comparator (Cmp)
16.1.1 CMP features The CMP has the following features: • Operational over the entire supply range • Inputs may range from rail to rail • Programmable hysteresis control K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 346: 6-Bit Dac Key Features
The 6-bit DAC has the following features: • 6-bit resolution • Selectable supply reference source • Power Down mode to conserve power when not in use • Option to route the output to internal comparator input K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 347: Cmp, Dac And Anmux Diagram
• Two 8-to-1 channel mux • Operational over the entire supply range 16.1.4 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 348: Cmp Block Diagram
Reference Input 6 Window ANMUX and filter control CMPO MSEL[2:0] Figure 16-1. CMP, DAC and ANMUX block diagram 16.1.5 CMP block diagram The following figure shows the block diagram for the CMP module. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 349 CR0[FILTER_CNT] is set greater than 0x01. • If CR1[SE] = 1, the external SAMPLE input is used as sampling clock • If CR1[SE] = 0, the divided bus clock is used as sampling clock K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 350: Memory Map/Register Definitions
CMPx_CR0 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 Filter Sample Count FILTER_CNT Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 351: Cmp Control Register 1 (Cmpx_Cr1)
WE is cleared. However, avoid writing 1s to both field locations because this "11" case is reserved and may change in future implementations. Sampling mode is not selected. Sampling mode is selected. Windowing Enable Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 352 Enables the Analog Comparator module. When the module is not enabled, it remains in the off state, and consumes no power. When the user selects the same input from analog mux to the positive and negative port, the comparator is disabled automatically. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 353: Cmp Filter Period Register (Cmpx_Fpr)
Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is asserted when CFR or CFF is set. DMA is disabled. DMA is enabled. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 354: Dac Control Register (Cmpx_Daccr)
Write Reset CMPx_DACCR field descriptions Field Description DAC Enable DACEN Enables the DAC. When the DAC is disabled, it is powered down to conserve power. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 355: Mux Control Register (Cmpx_Muxcr)
NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 356: Functional Description
SCR[COUT]. 16.3.1 CMP functional modes There are the following main sub-blocks to the CMP module: • The comparator itself • The window function • The filter function K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 357 SAMPLE=1 to generate COUTA, which is then resampled on an interval determined by FILT_PER to generate COUT. See the Windowed/Resampled mode (# > 0x01 0x01–0xFF Windowed/Filtered mode Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 358 16.3.1.1 Disabled mode (# 1) In Disabled mode, the analog comparator is non-functional and consumes no power. CMPO is 0 in this mode. 16.3.1.2 Continuous mode (#s 2A & 2B) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 359 COUT and COUTA are identical. For control configurations which result in disabling the filter block, see the Filter Block Bypass Logic diagram. 16.3.1.3 Sampled, Non-Filtered mode (#s 3A & 3B) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 360 #3B, the clock to filter block is internally derived. The comparator filter has no other function than sample/hold of the comparator output in this mode (# 3B). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 361 COUTA is sampled whenever a rising edge is detected on the filter block clock input. The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Filtered (# 4A) is that, now, CR0[FILTER_CNT]>1, which activates filter operation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 362 CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 16-6. Sampled, Filtered (# 4A): sampling point externally driven K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 363 WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 364 COUTA Clock CMPO to divided prescaler FILT_PER CGMUX clock SE=0 Figure 16-9. Windowed mode For control configurations which result in disabling the filter block, see Filter Block Bypass Logic diagram. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 365 FPR[FILT_PER] and the bus clock rate. Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of CR0[FILTER_CNT] must be 1. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 366: Power Modes
Figure 16-11. Windowed/Filtered mode 16.3.2 Power modes 16.3.2.1 Wait mode operation During Wait and VLPW modes, the CMP, if enabled, continues to operate normally and a CMP interrupt can wake the MCU. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 367: Startup And Operation
The filter delay is specified in the Low-pass filter. • During operation, the propagation delay of the selected data paths must always be considered. It may take many bus clock cycles for COUT and SCR[CFR]/SCR[CFF] K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 368: Low-Pass Filter
In other words, SCR[COUT] will be 0 for some initial period, even when COUTA is at logic 1. Setting both CR1[SE] and FPR[FILT_PER] to 0 disables the filter and eliminates switching current associated with the filtering process. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 369 > 0x01 Sampled, Filtered mode + (CR0[FILTER_CNT] * ) + T SAMPLE > 0x01 > 0x00 + (CR0[FILTER_CNT] * FPR[FILT_PER] x T ) + T Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 370: Cmp Interrupts
DMA transfer request and clears the flag to allow a subsequent change on comparator output to occur and force another DMA request. The comparator can remain functional in STOP modes. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 371: Cmp Asynchronous Dma Support
STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 372: Digital-To-Analog Converter
This section provides DAC functional description information. 16.8.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder • V connects to an alternate voltage source K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 373: Dac Resets
Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received. See the chip configuration chapter for details about the external timer resource. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 374 CMP Trigger Mode K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 375: Cyclic Redundancy Check (Crc)
• Option for inversion of final CRC result • 32-bit CPU register programming interface 17.1.2 Block diagram The following is a block diagram of the CRC. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 376: Modes Of Operation
Register name Access Reset value (in bits) page (hex) 4007_8000 CRC Data register (CRC_DATA) FFFF_FFFFh 17.2.1/377 4007_8004 CRC Polynomial register (CRC_GPOLY) 0000_1021h 17.2.2/378 4007_8008 CRC Control register (CRC_CTRL) 0000_0000h 17.2.3/378 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 377: Crc Data Register (Crc_Data)
CRC Low Lower Byte When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 378: Crc Polynomial Register (Crc_Gpoly)
CRC calculation. A new CRC calculation is initialized by asserting CTRL[WAS] and then writing the seed into the CRC data register. Address: 4007_8000h base + 8h offset = 4007_8008h TOTR FXOR WAS Reset Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 379: Functional Description
Writes to the CRC data register are seed values. Width of CRC protocol. TCRC 16-bit CRC protocol. 32-bit CRC protocol. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 17.3 Functional description K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 380: Crc Calculations
8. When all values have been written, read the final CRC result from CRC_DATA[LU:LL]. Transpose and complement operations are performed on the fly while reading or writing values. See Transpose feature CRC result complement for details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 381: Transpose Feature
CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register: 1. CTRL[TOT] or CTRL[TOTR] is 00. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 382 = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 17-3. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. Bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 383: Crc Result Complement
CRC data register every time the CRC data register is read. When CTRL[FXOR] is cleared, reading the CRC data register accesses the raw checksum value. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 384 Functional description K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 385: 12-Bit Digital-To-Analog Converter (Dac)
• Static operation in Normal Stop mode • 16-word data buffer supported with configurable watermark and multiple operation modes • DMA support 18.3 Block diagram The block diagram of the DAC module is as follows: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 386: Memory Map/Register Definition
DACBFRP & DACBBIEN DACBFMD DACTRGSE Figure 18-1. DAC block diagram 18.4 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 387 4006_A01F DAC Data High Register (DAC0_DAT15H) 18.4.2/388 4006_A020 DAC Status Register (DAC0_SR) 18.4.3/388 4006_A021 DAC Control Register (DAC0_C0) 18.4.4/389 4006_A022 DAC Control Register 1 (DAC0_C1) 18.4.5/391 4006_A023 DAC Control Register 2 (DAC0_C2) 18.4.6/392 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 388: Dac Data Low Register (Dacx_Datnl)
Writing 0 to a field clears it whereas writing 1 has no effect. After reset, DACBFRPTF is set and can be cleared by software, if needed. The flags are set only when the data buffer status is changed. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 389: Dac Control Register (Dacx_C0)
Read DACTRGSE DACEN DACRFS LPEN DACBWIEN DACBTIEN DACBBIEN Write DACSWTRG Reset DACx_C0 field descriptions Field Description DAC Enable DACEN Starts the Programmable Reference Generator operation. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 390 The DAC buffer read pointer top flag interrupt is enabled. DAC Buffer Read Pointer Bottom Flag Interrupt Enable DACBBIEN The DAC buffer read pointer bottom flag interrupt is disabled. The DAC buffer read pointer bottom flag interrupt is enabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 391: Dac Control Register 1 (Dacx_C1)
Buffer read pointer is disabled. The converted data is always the first word of the buffer. Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 392: Dac Control Register 2 (Dacx_C2)
Scan mode. When the buffer operation is switched from one mode to another, the read pointer does not change. The read pointer can be set to any value between 0 and C2[DACBFUP] by writing C2[DACBFRP]. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 393: Dma Operation
When DMA is enabled, DMA requests are generated instead of interrupt requests. The DMA Done signal clears the DMA request. The status register flags are still set and are cleared automatically when the DMA completes. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 394: Resets
In low-power stop modes, the DAC is fully shut down. NOTE The assignment of module modes to core modes is chip- specific. For module-to-core mode assignments, see the chapter that describes how modules are configured. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 395: Direct Memory Access Multiplexer (Dmamux)
19.1.1 Overview The Direct Memory Access Multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 8 DMA channels. This process is illustrated in the following figure. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 396: Features
• Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. 19.1.3 Modes of operation The following operating modes are available: • Disabled mode K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 397: External Signal Description
19.3.1/398 4002_1003 Channel Configuration register (DMAMUX0_CHCFG3) 19.3.1/398 4002_1004 Channel Configuration register (DMAMUX0_CHCFG4) 19.3.1/398 4002_1005 Channel Configuration register (DMAMUX0_CHCFG5) 19.3.1/398 4002_1006 Channel Configuration register (DMAMUX0_CHCFG6) 19.3.1/398 4002_1007 Channel Configuration register (DMAMUX0_CHCFG7) 19.3.1/398 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 398: Channel Configuration Register (Dmamuxx_Chcfgn)
DMAMUX information for details about the peripherals and their slot numbers. 19.4 Functional description The primary purpose of the DMAMUX is to provide flexibility in the system's use of the available DMA channels. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 399: Dma Channels With Periodic Triggering Capability
Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 400 This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 401: Dma Channels With No Triggering Capability
19.4.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 402: Always-Enabled Dma Sources
DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use an always-enabled DMA source. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 403: Initialization/Application Information
DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability: 1. Write 0x00 to CHCFG1. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 404 *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0009); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x0008); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 405 *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 406 Initialization/application information In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 407: Enhanced Direct Memory Access (Edma)
• Local memory containing transfer control descriptors for each of the 8 channels 20.1.1 eDMA system block diagram Figure 20-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 408: Block Parts
After the minor loop completes execution, the address path hardware writes Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 409: Features
The eDMA module features: • All data movement via dual-address transfers: read from source, write to destination • Programmable source and destination addresses and transfer size • Support for enhanced addressing modes K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 410: Modes Of Operation
In Normal mode, the eDMA transfers data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 411: Memory Map/Register Definition
0, channel 1, ... channel 7. Each TCDn definition is presented as 11 registers of 16 or 32 bits. 20.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 412: Tcd Structure
Enable Error Interrupt Register (DMA0_EEI) 0000_0000h 20.3.8/425 4000_8018 Clear Enable Error Interrupt Register (DMA0_CEEI) (always 20.3.9/426 reads 0) 4000_8019 Set Enable Error Interrupt Register (DMA0_SEEI) (always 20.3.10/427 reads 0) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 413 (DMA0_TCD0_NBYTES_MLOFFNO) TCD Signed Minor Loop Offset (Minor Loop Mapping and 4000_9008 Undefined 20.3.27/445 Offset Enabled) (DMA0_TCD0_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 4000_900C Undefined 20.3.28/446 (DMA0_TCD0_SLAST) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 414 Undefined 20.3.35/453 (DMA0_TCD1_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_903E (Channel Linking Disabled) Undefined 20.3.36/454 (DMA0_TCD1_BITER_ELINKNO) 4000_9040 TCD Source Address (DMA0_TCD2_SADDR) Undefined 20.3.22/441 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 415 20.3.29/446 TCD Signed Destination Address Offset 4000_9074 Undefined 20.3.30/447 (DMA0_TCD3_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9076 Undefined 20.3.31/447 Linking Enabled) (DMA0_TCD3_CITER_ELINKYES) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 416 TCD Signed Source Address Offset (DMA0_TCD5_SOFF) Undefined 20.3.23/441 4000_90A6 TCD Transfer Attributes (DMA0_TCD5_ATTR) Undefined 20.3.24/442 TCD Minor Byte Count (Minor Loop Mapping Disabled) 4000_90A8 Undefined 20.3.25/443 (DMA0_TCD5_NBYTES_MLNO) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 417 Linking Enabled) (DMA0_TCD6_CITER_ELINKYES) 4000_90D6 DMA0_TCD6_CITER_ELINKNO Undefined 20.3.32/449 TCD Last Destination Address Adjustment/Scatter Gather 4000_90D8 Undefined 20.3.33/450 Address (DMA0_TCD6_DLASTSGA) 4000_90DC TCD Control and Status (DMA0_TCD6_CSR) Undefined 20.3.34/450 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 418: Control Register (Dmax_Cr)
The channel priority registers assign the priorities; see the DCHPRIn registers. For round-robin arbitration, the channel priorities are ignored and channels are cycled through (from high to low channel number) without regard to priority. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 419 When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. Address: 4000_8000h base + 0h offset = 4000_8000h Reserved Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 420 The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. Continuous Link Mode Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 421: Error Status Register (Dmax_Es)
• An error termination to a bus master read or write cycle • A cancel transfer with error bit that will be set when a transfer is canceled via the corresponding cancel transfer control bit Fault reporting and handling for more details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 422 No source offset configuration error The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. Destination Address Error Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 423: Enable Request Register (Dmax_Erq)
DMA request input signals and this enable request flag must be asserted before a channel’s hardware service request is accepted. The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 424 The DMA request signal for the corresponding channel is enabled Enable DMA Request 0 ERQ0 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 425: Enable Error Interrupt Register (Dmax_Eei)
The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 426: Clear Enable Error Interrupt Register (Dmax_Ceei)
Clear All Enable Error Interrupts CAEE Clear only the EEI bit specified in the CEEI field Clear all bits in EEI 5–3 This field is reserved. Reserved Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 427: Set Enable Error Interrupt Register (Dmax_Seei)
Set only the EEI bit specified in the SEEI field. Sets all bits in EEI 5–3 This field is reserved. Reserved SEEI Set Enable Error Interrupt Sets the corresponding bit in EEI K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 428: Clear Enable Request Register (Dmax_Cerq)
Clear only the ERQ bit specified in the CERQ field Clear all bits in ERQ 5–3 This field is reserved. Reserved CERQ Clear Enable Request Clears the corresponding bit in ERQ. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 429: Set Enable Request Register (Dmax_Serq)
Set only the ERQ bit specified in the SERQ field Set all bits in ERQ 5–3 This field is reserved. Reserved SERQ Set Enable Request Sets the corresponding bit in ERQ. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 430: Clear Done Status Bit Register (Dmax_Cdne)
Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] 5–3 This field is reserved. Reserved CDNE Clear DONE Bit Clears the corresponding bit in TCDn_CSR[DONE] K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 431: Set Start Bit Register (Dmax_Ssrt)
Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] 5–3 This field is reserved. Reserved SSRT Set START Bit Sets the corresponding bit in TCDn_CSR[START] K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 432: Clear Error Register (Dmax_Cerr)
Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5–3 This field is reserved. Reserved CERR Clear Error Indicator Clears the corresponding bit in ERR K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 433: Clear Interrupt Request Register (Dmax_Cint)
Clear only the INT bit specified in the CINT field Clear all bits in INT 5–3 This field is reserved. Reserved CINT Clear Interrupt Request Clears the corresponding bit in INT K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 434: Interrupt Request Register (Dmax_Int)
The interrupt request for corresponding channel is active Interrupt Request 6 INT6 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 5 INT5 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 435: Error Register (Dmax_Err)
A zero in any bit position has no affect on the corresponding channel’s current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 436 An error in this channel has not occurred An error in this channel has occurred Error In Channel 0 ERR0 An error in this channel has not occurred An error in this channel has occurred K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 437: Hardware Request Status Register (Dmax_Hrs)
A hardware service request for channel 6 is not present A hardware service request for channel 6 is present Hardware Request Status Channel 5 HRS5 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 438 Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. A hardware service request for channel 0 is not present A hardware service request for channel 0 is present K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 439: Enable Asynchronous Request In Stop Register (Dmax_Ears)
Enable asynchronous DMA request in stop mode for channel 2. EDREQ_2 Disable asynchronous DMA request for channel 2. Enable asynchronous DMA request for channel 2. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 440: Channel N Priority Register (Dmax_Dchprin)
Channel n cannot suspend any channel, regardless of channel priority. 5–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CHPRI Channel n Arbitration Priority Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 441: Tcd Source Address (Dmax_Tcdn_Saddr)
= Undefined at reset. DMAx_TCDn_SOFF field descriptions Field Description SOFF Source address signed offset Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 442: Tcd Transfer Attributes (Dmax_Tcdn_Attr)
The eDMA defaults to privileged data access for all transactions. 8-bit 16-bit 32-bit Reserved 16-byte 32-byte Reserved Reserved 7–3 Destination Address Modulo DMOD See the SMOD definition DSIZE Destination data transfer size See the SSIZE definition K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 443: Tcd Minor Byte Count (Minor Loop Mapping Disabled) (Dmax_Tcdn_Nbytes_Mlno)
TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 444 After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 445: Tcd Signed Minor Loop Offset (Minor Loop Mapping And Offset Enabled)
The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 446: Tcd Last Source Address Adjustment (Dmax_Tcdn_Slast)
Reset * Notes: • x = Undefined at reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 447: Tcd Signed Destination Address Offset (Dmax_Tcdn_Doff)
Address: 4000_8000h base + 1016h offset + (32d × i), where i=0d to 7d Read ELINK LINKCH CITER Write Reset Read CITER Write Reset * Notes: • x = Undefined at reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 448 NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 449: Tcd Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 450: Tcd Last Destination Address Adjustment/Scatter Gather Address (Dmax_Tcdn_Dlastsga)
Address: 4000_8000h base + 101Ch offset + (32d × i), where i=0d to 7d Read MAJORLINKCH Write Reset Read ACTIVE MAJORELI DONE DREQ INTHALF INTMAJOR START Write Reset * Notes: • x = Undefined at reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 451 32-byte data structure loaded as the transfer control descriptor into the local memory. NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 452 If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. The channel is not explicitly started. The channel is explicitly started via a software initiated service request. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 453: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 454: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 455: Functional Description
20.4.1 eDMA basic data flow The basic flow of a data transfer can be partitioned into three segments. As shown in the following diagram, the first segment involves the channel activation: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 456 The following diagram illustrates the second part of the basic data flow: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 457 (if scatter/ gather is enabled). The updates to the TCD memory and the assertion of an interrupt request are shown in the following diagram. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 458: Fault Reporting And Handling
Each of these possible causes are detailed below: • The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. • The minor loop byte count must be a multiple of the source and destination transfer sizes. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 459 Due to pipeline effect, the next transfer is already in progress when the bus error is received by the eDMA. If a bus error K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 460 If a channel is terminated by an error and then issues another service request before the error is fixed, that channel executes and terminates with the same error condition. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 461: Channel Preemption
However, the microarchitecture of the eDMA also factors significantly into the resulting metric. 20.4.4.1 Peak transfer rates The peak transfer rates for several different source and destination transfers are shown in the following tables. These tables assume: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 462 SRAM. The same timing assumptions used in the previous example apply to this calculation. In particular, this metric also reflects the time required to activate the channel. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 463 Assuming zero wait states on the system bus, DMA requests can be processed every 9 cycles. Assuming an average of the access times associated with internal peripheral bus- to-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 464 • All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states viewed from the system bus data phase • System operates at 150 MHz For an SRAM to internal peripheral bus transfer, K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 465: Initialization/Application Information
1. Write to the CR if a configuration other than the default is desired. 2. Write the channel priority levels to the DCHPRIn registers if a configuration other than the default is desired. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 466 CPU intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 467: Programming Errors
The eDMA performs various tests on the transfer control descriptor to verify consistency in the descriptor data. Most programming errors are reported on a per channel basis with the exception of channel priority error (ES[CPE]). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 468: Arbitration Mode Considerations
(TCDn_CITER = TCDn_BITER = 1). The data transfer begins after the channel service request is acknowledged and the channel is selected to execute. After the transfer is complete, the TCDn_CSR[DONE] bit is set and an interrupt generates if properly enabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 469 Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 470 Write 32-bits to location 0x2004 → second iteration of the minor loop. e. Read byte from location 0x1008, read byte from location 0x1009, read byte from 0x100A, read byte from 0x100B. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 471 Write 32-bits to location 0x201C → last iteration of the minor loop → major loop complete. 14. eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 2 (TCDn_BITER). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 472: Monitoring Transfer Descriptor Status
There are two methods to test for minor loop completion when using software initiated service requests. The first is to read the TCDn_CITER field and test for a change. Another method may be extracted from the sequence shown below. The second method is K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 473 The true values of the SADDR, DADDR, and NBYTES are the values the eDMA engine currently uses in its internal register file and not the values in the TCD local memory for that channel. The addresses, SADDR and K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 474: Channel Linking
TCDn_CITER[E_LINK] = 1 TCDn_CITER[LINKCH] = 0xC TCDn_CITER[CITER] value = 0x4 TCDn_CSR[MAJOR_E_LINK] = 1 TCDn_CSR[MAJOR_LINKCH] = 0x7 executes as: 1. Minor loop done → set TCD12_CSR[START] bit K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 475: Dynamic Programming
This section provides recommended methods to change the programming model during channel execution. 20.5.7.1 Dynamically changing the channel priority The following two options are recommended for dynamically changing channel priority levels: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 476 NOTE The user must clear the TCD.done bit before writing the TCD.major.e_link bit. The TCD.done bit is cleared automatically by the eDMA engine after a channel begins execution. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 477 1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field for each TCD associated with a channel using dynamic scatter/gather. 2. Write 1b to the TCD.d_req bit. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 478 If e_sg = 0b, read the 32 bit TCD dlast_sga field. If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 479: Suspend/Resume A Dma Channel With Active Hardware Service Requests
TXFIFO upon the request. If the user needs to suspend the DMA/ transfer loop, perform the following steps: 1. Disable the DMA service request at the source by writing 0 to . Confirm that is 0. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 480 DMA_HRS[HRSn] is 0 for the appropriate channel. If no service request is present, disable the DMA channel by clearing the channel’s ERQ bit. If a service request is present, wait until the request has been processed and the HRS bit reads zero. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 481: Smart Card Interface Module (Emv Sim)
• Two general purpose counters available for use by software application with programmable clock selection for the counters • DMA support available to transfer data to/from FIFOs. Programmable option available to select interrupt or DMA feature K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 482: Block Diagram
Figure 21-1. EMV SIM Block Diagram 21.3 Design Overview The EMV SIM is designed to be compliant to the EMV ICC Specifications ver. 4.3 (dated Nov 2011) and the ISO-7816-3 standard. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 483 Framing Error. It can then direct the transmitter to insert NACK on parity error detection. For a block of bytes received, the receiver checks for LRC or CRC errors K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 484: Signal Description
Card Reset. Reset signal to Smart Card O EMVSIM_VCC_EN Card Power Enable. This signal controls the power to Smart Card EMVSIM_IO Card Data Line. Bi-directional data line. EMVSIM_PD Card Presence Detect. Signal indicating presence or removal of card K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 485: Memory Map And Registers
21.5.16/508 4004_E040 Block Guard Time Value Register (EMVSIM0_BGT_VAL) 0000_0000h 21.5.17/509 General Purpose Counter 0 Timeout Value Register 4004_E044 0000_FFFFh 21.5.18/509 (EMVSIM0_GPCNT0_VAL) General Purpose Counter 1 Timeout Value 4004_E048 0000_FFFFh 21.5.19/510 (EMVSIM0_GPCNT1_VAL) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 486: Version Id Register (Emvsimx_Ver_Id)
This read-only field is reserved and always has the value 0. 15–8 Transmit FIFO Depth TX_FIFO_ Value of parameter for Transmit FIFO Depth (in Bytes) DEPTH RX_FIFO_ Receive FIFO Depth DEPTH Value of parameter for Receive FIFO Depth (in Bytes) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 487: Clock Configuration Register (Emvsimx_Clkcfg)
0, 1 Max Divide value used (default 0 is used) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 488: Baud Rate Divisor Register (Emvsimx_Divisor)
0 - 4 Invalid. As per ISO 7816 specification, minimum value of F/D is 5 Divisor value for F = 372 and D = 1 (default) others Integer value of result of F/D K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 489: Control Register (Emvsimx_Ctrl)
(that is, when the FIFO becomes empty). No CRC or LRC value is transmitted (default) Transmit LRC or CRC info when FIFO empties (whichever is enabled) CRC Enable CRC_EN Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 490 Enables assertion of DMA write request when Transmit FIFO is empty. Request is held asserted till Transmit FIFO reaches the programmed data threshold value. Transmit Data Threshold Interrupt will not be generated when this bit is asserted. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 491 DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) DOZE instruction has no effect on EMV SIM module Kill all internal clocks KILL_CLOCKS Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 492 Enables initial character mode. Will be automatically cleared by hardware once a valid initial character is received. Initial Character Mode disabled Initial Character Mode enabled (default) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 493: Interrupt Mask Register (Emvsimx_Int_Mask)
Used to enable/disable the ability of the RX_DATA flag in the RX_STATUS register to generate EMV SIM interrupts. RX_DATA interrupt enabled RX_DATA interrupt masked (default) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 494 TDTF interrupt masked (default) Transmit FIFO Full Interrupt Mask TFF_IM Used to enable/disable the ability of the TFF flag in the TX_STATUS register to generate EMV SIM interrupts. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 495 Receive Data Threshold Interrupt Mask RDT_IM Used to enable/disable the ability of the RDTF flag in the RX_STATUS register to generate EMV SIM interrupts. RDTF interrupt enabled RDTF interrupt masked (default) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 496: Receiver Threshold Register (Emvsimx_Rx_Thd)
Used to set the NACK threshold for the transmitter. Once the threshold number set by TNCK_THD has been reached for the current byte being transmitted, the error flag TNTE in the TX_STATUS register will Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 497 Used to set the threshold value for the Transmit FIFO at which the TDTF bit in the TX_STATUS register will be set. When the number of bytes in the Transmit FIFO is less than or equal to TDT[3:0], TDTF will be set. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 498: Receive Status Register (Emvsimx_Rx_Status)
RX_WPTR Value of write pointer of Receive FIFO 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 499 CHAR_WAIT register. No CWT violation has occurred (default). Time between two consecutive characters has exceeded the value in CHAR_WAIT. CRC Check OK Flag CRC_OK Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 500 The RFO flag will cause an interrupt if the RFO_IM bit in the INT_MASK register. The RFO flag is a write-one-to-clear bit. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 501: Transmitter Status Register (Emvsimx_Tx_Status)
This read-only field is reserved and always has the value 0. 24–22 Transmit FIFO Byte Count TX_CNT These bits indicate the number of bytes stored in the transmit FIFO. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 502 LRC or CRC byte (if XMT_CRC_LRC bit = 1) has been transmitted. The TC flag will create an interrupt if TC_IM in the INT_MASK register is low. The TC bit is a write-one-to-clear bit. Transmit pending or in progress Transmit complete (default) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 503 FIFO will be aborted, and the TC, ETC, and TFE flags will be set. The TNTE flag will create an interrupt if TNACK_IM in the INT_MASK register is low. The TNTE bit is a write-one-to-clear bit. Transmit NACK threshold has not been reached (default) Transmit NACK threshold reached; transmitter frozen K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 504: Port Control And Status Register (Emvsimx_Pcsr)
This bit reflects the state of the Smart Card Presence Detect pin. It is not a latched register bit, but instead a synchronized version of the state of the pin itself. SIM Presence Detect pin is logic low SIM Presence Detectpin is logic high Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 505 Used to control the polarity of the SVEN output pad via the SVCC_EN bit. When set to '1', this bit will invert the value of SVCC_EN bit of this register and output to SVEN output pad of device. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 506: Receive Data Read Buffer (Emvsimx_Rx_Buf)
RX_BYTE Receive Data Byte Read Provides the byte value from the top of the receive FIFO. Each read access to this register will increment the read pointer of the Receive FIFO. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 507: Transmit Data Buffer (Emvsimx_Tx_Buf)
0x00 inserts no additional ETUs, while a value of 0xFE inserts 254 additional ETUs. A value of 0xFF subtracts one ETU by reducing the number of STOP bits from two to one. no additional ETUs inserted (default) 1 additional ETU inserted Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 508: Character Wait Time Value Register (Emvsimx_Cwt_Val)
The time from START bit of last byte sent from the EMV SIM module to the START bit of the first byte sent from the Smart Card must be less than the value in this register. If it is not, then the BWT_TO flag is set. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 509: Block Guard Time Value Register (Emvsimx_Bgt_Val)
This counter is intended to be used for any events that must be monitored for duration based on the card clock, receiver sample rate, or ETU rate (transmit clock). Example: ATR arrival time and ATR duration. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 510: General Purpose Counter 1 Timeout Value (Emvsimx_Gpcnt1_Val)
ETU period to be used by the transmitter or receiver • Enable power to the Smart Card by setting the VCC_EN bit in PCSR register • Enable the Smart Card clock by setting the SCEN bit in PCSR register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 511 • Configure the timeout values for Character Wait Time Counter, the Block Wait Timer Counter and the Block Guard Time Counter • Enable necessary interrupts by clearing respective bits in the INT_MASK register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 512: Smart Card Interface And Control
NOTE The Transmit and Receive operations are mutually exclusive and should not be enabled together. 21.6.2 Smart Card Interface and Control K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 513 • Smart Card Clock (CLK) is turned off to low • Smart Card IO (IO) is transitioned from high impedance to low • Smart Card Voltage Enable (VCC_EN) to turned off (pin driven low) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 514 (usually 32 kHz clock source) to be active on the device. The auto power down sequence will clear the following register bits upon power down sequence completion: • SPD bit in PCSR register • SCEN bit in PCSR register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 515: Emv Sim Receiver
When receiving inverse convention data, the transformation of the data back to direct convention format is done in hardware, including the inversion of the data and parity bits. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 516 (0x3B) could be decoded as what appears to be a valid initial character for inverse convention (that is, 0x3F). The EMV SIM module will not recognize this as a valid K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 517 LRC & CRC: The receiver also checks the LRC or CRC on the incoming block of bytes (if LRC or CRC is enabled). The result of the CRC or LRC check is updated in the RX_STATUS register once the complete message block is received. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 518 • Error Detection Code • “T=1” cards can specify LRC or CRC error detection codes to be used. The EMV SIM module provides hardware support for both the LRC and CRC operations. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 519: Emv Sim Transmitter
The transmitter sends each byte to the LRC or CRC block to allow the check byte generation. At the end of each byte, the transmitter inserts the programmed Guard ETUs. Refer to Protocol Timers section for more details on Guard Time Counter. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 520 • The character waiting time (CWT) is defined as the time between the start bits of two consecutive characters. The value of CWT can range from 12 ETU to 32779 ETU. The time between transmitted characters is controlled by the K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 521: Lrc And Crc
8-bit exclusive-OR on all received or transmitted characters. At the end of the reception of a block of characters, the result is expected to be 00. If so, the LRC_OK bit is set in the RX_STATUS register. During transmission, the LRC block Exclusive-ORs K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 522 EMV SIM transmitter as the final two characters when the transmit FIFO empties. At the end of the reception of a block of characters, the residual from the CRC calculation is compared and the CRC_OK bit is set in the RX_STATUS register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 523: Message Handling
TX_DMA_EN = 1 in the CTRL register. On setting this bit, a DMA request will be asserted and remain asserted till the number of bytes in FIFO reached the programmed threshold value (TDT[3:0] in the TX_THD register). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 524 1 in RX_STATUS register). The received byte will be discarded leaving the FIFO with the first 4 bytes received. If the ONACK bit in the CTRL register is asserted, the K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 525: Protocol Timers
If the time between characters exceeds this value, an interrupt flag will be set and an interrupt generated if the mask is clear. The CWT can be configured as follows: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 526 FIFO. This is necessary to avoid the condition where writes to Tx FIFO are very slow (more than 1 ETU time apart) and if BWT is enabled earlier, then BWT error can trigger falsely. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 527 The counter will begin to count at the card clock rate as soon as these conditions are met. To run the counters from the receive clock source the following conditions must be met: • ‘KILL_CLOCKS = 0’ in the CTRL register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 528: Answer To Reset (Atr) Detection
ISO 7816-3 spec, both “T=0” and “T=1” cards will communicate initially using 12 ETU character durations. The following steps provide a suggested approach to configure the EMV SIM module to receive the ATR. • Clear RCVR11 bit in the CTRL register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 529 • Enable the Character Wait Time Counter by setting the CWT_EN bit in the CTRL register The last step in preparing for ATR reception is to enable the receiver. • Set RCV_EN bit in CTRL register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 530 • Enable the transmitter by setting the XMT_EN bit in the CTRL register. • Write the characters to be sent as response (max 4) to the transmit FIFO using the TX_BUF register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 531 SIM module. In order to send the response or the first block, the following steps should be performed: • Set the desired transmit FIFO threshold level by writing the TDT[3:0] bits in the TX_THD register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 532 Once the transmission is complete, the EMV SIM module should be completely configured for standard operation with the T=1 Smart Card. The software can continue to service RDTF interrupts for received characters, and TDTF interrupts for transmitted characters. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 533: Flexible I/O (Flexio)
• I2S • Camera IF • Motorola 68K/Intel 8080 bus • PWM/Waveform generation The following key features are provided: • Array of 32-bit shift registers with transmit, receive and data match modes K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 534: Block Diagram
The following diagram gives a high-level overview of the configuration of FlexIO timers and shifters. SHIFTBUF0 Input Output Selection Selection SHIFTER0 SHIFTBUFi FXIO_Dn FXIO_Dn out/outen SHIFTERi Timer Selection TIMER0 TIMERi External Triggers Figure 22-1. FlexIO block diagram K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 535: Modes Of Operation
Memory Map and Registers 22.2.1 FLEXIO Register Descriptions 22.2.1.1 FLEXIO Memory Map Offset Register Width Access Reset value (In bits) 400CA000h Version ID (VERID) 01010001h Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 536 NBS7) 400CA700h - Shifter Buffer N Half Word Swapped (SHIFTBUFHWS0 - SHIFTBUF 00000000h 400CA71Ch HWS7) 400CA780h - Shifter Buffer N Nibble Swapped (SHIFTBUFNIS0 - SHIFTBUFNIS7) 00000000h 400CA79Ch 22.2.1.2 Version ID (VERID) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 537 This read only field returns the minor version number for the module specification. 15-0 Feature Specification Number FEATURE This read only field returns the feature set number. 0000000000000000b - Standard features implemented. 0000000000000001b - Supports state, logic and parallel modes. 22.2.1.3 Parameter (PARAM) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 538 Number of external triggers implemented. 23-16 Pin Number Number of Pins implemented. 15-8 Timer Number TIMER Number of Timers implemented. Shifter Number SHIFTER Number of Shifters implemented. 22.2.1.4 FlexIO Control (CTRL) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 539 0b - Configures for normal register accesses to FlexIO 1b - Configures for fast register accesses to FlexIO Software Reset SWRST Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 540 22.2.1.5 Pin State (PIN) 22.2.1.5.1 Address Register Offset 400CA00Ch 22.2.1.5.2 Diagram Bits Reset Bits Reset 22.2.1.5.3 Fields Field Function 31-0 Pin Data Input Returns the input data on each of the FlexIO pins. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 541 For SMOD=State, the status flag for a shifter will set when it is selected by the current state pointer. For SMOD=Logic, returns the current value of the programmable logic block output. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 542 400CA014h 22.2.1.7.2 Function 22.2.1.7.3 Diagram Bits Reset Bits Reset 22.2.1.7.4 Fields Field Function 31-8 — Shifter Error Flags The shifter error flag is set when one of the following events occurs: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 543 00000000b - Shifter Error Flag is clear 00000001b - Shifter Error Flag is set 22.2.1.8 Timer Status (TIMSTAT) 22.2.1.8.1 Address Register Offset TIMSTAT 400CA018h 22.2.1.8.2 Function 22.2.1.8.3 Diagram Bits Reset Bits Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 544 00000000b - Timer Status Flag is clear 00000001b - Timer Status Flag is set 22.2.1.9 Shifter Status Interrupt Enable (SHIFTSIEN) 22.2.1.9.1 Address Register Offset SHIFTSIEN 400CA020h 22.2.1.9.2 Function 22.2.1.9.3 Diagram Bits Reset Bits SSIE Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 545 22.2.1.10 Shifter Error Interrupt Enable (SHIFTEIEN) 22.2.1.10.1 Address Register Offset SHIFTEIEN 400CA024h 22.2.1.10.2 Function 22.2.1.10.3 Diagram Bits Reset Bits SEIE Reset 22.2.1.10.4 Fields Field Function 31-8 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 546 Offset TIMIEN 400CA028h 22.2.1.11.2 Function 22.2.1.11.3 Diagram Bits Reset Bits TEIE Reset 22.2.1.11.4 Fields Field Function 31-8 — Timer Status Interrupt Enable TEIE Enables interrupt generation when corresponding TSF is set. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 547 Shifter Status DMA Enable SSDE Enables DMA request generation when corresponding SSF is set. 00000000b - Shifter Status Flag DMA request is disabled 00000001b - Shifter Status Flag DMA request is enabled K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 548 The current state field maintains a pointer to keep track of the current Shifter (configured for State mode) enabled to drive outputs and compute the next state. See 'State Mode' section for more detail. 22.2.1.14 Shifter Control N (SHIFTCTLa) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 549 1b - Shift on negedge of Shift clock 22-18 — 17-16 Shifter Pin Configuration PINCFG 00b - Shifter pin output disabled 01b - Shifter pin open drain or bidirectional output enable Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 550 111b - Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. 22.2.1.15 Shifter Configuration N (SHIFTCFGa) 22.2.1.15.1 Address Register Offset SHIFTCFG0 400CA100h SHIFTCFG1 400CA104h SHIFTCFG2 400CA108h SHIFTCFG3 400CA10Ch SHIFTCFG4 400CA110h SHIFTCFG5 400CA114h SHIFTCFG6 400CA118h SHIFTCFG7 400CA11Ch 22.2.1.15.2 Function K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 551 15-9 — Input Source INSRC Selects the input source for the shifter. 0b - Pin 1b - Shifter N+1 Output — — Shifter Stop bit Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 552 1 22.2.1.16 Shifter Buffer N (SHIFTBUFa) 22.2.1.16.1 Address Register Offset SHIFTBUF0 400CA200h SHIFTBUF1 400CA204h SHIFTBUF2 400CA208h SHIFTBUF3 400CA20Ch SHIFTBUF4 400CA210h SHIFTBUF5 400CA214h SHIFTBUF6 400CA218h SHIFTBUF7 400CA21Ch K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 553 SHIFTBUF[23:0] is used to configure the value of the next state transition. See 'State Mode' section for more detail. 22.2.1.17 Shifter Buffer N Bit Swapped (SHIFTBUFBISa) 22.2.1.17.1 Address Register Offset SHIFTBUFBIS0 400CA280h Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 554 Reset 22.2.1.17.4 Fields Field Function 31-0 Shift Buffer SHIFTBUFBIS Alias to SHIFTBUF register, except reads/writes to this register are bit swapped. Reads return SHIFTBUF[0:31]. 22.2.1.18 Shifter Buffer N Byte Swapped (SHIFTBUFBYSa) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 555 Shift Buffer SHIFTBUFBYS Alias to SHIFTBUF register, except reads/writes to this register are byte swapped. Reads return { SHIFTBUF[7:0], SHIFTBUF[15:8], SHIFTBUF[23:16], SHIFTBUF[31:24] }. 22.2.1.19 Shifter Buffer N Bit Byte Swapped (SHIFTBUFBBSa) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 556 Shift Buffer SHIFTBUFBBS Alias to SHIFTBUF register, except reads/writes to this register are bit swapped within each byte. Reads return { SHIFTBUF[24:31], SHIFTBUF[16:23], SHIFTBUF[8:15], SHIFTBUF[0:7] }. 22.2.1.20 Timer Control N (TIMCTLa) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 557 • When TRGSRC = 0, the valid values for N will depend on TRIGGER field in FLEXIO_PARAM register. Refer to the chip configuration section for external trigger selection. NOTE: For a pin, N=0 to 31. For a Shifter/Timer, N=0 to 7. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 558 00b - Timer Disabled. 01b - Dual 8-bit counters baud/bit mode. 10b - Dual 8-bit counters PWM mode. 11b - Single 16-bit counter mode. 22.2.1.21 Timer Configuration N (TIMCFGa) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 559 10b - Timer output is logic one when enabled and on timer reset 11b - Timer output is logic zero when enabled and on timer reset 23-22 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 560 101b - Timer enabled on Pin rising edge and Trigger high 110b - Timer enabled on Trigger rising edge 111b - Timer enabled on Trigger rising or falling edge — Timer Stop Bit TSTOP Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 561 1b - Start bit enabled — 22.2.1.22 Timer Compare N (TIMCMPa) 22.2.1.22.1 Address Register Offset TIMCMP0 400CA500h TIMCMP1 400CA504h TIMCMP2 400CA508h TIMCMP3 400CA50Ch TIMCMP4 400CA510h TIMCMP5 400CA514h TIMCMP6 400CA518h TIMCMP7 400CA51Ch 22.2.1.22.2 Function K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 562 (CMP[15:0] + 1) / 2. 22.2.1.23 Shifter Buffer N Nibble Byte Swapped (SHIFTBUFNBSa) 22.2.1.23.1 Address Register Offset SHIFTBUFNBS0 400CA680h SHIFTBUFNBS1 400CA684h SHIFTBUFNBS2 400CA688h SHIFTBUFNBS3 400CA68Ch SHIFTBUFNBS4 400CA690h SHIFTBUFNBS5 400CA694h SHIFTBUFNBS6 400CA698h SHIFTBUFNBS7 400CA69Ch K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 563 SHIFTBUF[11:8], SHIFTBUF[15:12], SHIFTBUF[3:0], SHIFTBUF[7:4] }. 22.2.1.24 Shifter Buffer N Half Word Swapped (SHIFTBUFHWSa) 22.2.1.24.1 Address Register Offset SHIFTBUFHWS0 400CA700h SHIFTBUFHWS1 400CA704h SHIFTBUFHWS2 400CA708h SHIFTBUFHWS3 400CA70Ch SHIFTBUFHWS4 400CA710h SHIFTBUFHWS5 400CA714h SHIFTBUFHWS6 400CA718h SHIFTBUFHWS7 400CA71Ch K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 564 { SHIFTBUF[15:0], SHIFTBUF[31:24] }. 22.2.1.25 Shifter Buffer N Nibble Swapped (SHIFTBUFNISa) 22.2.1.25.1 Address Register Offset SHIFTBUFNIS0 400CA780h SHIFTBUFNIS1 400CA784h SHIFTBUFNIS2 400CA788h SHIFTBUFNIS3 400CA78Ch SHIFTBUFNIS4 400CA790h SHIFTBUFNIS5 400CA794h SHIFTBUFNIS6 400CA798h SHIFTBUFNIS7 400CA79Ch K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 565: Functional Description
Timer assigned to the Shifter via the SHIFTCTL[TIMSEL] register. The Shifters are designed to support either DMA, interrupt or polled operation. The following block diagram provides a detailed view of the Shifter microarchitecture. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 566 SHIFTBUF register when a store event is signalled by the assigned Timer. Checking for a start/stop bit can be enabled before/after shifter data is sampled by configuring the SHIFTCFG[SSTART], TIMCFG[TSTART] or SHIFTCFG[SSTOP], TIMCFG[TSTOP] registers in the Shifter and Timer. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 567 The Shifter Status Flag (SHIFTSTAT[SSF]) and any enabled interrupts or DMA requests will set when a match occurs. The flag will clear automatically as soon as there is no longer a match between Shifter data and SHIFTBUF register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 568 3 input pins. The following table details how the next state value is computed when the current state pointer is pointing to Shifter i. Table 22-2. Next State computation for SHIFTSTATE[STATE]=i FXIO_D[PINSEL+2] FXIO_D[PINSEL+1] FXIO_D[PINSEL] Next State Value Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 569 When configured for Logic mode (SHIFTCTL[SMOD]=Logic), the SHIFTBUF register is used to implement a 5-input, 32-bit programmable logic look-up table. The following diagram provides a detailed view of Shifter microarchitecture when configured for Logic mode. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 570 Note that other shifters/timers could potentially be configured to drive the input pins of a given look-up table (without synchronization), allowing the user to concatenate look-up tables or create complex combinations of shifters/timers as desired. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 571: Timer Operation
(TIMENA) is detected then the following events occur. • Timer counter will load the current value of the Compare Register and start decrementing as configured by TIMDEC. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 572 SSTOP. • On the first rising edge of the shifter clock after the compare, the timer counter will reload the current value of the Compare Register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 573: Pin Operation
2. Number of pins driven by the shifter per Shift clock (only on shifters supporting parallel transmit i.e. SHIFTER0, SHIFTER4). 3. Number of pins sampled by the shifter per Shift clock (only on Shifter supporting parallel receive i.e. SHIFTER3, SHIFTER7). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 574 For timing considerations such as output valid time and input setup time for specific applications (SPI Master, SPI Slave, I2C Master, I2S Master, I2S Slave) please refer to the FlexIO Application Information Section. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 575: Application Information
Shifter 0 status flag as inverted internal trigger source. Can support CTS by configuring PINSEL=0x1 (for Pin 1) and PINPOL=0x1. SHIFTBUFn Data to transmit Transmit data can be written to SHIFTBUF[7:0] to initiate an 8-bit K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 576: Uart Receive
Configure dual 8-bit counter using inverted Pin 0 input. SHIFTBUFn Data to receive Received data can be read from SHIFTBUFBYS[7:0], use the Shifter Status Flag to indicate when data can be K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 577 Received data can be read from SHIFTBUFBYS[7:0], use the Shifter Status Flag to indicate when data can be read using interrupt or DMA request. Can support MSB first transfer by reading from SHIFTBUFBIS[7:0] register instead. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 578: Spi Master
Transmit data can be written to SHIFTBUF, use the Shifter Status Flag to indicate when data can be written using interrupt or DMA request. Can Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 579 SHIFTBUF, use the Shifter Status Flag to indicate when data can be written using interrupt or DMA request. Can support MSB first transfer by writing to SHIFTBUFBBS register instead. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 580: Spi Slave
Transmit data can be written to SHIFTBUF, use the Shifter Status Flag to indicate when data can be written using interrupt or DMA request. Can Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 581 Received data can be read from SHIFTBUFBYS, use the Shifter Status Flag to indicate when data can be read using interrupt or DMA request. Can support MSB first transfer by reading from SHIFTBUFBIS register instead. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 582: I2C Master
(to guarantee some SDA hold time). Since the SCL output is synchronous with FlexIO clock, the synchronization delay is 1 cycle and then 1 cycle to generate the output. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 583: I2S Master
FlexIO waits for the first write to the transmit data buffer before K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 584 SHIFTBUFBIS, use the Shifter Status Flag to indicate when data can be written using interrupt or DMA request. Can support LSB first transfer by writing to SHIFTBUF register instead. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 585: I2S Slave
(bit clock). TIMCTLn 0x0440_0383 Configure 16-bit counter using inverted Pin 3 input (frame sync), with Pin 2 input (bit clock) as the trigger. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 586: Camera Interface
Configure 8-bit parallel shift in from adjacent shifter. SHIFTCFGn+3 0x0007_0000 Configure 8-bit parallel shift in from pins FXIO_D[7:0] (D[7:0]). SHIFTCTLn...n+3 0x0080_0001 Configure receive using Timer 0 on negedge of clock. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 587: Motorola 68K/Intel 8080 Bus Interface
4 of the FlexIO 0x0000_1F01 (16-beats) clock. Set TIMCMP[15:8] = (number of beats x 2) - 1. Set TIMCMP[7:0] = (baud rate divider / 2) - 1. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 588 In general, any operation to a 68K/8080 bus slave will begin with a register write cycle followed by one or more data read or write cycles. To accomplish this, the following program flow should be used: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 589: Low Power State Machine
Throughout this operation, the CPU can be kept in a STOP/VLPS mode, by clearing the CTRL[DOZEN] bit and ensuring the FLEXIO_CLK is enabled. The state diagram below shows the states and transitions implemented by this example. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 590 FXIO_D[4:2] as inputs to select next state and Timer0 output low to trigger next state. SHIFTBUF2 0x0224_9249 State2: Drive FXIO_D[1:0]=10, transition to State1 when Timer0 output low Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 591 0x0010_7600 Configure timer enabled on trigger rising edge, disabled on trigger falling edge, decrement on trigger edge. TIMCTL1 0x0F03_0303 Configure timer output enabled on FXIO_D[3], external trigger 15 (comparator output) selected. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 592 Application Information K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 593: Flash Memory Controller (Fmc)
A 64-bit speculation buffer can prefetch the next 64-bit flash memory location, and a shared 4-way, 4-set cache can store previously accessed flash memory data for quick access times. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 594: Features
In this device, the PFC = Platform Flash Controller does not have any program model; therefore, there are no register definitions in the PFC chapter. All PFC operating controls are in the Platform Control Register (MCMx_PLACR) in the MCM module. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 595: Flash Access Control (Fac) Function
The access control functionality is implemented in 2 separate blocks within the SoC. The Flash Management Unit (FMU) includes non-volatile configuration information that is retrieved during reset and and sent to the platform to control access to the flash array during normal operation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 596 Segment Size (Fraction of total Flash) 64 Segment Encodings 0x0_0000_0000 – (Flash_size/64-1) 1/64 (Flash_size/64) – 2*(Flash_size/64-1) 1/64 ..63*(Flash_size/64) – 62*(Flash_size/64-1) 1/64 32 Segment Encodings Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 597 64 or 32 Platform Direct sacc (supervisor access control) register numsg Platform NUMSG bit field - Binary encoded number of segments 0x40 for 64 segments Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 598 0's. This will impact debug breakpoints. See the debug section for details. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 599 NOPs, to prevent additional code from being programmed in that segment by hackers. 23.5.2.5 Access Check Evaluation The flash controller FAC provides a cycle-by-cycle evaluation of the access rights for each data transaction routed to the on-chip flash memory. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 600 0x6: // {user, data} && {supv+user, ifetch-only} case 0xc: // {supv, data} && {supv-only, ifetch-only} case 0xe: // {supv, data} && {supv+user, ifetch-only} fac_error = 1; break; } // switch() } // fac_evaluation() K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 601: Initialization And Application Information
FMC's cache might need to be disabled and/or flushed, to prevent the possibility of returning stale data. To invalidate the cache in this manner, use the Flash Cache Invalidate control register in the MCM. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 602 Initialization and application information K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 603: Flash Memory Module (Ftfa)
('1') states and/or programmed ('0') states. Therefore, it is recommended that each flash block or sector be re-erased immediately prior to factory programming to ensure that the full data retention capability is achieved. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 604: Features
• Supports MCU security mechanisms which prevent unauthorized access to the flash memory contents 24.1.2 Block Diagram The block diagram of the flash memory module is shown in the following figure. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 605: Glossary
HSRUN — An MCU power mode enabling high-speed access to the memory resources in the flash module. The user has no access to the flash command set when the MCU is in HSRUN mode. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 606: External Signal Description
Word — 16 bits of data with an aligned word having byte-address[0] = 0. 24.2 External Signal Description The flash memory module contains no signals that connect off-chip. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 607: Memory Map And Registers
Read Resource commands in Read Once Command, Program Once Command Read Resource Command). The contents of the program flash IFR are summarized in the table found here and further described in the subsequent paragraphs. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 608: Program Flash Erasable Ifr Map
The program flash erasable IFR is nonvolatile information memory that can be erased but has limited program capabilities and limited read access. The contents of the program flash erasable IFR fields are summarized in the table found here. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 609: Register Descriptions
4002_0000 Flash Status Register (FTFA_FSTAT) 24.3.4.2/ 4002_0001 Flash Configuration Register (FTFA_FCNFG) 24.3.4.3/ 4002_0002 Flash Security Register (FTFA_FSEC) Undefined 24.3.4.4/ 4002_0003 Flash Option Register (FTFA_FOPT) Undefined Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 610 Execute-only Access Registers (FTFA_XACCH1) Undefined 24.3.4.7/ 4002_001B Execute-only Access Registers (FTFA_XACCH0) Undefined 24.3.4.7/ 4002_001C Execute-only Access Registers (FTFA_XACCL3) Undefined 24.3.4.7/ 4002_001D Execute-only Access Registers (FTFA_XACCL2) Undefined Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 611 When set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in this register prevent the launch of any more commands until the flag is cleared (by writing a one to it). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 612 As a status flag, this field cannot (and need not) be cleared by the user like the other error flags in this register. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 613 (no command is currently being executed). ERSAREQ is cleared by the flash memory module when the operation completes. No request or request complete Request to: 1. run the Erase All Blocks command, Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 614 Enables or disables backdoor key access to the flash memory module. Backdoor key access disabled Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 615 Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. However, the register is written to 0xFF if the contents of the flash nonvolatile option byte are 0x00. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 616 This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific flash command, typically an address and/or data values. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 617 KB of program flash memory or less, FPROT1 is not used. For configurations with 16 KB of program flash memory, FPROT2 is not used. The bitfields are defined in each register as follows: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 618 Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 619 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only access control fields that are loaded during the reset sequence. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 620 Supervisor-only access register Program Flash IFR address A Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9 SACCH3 0xB0 0xB8 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 621 The contents of this register are loaded during the reset sequence. Address: 4002_0000h base + 28h offset = 4002_0028h Read SGSIZE Write Reset * Notes: • x = Undefined at reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 622: Functional Description
The NUMSG field indicates the number of equal-sized segments in the program flash. 0x4x Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes) 24.4 Functional Description The information found here describes functional details of the flash memory module. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 623: Flash Protection
Block, Erase Flash Sector) monitor FXACC contents to protect flash memory but the FSACC contents do not impact flash command operation. AN5112: Using the Kinetis Flash Execute-Only Access Control Feature for further details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 624 Program flash size / 64 SACCH0[SA61] Program flash size / 64 SACCH0[SA62] Program flash size / 64 SACCH0[SA63] Last program flash address Figure 24-4. Program flash supervisor access control (256KB or 512KB of program flash) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 625: Interrupts
24.4.4.2 Stop Mode When the MCU requests stop mode, if a flash command is active (CCIF = 0) the command execution completes before the MCU is allowed to enter stop mode. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 626: Functional Modes Of Operation
• The user may read from one logical program flash memory space while flash commands are active in the other logical program flash memory space. Simultaneous operations are further discussed in Allowed Simultaneous Flash Operations. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 627: Flash Command Operations
The user must load the FCCOB registers with all parameters required by the desired flash command. The individual registers that make up the FCCOB data set can be written in any order. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 628 FCCOB and FSTAT registers. 4. The flash memory module sets FSTAT[CCIF] signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 629 The following table summarizes the function of all flash commands. FCMD Command Program flash 0 Program flash 1 Function 0x00 Read 1s Block × × Verify that a program flash block is erased. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 630 0x45 Verify Backdoor × × Release MCU security Access Key after comparing a set of user-supplied security keys to those stored in the program flash. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 631 Erase All Blocks Unsecure × × — × × — Read 1s All Execute-only 0x4A × × × × — — Segments Erase All Execute-only 0x4B × × × × — — Segments K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 632: Margin Read Commands
The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 633: Flash Command Description
MCU with the collision error flag (FSTAT[RDCOLERR]) set. CAUTION Flash data must be in the erased state before being programmed. Cumulative programming of bits (adding more zeros) is not allowed. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 634 The Read 1s Section command checks if a section of program flash memory is erased to the specified read margin level. The Read 1s Section command defines the starting address and the number of phrases to be verified. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 635 The requested number of phrases is 0. FSTAT[ACCERR] Read-1s fails. FSTAT[MGSTAT0] 24.4.11.3 Program Check Command The Program Check command tests a previously programmed program flash longword to see if it reads correctly at the specified margin level. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 636 Table 24-12. Program Check Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid flash address is supplied FSTAT[ACCERR] Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 637 Resource Description Resource Size Local Address Range Select Code 0x00 Program Flash 0 IFR 256 Bytes 0x00_0000–0x00_00FF 0x01 Version ID 8 Bytes 0x00_0000–0x00_0007 1. Located in program flash 0 reserved space. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 638 Flash address [15:8] Flash address [7:0] Byte 0 program value Byte 1 program value Byte 2 program value Byte 3 program value 1. Must be longword aligned (Flash address [1:0] = 00). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 639 Flash address [23:16] in the flash block to be erased Flash address [15:8] in the flash block to be erased Flash address [7:0] in the flash block to be erased 1. Must be longword aligned (Flash address [1:0] = 00). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 640 FPROT registers). If the erase-verify fails the FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase Flash Sector operation completes. The Erase Flash Sector command is suspendable (see the FCNFG[ERSSUSP] bit and Figure 24-6). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 641 Erase Flash Sector operation (CCIF is cleared) and the request to suspend the operation again (ERSSUSP is set). This minimum time period is required to ensure that the Erase Flash Sector operation will eventually complete. If the minimum period is continually K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 642 Aborting the erase leaves the bitcells in an indeterminate, partially-erased state. Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 643 Set CCIF ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 24-6. Suspend and Resume of Erase Flash Sector Operation K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 644 Apply the 'Factory' margin to the normal read-1 level Table 24-24. Read 1s All Blocks Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 645 The Read Once command can be executed any number of times. Table 24-26. Read Once Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid record index is supplied FSTAT[ACCERR] K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 646 If erased, then the selected record is programmed using the values provided. The Program Once command also verifies that the programmed values read back correctly. The CCIF flag is set after the Program Once operation has completed. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 647 IFR space containing the Program Once XACC and SACC fields will not be erased and, therefore, the contents of the Program Once XACC and SACC fields will not change. The contents of the FXACC and FSACC registers will not be impacted K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 648 FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash Configuration Field (see Flash Configuration Field Description). The column labelled Flash Configuration Field offset address shows the location of the matching byte in the Flash Configuration Field. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 649 Backdoor key access has not been enabled (see the description of the FSEC register) FSTAT[ACCERR] This command is launched and the backdoor key has mismatched since the last power down FSTAT[ACCERR] reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 650 Table 24-34. Erase All Blocks Unsecure Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] Any errors have been encountered during erase or program verify operations FSTAT[MGSTAT0] K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 651 Table 24-37. Read 1s All Execute-only Segments Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Sector size is larger than segment size FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 652 FSTAT[ACCERR] Sector size is larger than segment size FSTAT[ACCERR] Any XA controlled segment in the program flash memory is protected FSTAT[FPVIOL] Any errors have been encountered during the verify operation FSTAT[MGSTAT0] K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 653: Security
Chip Security State Operating Mode Unsecure Secure NVM Normal Full command set Only the Erase All Blocks, Erase All Blocks NVM Special Full command set Unsecure and Read 1s All Blocks commands. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 654 FSEC register only. It does not alter the security byte or the keys stored in the Flash Configuration Field (Flash Configuration Field Description). After the next reset of the chip, the security state of the flash memory K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 655: Reset Sequence
If a reset occurs while any flash command is in progress, that command is immediately aborted. The state of the word being programmed or the sector/block being erased is not guaranteed. Commands and operations do not automatically resume after exiting reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 656 Functional Description K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 657: Interrupt Multiplexer (Intmux)
• Each channel receives 32 interrupt sources and has 1 interrupt output • Each interrupt source can be enabled or disabled • Each channel supports Logic AND or Logic OR of all enabled interrupt sources 25.1.3 Block diagram K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 658: Memory Map And Register Definition
N: Interrupt Channel Instance Number (N=3) X: Interrupt Source Number for each channel (X=32) 25.2 Memory Map and register definition This section includes the module memory map and detailed descriptions of all registers. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 659: Channel N Control Status Register (Intmuxx_Chn_Csr)
Address: 4002_4000h base + 0h offset + (64d × i), where i=0d to 3d IRQP Reset CHIN IRQN Reset * Notes: • CHIN field: The reset value of CHIN depends on the channel number. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 660: Channel N Vector Number Register (Intmuxx_Chn_Vec)
No operation. Perform a software reset on this channel. 25.2.2 Channel n Vector Number Register (INTMUXx_CHn_VEC) Address: 4002_4000h base + 4h offset + (64d × i), where i=0d to 3d VECN Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 661: Channel N Interrupt Enable Register (Intmuxx_Chn_Ier_31_0)
These bits are used to enable the interrupt sources of this channel. Interrupt is disabled. Interrupt is enabled. 25.2.4 Channel n Interrupt Pending Register (INTMUXx_CHn_IPR_31_0) Address: 4002_4000h base + 20h offset + (64d × i), where i=0d to 3d INTP Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 662: Functional Description
Further control for each output channel is available by selecting the Boolean operation to perform on pending interrupts. The default is logical OR, but logical AND can be selected via the CHn_CSR[AND] register bit. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 663: Intmux Vectors
Unlike the NVIC, the INTMUX does not latch pending source interrupts. This means that the INTMUX output channel ISRs must check for and handle a 0 value of the CHn_VEC register to account for spurious interrupts. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 664 Functional Description K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 665: Low-Leakage Wakeup Unit (Llwu)
• Support for up to 32 external input pins and up to 8 internal modules with individual enable bits for MCU interrupt from low leakage modes • Support for up to 8 internal modules with individual enable bits for DMA wakeup from low leakage modes K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 666: Modes Of Operation
The LLWU is not active in all non-low leakage modes where detection and control logic are in a static state. The LLWU registers are accessible in non-low leakage modes and are available for configuring and reading status when bus transactions are possible. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 667: Block Diagram
Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive. 26.1.3 Block diagram The following figure is the block diagram for the LLWU module. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 668: Llwu Signal Descriptions
External pin sources LLWU_P0 wakeup occurred Edge detect WUPE0 Figure 26-1. LLWU block diagram 26.2 LLWU signal descriptions The signal properties of LLWU are shown in the table found here. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 669: Memory Map/Register Definition
LLWU registers are unaffected by reset types that do not trigger Chip Reset not VLLS. For more information about the types of reset on this chip, refer to the Introduction details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 670: Version Id Register (Llwu_Verid)
MINOR This read only field returns the minor version number for the module specification. FEATURE Feature Specification Number This read only field returns the feature set number. 0x0000 Standard features implemented K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 671: Parameter Register (Llwu_Param)
Introduction details for more information. Address: 4006_1000h base + 8h offset = 4006_1008h WUPE15 WUPE14 WUPE13 WUPE12 WUPE11 WUPE10 WUPE9 WUPE8 Reset WUPE7 WUPE6 WUPE5 WUPE4 WUPE3 WUPE2 WUPE1 WUPE0 Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 672 External input pin enabled with any change detection 19–18 Wakeup Pin Enable For LLWU_P9 WUPE9 Enables and configures the edge detection for the wakeup pin. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 673 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 674: Llwu Pin Enable 2 Register (Llwu_Pe2)
Chip Reset not VLLS. See the Introduction details for more information. Address: 4006_1000h base + Ch offset = 4006_100Ch WUPE31 WUPE30 WUPE29 WUPE28 WUPE27 WUPE26 WUPE25 WUPE24 Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 675 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 676 External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 677: Llwu Module Interrupt Enable Register (Llwu_Me)
This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 678 Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 2 WUME2 Enables an internal module as a wakeup source input. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 679: Llwu Module Dma Enable Register (Llwu_De)
Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4006_1000h base + 1Ch offset = 4006_101Ch Reset Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 680 DMA Wakeup Enable For Module 0 WUDE0 Enables an internal module as a DMA wakeup source. Internal module request not used as a DMA wakeup source Internal module request used as a DMA wakeup source K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 681: Llwu Pin Flag Register (Llwu_Pf)
Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF31. LLWU_P31 input was not a wakeup source LLWU_P31 input was a wakeup source Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 682 WUF24. LLWU_P24 input was not a wakeup source LLWU_P24 input was a wakeup source Wakeup Flag For LLWU_P23 WUF23 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 683 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF16. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 684 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF9. LLWU_P9 input was not a wakeup source LLWU_P9 input was a wakeup source Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 685 WUF2. LLWU_P2 input was not a wakeup source LLWU_P2 input was a wakeup source Wakeup Flag For LLWU_P1 WUF1 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 686: Llwu Module Interrupt Flag Register (Llwu_Mf)
Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4006_1000h base + 28h offset = 4006_1028h Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 687 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 688: Llwu Pin Filter Register (Llwu_Filt)
Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4006_1000h base + 30h offset = 4006_1030h FILTE4 FILTSEL4 FILTE3 FILTSEL3 Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 689 Filter negedge detect enabled Filter any edge detect enabled 20–16 Filter 3 Pin Select FILTSEL3 Selects 1 of the wakeup pins to be muxed into filter 3. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 690 Filter any edge detect enabled FILTSEL1 Filter 1 Pin Select Selects 1 of the wakeup pins to be muxed into filter 1. 00000 Select LLWU_P0 for filter 11111 Select LLWU_P31 for filter K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 691: Functional Description
Wakeup events triggered from an internal module DMA request, result in a temporary wake-up from LLS with CPU remaining clock gated to allow the DMA request to be serviced. After the DMA request to the LLWU negates, the system will re-enter LLS mode. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 692: Vlls Modes
LLWU flag from being falsely set when PMC_REGSC[ACKISO] is cleared. The signal selected as a wake-up source pin must be a digital pin, as selected in the pin mux control. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 693: Low Power Inter-Integrated Circuit (Lpi2C)
• General call, 7-bit and 10-bit addressing. • Software reset, START byte and Device ID require software support. The LPI2C master supports the following features: • Command/transmit FIFO of 4 words. • Receive FIFO of 4 words. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 694 • Software controllable ACK or NACK, with optional clock stretching on ACK/ NACK bit. • Configurable clock stretching to avoid transmit FIFO underrun and receive FIFO overrun. • Flag and optional interrupt at end of packet, STOP condition or bit error detection. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 695: Block Diagram
Configuration Registers Bus Clock External Clock Functional Clock Clock Domains Figure 27-1. LPI2C block diagram 27.1.4 Modes of operation The LPI2C module supports the chip modes described in the following table. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 696 (in bits) page (hex) 4004_2000 Version ID Register (LPI2C2_VERID) See section 27.2.1/700 4004_2004 Parameter Register (LPI2C2_PARAM) See section 27.2.2/701 4004_2010 Master Control Register (LPI2C2_MCR) 0000_0000h 27.2.3/702 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 697 0000_0000h 27.2.25/ 4004_2150 Slave Address Status Register (LPI2C2_SASR) 0000_4000h 27.2.26/ 4004_2154 Slave Transmit ACK Register (LPI2C2_STAR) 0000_0000h 27.2.27/ 4004_2160 Slave Transmit Data Register (LPI2C2_STDR) 0000_0000h Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 698 0000_0000h 27.2.23/ 400C_0128 Slave Configuration Register 2 (LPI2C0_SCFGR2) 0000_0000h 27.2.24/ 400C_0140 Slave Address Match Register (LPI2C0_SAMR) 0000_0000h 27.2.25/ 400C_0150 Slave Address Status Register (LPI2C0_SASR) 0000_4000h Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 699 0000_0000h 27.2.21/ 400C_111C Slave DMA Enable Register (LPI2C1_SDER) 0000_0000h 27.2.22/ 400C_1124 Slave Configuration Register 1 (LPI2C1_SCFGR1) 0000_0000h 27.2.23/ 400C_1128 Slave Configuration Register 2 (LPI2C1_SCFGR2) 0000_0000h Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 700 This read only field returns the minor version number for the specification. FEATURE Feature Specification Number This read only field returns the feature set number. 0x0002 Master only with standard feature set. 0x0003 Master and slave with standard feature set. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 701 This field is reserved. Reserved This read-only field is reserved and always has the value 0. MTXFIFO Master Transmit FIFO Size The number of words in the master transmit FIFO is 2^MTXFIFO. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 702 DBGEN Master is disabled in debug mode. Master is enabled in debug mode. Doze mode enable DOZEN Enables or disables Doze mode for the master. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 703 I2C Master is idle. I2C Master is busy. 23–15 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Data Match Flag Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 704 START condition. Master has not generated a STOP or Repeated START condition. Master has generated a STOP or Repeated START condition. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 705 This read-only field is reserved and always has the value 0. Data Match Interrupt Enable DMIE Interrupt disabled. Interrupt enabled. Pin Low Timeout Interrupt Enable PLTIE Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 706 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Receive Data Interrupt Enable RDIE Interrupt disabled. Interrupt enabled. Transmit Data Interrupt Enable TDIE Interrupt disabled. Interrupt enabled K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 707 This read-only field is reserved and always has the value 0. Receive Data DMA Enable RDDE DMA request disabled. DMA request enabled. Transmit Data DMA Enable TDDE DMA request disabled. DMA request enabled K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 708 HRSEL Selects the source of the host request input. Host request input is pin LPI2C_HREQ. Host request input is input trigger. Host Request Polarity HRPOL Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 709 LPI2C configured for 2-pin output only mode (ultra-fast mode). LPI2C configured for 2-pin push-pull mode. LPI2C configured for 4-pin push-pull mode. LPI2C configured for 2-pin open drain mode with separate LPI2C slave. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 710 Configures the clock prescaler used for all LPI2C master logic, except the digital glitch filters. Divide by 1. Divide by 2. Divide by 4. Divide by 8. Divide by 16. Divide by 32. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 711 Configures the bus idle timeout period in clock cycles. If both SCL and SDA are high for longer than BUSIDLE cycles, then the I2C bus is assumed to be idle and the master can generate a START condition. When set to zero, this feature is disabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 712 This field is reserved. Reserved This read-only field is reserved and always has the value 0. MATCH0 Match 0 Value Compared against the received data when receive data match is enabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 713 Minimum number of cycles (minus one) that the SCL clock is driven low by the master. This value is also used for the minimum bus free time between a STOP and a START condition. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 714 Minimum number of cycles (minus one) that the SCL clock is driven low by the master. This value is also used for the minimum bus free time between a STOP and a START condition. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 715 Returns the number of words in the receive FIFO. 15–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. TXCOUNT Transmit FIFO Count Returns the number of words in the transmit FIFO. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 716 Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned. DATA Transmit Data Performing an 8-bit write to DATA will zero extend the CMD field. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 717 Reading this register returns the data received by the I2C master that has not been discarded. Receive data can be discarded due to the CMD field or the master can be configured to discard non-matching data. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 718 Filter is disabled in Doze mode. Filter Enable FILTEN Disable digital filter and output delay counter for slave mode. Enable digital filter and output delay counter for slave mode. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 719 LPI2Cx_SSR field descriptions Field Description 31–26 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Bus Busy Flag Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 720 (repeated) START condition. Slave has not detected a bit error. Slave has detected a bit error. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 721 This flag is cleared by writing the transmit data register. When TXCFG is clear, it is also cleared if a NACK or Repeated START or STOP condition is detected. Transmit data not requested. Transmit data is requested. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 722 Interrupt disabled. FIFO Error Interrupt Enable FEIE Interrupt disabled. Interrupt enabled. Bit Error Interrupt Enable BEIE Interrupt disabled. Interrupt enabled. STOP Detect Interrupt Enable SDIE Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 723 Receive Data Interrupt Enable RDIE Interrupt disabled. Interrupt enabled. Transmit Data Interrupt Enable TDIE Interrupt disabled. Interrupt enabled 27.2.21 Slave DMA Enable Register (LPI2Cx_SDER) Address: Base address + 11Ch offset Reset Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 724 LPI2Cx_SCFGR1 field descriptions Field Description 31–19 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 18–16 Address Configuration ADDRCFG Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 725 Transmit Data Flag will only assert during a slave-transmit transfer when the transmit data register is empty. Transmit Data Flag will assert whenever the transmit data register is empty. SMBus Alert Enable SAEN Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 726 Clock stretching enabled. 27.2.23 Slave Configuration Register 2 (LPI2Cx_SCFGR2) The SCFGR2 should only be written when the I2C Slave is disabled. Address: Base address + 128h offset FILTSDA FILTSCL DATAVD CLKHOLD Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 727 CLKHOLD+3 cycles. The I2C slave clock hold time is not affected by the PRESCALE configuration, and is disabled in high speed mode. 27.2.24 Slave Address Match Register (LPI2Cx_SAMR) Address: Base address + 140h offset ADDR1 Reset ADDR0 Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 728 RADDR updates whenever the AMF is set and the AMF is cleared by reading this register. In 7-bit mode, the address byte is store in RADDR[7:0]. In 10-bit mode, the first address byte is { 11110, RADDR[10:9], Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 729 Can also be written when LPI2C Slave is disabled or idle to configure the default ACK/NACK. Transmit ACK for received word. Transmit NACK for received word. 27.2.27 Slave Transmit Data Register (LPI2Cx_STDR) Address: Base address + 160h offset Reserved DATA Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 730 Indicates this is not the first data word since a (repeated) START or STOP condition. Indicates this is the first data word since a (repeated) START or STOP condition. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 731 LPI2C functional clock is disabled. Note that the LPI2C slave digital filter must be disabled if the LPI2C functional clock is disabled and this can effect compliance with some of the timing parameters of the I2C specification, such as the data hold time. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 732 I2C bus. 27.3.2.1 Transmit and Command FIFO The transmit FIFO stores command data to initiate the various I2C operations. The following operations can be initiated through commands in the transmit FIFO: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 733 • Perform master-transmit or master-receive transfers, as configured by the transmit FIFO. • Transmit a Repeated START or STOP condition as configured by the transmit FIFO and/or MCFGR1[AUTOSTOP]. A repeated START can change which timing configuration register is used. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 734 STOP condition. The LPI2C master timing parameters in LPI2C functional clock cycles are configured as follows. They must be configured to meet the I2C timing specification for the required mode. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 735 [CLKLO × (2 ^ PRESCALER)] FILTSDA FILTSCL [CLKLO × (2 ^ PRESCALER)] Does not apply if compensating for board level skew between SCL and SDA. BUSIDLE (CLKLO+SETHOLD+2) × 2 Must also be greater than CLKHI+1. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 736 MSR[NDF]). • NACK detected and expecting ACK for address byte, provided MCFGR1[IGNACK] is clear (sets MSR[NDF]). • ACK detected and expecting NACK for address byte, provided MCFGR1[IGNACK] is clear (sets MSR[NDF]). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 737 I2C bus to external level shifters. The LPI2C master logic and LPI2C slave logic are not able to connect to separate I2C buses when using this configuration. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 738 • During 9th clock pulse of address byte and address valid flag is set. • During 9th clock pulse of slave-transmit transfer and transmit data flag is set. • During 9th clock pulse of slave-receive transfer and receive data flag is set. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 739 • FIFO error flag will also set due to an address overrun when RXCFG is set, otherwise an address overrun is not flagged. Clock stretching can be enabled to eliminate the possibility of overrun occurring. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 740 ACK during address byte and expecting NACK, or master detected NACK during master- transmitter data byte. Master lost arbitration due to START/STOP condition detected at Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 741 Flag Description Interrupt DMA Request Low Power Wakeup Data can be written to transmit data register. Data can be read from the receive data register. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 742 SMBus alert address. LPI2C slave is busy receiving address byte or transmitting/receiving data. LPI2C slave is enabled and START condition detected on I2C bus, but STOP condition has not been detected. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 743 The LPI2C input trigger can be selected in place of the LPI2C_HREQ pin to control the start of a LPI2C master bus transfer. The input trigger must assert for longer than one LPI2C functional clock cycle to be detected. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 744 Functional description K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 745 (for example, frequency measurements). The timer channels operate on an asynchronous clock, which is independent from the register read/write access clock. Clock synchronization between the clock domains ensures normal operations. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 746 The Doze Enable (MCR[DOZE_EN]) bit is ignored and the LPIT will be disabled for the duration of low leakage mode. Debug Can continue operating provided the Debug Enable bit (MCR[DBG_EN]) is set. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 747 Current Timer Value (LPIT0_CVAL2) FFFF_FFFFh 28.3.9/756 28.3.10/ 4003_0048 Timer Control Register (LPIT0_TCTRL2) 0000_0000h 4003_0050 Timer Value Register (LPIT0_TVAL3) 0000_0000h 28.3.8/755 4003_0054 Current Timer Value (LPIT0_CVAL3) FFFF_FFFFh 28.3.9/756 28.3.10/ 4003_0058 Timer Control Register (LPIT0_TCTRL3) 0000_0000h K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 748 This read-only field is reserved and always has the value 0. 15–8 Number of External Trigger Inputs EXT_TRIG Number of external triggers implemented. CHANNEL Number of Timer Channels Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 749 Resets all channels and registers, except the Module Control Register. Remains set until cleared by software. Timer channels and registers are not reset Timer channels and registers are reset Module Clock Enable M_CEN Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 750 In compare modes, sets to 1 at the end of the timer period. In capture modes, sets to 1 when the trigger asserts. Writing logic 1 to this flag clears it. Writing 0 has no effect. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 751 Enables interrupt generation when this bit is set to 1 and if corresponding Timer Interrupt Flag is asserted. Interrupt generation is disabled Interrupt generation is enabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 752 Writing a 0 will not disable the counter. This bit will be cleared when T_EN bit in TCTRL3 is set to '0' or '1' is written to the CLR_T_EN_3 bit in CLRTEN register. No effect Enables the Timer Channel 3 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 753 Writing a 0 will not disable the counter. This bit will be cleared when T_EN bit in TCTRL0 is set to 0 or '1' is written to the CLR_T_EN_0 bit in CLRTEN register. No effect Enables the Timer Channel 0 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 754 TCTRL2 register. Writing a 1 will not enable the counter. This bit is self clearing and will always read 0. No Action Clear T_EN bit for Timer Channel 2 Clear Timer 1 Enable CLR_T_EN_1 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 755 In capture modes, this register stores the inverse of the counter whenever the trigger asserts. Invalid load value in compare modes >0 Value to be loaded (Compare Mode) or Value of Timer (Capture Mode) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 756 These registers contain the control bits for each timer channel Address: 4003_0000h base + 28h offset + (16d × i), where i=0d to 3d TRG_ TRG_SEL TROT TSOI TSOT Reset MODE T_EN Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 757 Timer starts to decrement when rising edge on selected trigger is detected 15–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 758 M_CEN bit value. Reads to these registers can happen irrespective of M_CEN bit value. • Wait for 4 protocol clock cycles to allow time for clock synchronization and reset de- assertion. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 759 The timer operation is further controlled by Trigger Control bits (TSOT, TSOI, TROT) which control the timer load, reload, start and restart of the timers. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 760 TROT & TSOT bits have no effect on timer operation. • In 32-bit Input Trigger Capture mode, TSOI and TROT bits control the timer function. TSOT bit has no effect on timer operation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 761 (MODE bits). The TSOT bit does not have any effect if the channel timer (Channel 'n') is chained to previous channel's timer (Channel 'n-1'). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 762 Functional description K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 763 • Word size = 32 bits • Command/transmit FIFO of 4 words. • Receive FIFO of 4 words. • Host request input can be used to control the start time of an SPI bus transfer. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 764 LPSPI acknowledges entry into low leakage mode. Debug (the core is in Debug/Halted Can continue operating if the Debug Enable bit (CR[DBGEN]) is set. mode) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 765 Status Register (LPSPI2_SR) 0000_0001h 29.2.4/770 4003_E018 Interrupt Enable Register (LPSPI2_IER) 0000_0000h 29.2.5/772 4003_E01C DMA Enable Register (LPSPI2_DER) 0000_0000h 29.2.6/773 4003_E020 Configuration Register 0 (LPSPI2_CFGR0) 0000_0000h 29.2.7/774 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 766 400B_C05C FIFO Status Register (LPSPI0_FSR) 0000_0000h 29.2.14/ 400B_C060 Transmit Command Register (LPSPI0_TCR) 0000_001Fh 29.2.15/ 400B_C064 Transmit Data Register (LPSPI0_TDR) 0000_0000h 29.2.16/ 400B_C070 Receive Status Register (LPSPI0_RSR) 0000_0002h 29.2.17/ 400B_C074 Receive Data Register (LPSPI0_RDR) 0000_0000h K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 767 29.2.1 Version ID Register (LPSPIx_VERID) Address: Base address + 0h offset MAJOR MINOR FEATURE Reset LPSPIx_VERID field descriptions Field Description 31–24 Major Version Number MAJOR Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 768 This read-only field is reserved and always has the value 0. 15–8 Receive FIFO Size RXFIFO The number of words in the receive FIFO is 2^RXFIFO. TXFIFO Transmit FIFO Size The number of words in the transmit FIFO is 2^TXFIFO. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 769 This read-only field is reserved and always has the value 0. Debug Enable DBGEN Module is disabled in debug mode. Module is enabled in debug mode. Doze mode enable DOZEN Enables or disables Doze mode Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 770 Indicates that the received data has matched the MATCH0 and/or MATCH1 fields as configured by MATCFG. Have not received matching data. Have received matching data. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 771 Transmit Data Flag The Transmit Data Flag is set whenever the number of words in the transmit FIFO is equal or less than TXWATER. Transmit data not requested. Transmit data is requested. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 772 This read-only field is reserved and always has the value 0. Receive Data Interrupt Enable RDIE Interrupt disabled. Interrupt enabled. Transmit Data Interrupt Enable TDIE Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 773 This read-only field is reserved and always has the value 0. Receive Data DMA Enable RDDE DMA request disabled. DMA request enabled. Transmit Data DMA Enable TDDE DMA request disabled. DMA request enabled K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 774 Selects the source of the host request input. When the host request function is enabled with the LPSPI_HREQ pin, the LPSPI_PCS[1] function is disabled. Host request input is pin LPSPI_HREQ. Host request input is input trigger. Host Request Polarity HRPOL Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 775 PCSCFG must be set if performing 4-bit transfers. PCS[3:2] are enabled. PCS[3:2] are disabled. Output Config OUTCFG Configures if the output data is tristated between accesses (LPSPI_PCS is negated). Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 776 CPHA=1. When this bit is set, the SCK must remain idle for at least 4 LPSPI functional clock cycles (divided by PRESCALE configuration) between each word to ensure correct operation. This bit is ignored in master mode. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 777 Compared against the received data when receive data match is enabled. 29.2.10 Data Match Register 1 (LPSPIx_DMR1) Address: Base address + 34h offset MATCH1 Reset LPSPIx_DMR1 field descriptions Field Description MATCH1 Match 1 Value K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 778 LPSPI functional clock divided by the PRESCALE configuration, and the minimum period is 2 cycles. If the period is an odd number of cycles, then the first half of the period will be one cycle longer than the second half of the period. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 779 Returns the number of words in the receive FIFO. 15–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. TXCOUNT Transmit FIFO Count Returns the number of words in the transmit FIFO. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 780 Address: Base address + 60h offset PRESCALE LSBF WIDTH Reset FRAMESZ Reset LPSPIx_TCR field descriptions Field Description Clock Polarity CPOL This field is only updated between frames. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 781 In slave mode, when continuous transfer is enabled the LPSPI will only transmit the first FRAMESZ bits, after which it will transmit received data assuming a 32-bit shift register. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 782 FIFO and store of the receive FIFO will contain the remainder bits (e.g.: a 72-bit transfer will load/store 32- bits from the FIFO and then another 32-bits from the FIFO and then the final 8-bits from the FIFO). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 783 Reset LPSPIx_TDR field descriptions Field Description DATA Transmit Data Both 8-bit and 16-bit writes of transmit data will zero extend the data written and push the data into the transmit FIFO. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 784 RX FIFO is empty. Start Of Frame Indicates that this is the first data word received after LPSPI_PCS assertion. Subsequent data word received after LPSPI_PCS assertion. First data word received after LPSPI_PCS assertion. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 785 The LPSPI shift register is clocked directly by the external pins. This allows the LPSPI slave to remain operational in low power modes, even when the LPSPI functional clock is disabled, although this is limited to a single word transfer. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 786 • If the LPSPI is busy and either the existing CONT bit is clear or the new CONTC value is clear, the SPI frame will complete at the end of the existing word, ignoring K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 787 Enables byte swap on each 32-bit word when transmitting and receiving data. Can be useful when interfacing to devices that organize data as big endean. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 788 HREQ pin is asserted (or disabled) and the LPSPI is enabled. The SPI bus transfer uses the attributes configured in the transmit command register and timing parameters from the clock configuration register to perform the transfer. The SPI bus transfer ends once K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 789 PRESCALE configuration. Although the Clock Configuration Register cannot be changed when the LPSPI is busy, the PRESCALE configuration can be altered between transfers using the command register, to support interfacing to different slave devices at different frequencies. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 790 When configuring for half-duplex transfers using the same data pin in single bit transfer mode, or any transfer in 2-bit and 4-bit transfer modes, then the output data pins must be configured to tristate when LPSPI_PCS is negated. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 791 Single bit transfers support traditional SPI bus transfers in either half-duplex or full-duplex data formats. Two and four bit transfers are useful for interfacing to QuadSPI memory Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 792 AUTOPCS is set, a minimum of four LPSPI functional clock cycles (divided by PRESCALE configuration) is required between the last LPSPI_SCK edge of one word and the first LPSPI_SCK edge of the next word. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 793 This bit cannot set in master mode when NOSTALL is clear. Data match flag, received data has matched the configured data match value. LPSPI is busy performing a SPI bus transfer. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 794 The LPSPI input trigger can be selected in place of the LPSPI_HREQ input to control the start of a LPSPI bus transfer. The input trigger must assert for longer than one LPSPI functional clock cycle to be detected. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 795 • Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter • Rising-edge or falling-edge 30.1.2 Modes of operation The following table describes the operation of the LPTMR module in various modes. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 796 Deassertion—If configured for pulse counter mode with active-low input, then deassertion causes the CNR to increment. Timing Assertion or deassertion may occur at any time; input may assert asynchronously to the bus clock. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 797 When TDRE is set, the LPTMR DMA Request is generated whenever TCF is also set and the TCF is cleared when the DMA Controller is done. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 798 When TEN is clear, it resets the LPTMR internal logic, including the CNR and TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field, CSR[5:1] must not be altered. LPTMR is disabled and internal logic is reset. LPTMR is enabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 799 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 800 CNR increments. If the CMR is 0, the hardware trigger will remain asserted until the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only when TCF is set. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 801 LPTMR is enabled. NOTE The clock source selected may need to be configured to remain enabled in low-power modes, otherwise the LPTMR will not operate during low-power modes. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 802 In Time Counter mode, when the prescaler is bypassed, the selected prescaler clock increments the CNR on every clock cycle. When the LPTMR is enabled, the first increment will take an additional one or two prescaler clock cycles due to synchronization logic. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 803 When the LPTMR is enabled, the CMR can be altered only when CSR[TCF] is set. When updating the CMR, the CMR must be written and CSR[TCF] must be cleared before the LPTMR counter has incremented past the new LPTMR compare value. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 804 The LPTMR interrupt is generated whenever CSR[TIE] and CSR[TCF] are set. CSR[TCF] is cleared by disabling the LPTMR or by writing a logic 1 to it. CSR[TIE] can be altered and CSR[TCF] can be cleared while the LPTMR is enabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 805 The LPTMR interrupt is generated asynchronously to the system clock and can be used to generate a wakeup from any low-power mode, including the low-leakage modes, provided the LPTMR is enabled as a wakeup source. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 806 Functional description K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 807 • Programmable 1-bit or 2-bit stop bits • Three receiver wakeup methods: • Idle line wakeup • Address mark wakeup • Receive data match • Automatic address matching to reduce ISR overhead: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 808 The LPUART can be configured to Stop in Wait modes, when the DOZEEN bit is set. The transmitter and receiver will finish transmitting/receiving the current word. 31.1.2.3 Debug mode The LPUART remains functional in debug mode. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 809 LPUART_RX Receive data. LPUART_CTS Clear to send. LPUART_RTS Request to send. 31.1.4 Block diagram The following figure shows the transmitter portion of the LPUART. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 810 TO TxD Transmit Control Pin Logic TxD Direction TXDIR BRK13 TDRE Tx Interrupt Request TCIE Figure 31-1. LPUART transmitter block diagram The following figure shows the receiver portion of the LPUART. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 811 LPUART Status Register (LPUART2_STAT) 00C0_0000h 31.2.6/818 4004_6018 LPUART Control Register (LPUART2_CTRL) 0000_0000h 31.2.7/822 4004_601C LPUART Data Register (LPUART2_DATA) 0000_1000h 31.2.8/827 4004_6020 LPUART Match Address Register (LPUART2_MATCH) 0000_0000h 31.2.9/829 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 812 400C_5020 LPUART Match Address Register (LPUART1_MATCH) 0000_0000h 31.2.9/829 31.2.10/ 400C_5024 LPUART Modem IrDA Register (LPUART1_MODIR) 0000_0000h 31.2.11/ 400C_5028 LPUART FIFO Register (LPUART1_FIFO) See section 31.2.12/ 400C_502C LPUART Watermark Register (LPUART1_WATER) 0000_0000h K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 813 This read-only field is reserved and always has the value 0. 15–8 Receive FIFO Size RXFIFO The number of words in the receive FIFO is 2^RXFIFO. TXFIFO Transmit FIFO Size The number of words in the transmit FIFO is 2^TXFIFO. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 814 LPUARTx_PINCFG field descriptions Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. TRGSEL Trigger Select Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 815 Receiver and transmitter use 8-bit or 9-bit data characters. Receiver and transmitter use 10-bit data characters. 28–24 Oversampling Ratio Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 816 LBKDIE enables the LIN break detect flag, LBKDIF, to generate interrupt requests. Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling). Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 817 "baud clock / ((OSR+1) × SBR)". The 13-bit baud rate setting [SBR12:SBR0] must only be updated when the transmitter and receiver are both disabled (LPUART_CTRL[RE] and LPUART_CTRL[TE] are both 0). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 818 RXINV=1, on the LPUART_RX pin occurs. RXEDGIF is cleared by writing a 1 to it. No active edge on the receive pin has occurred. An active edge on the receive pin has occurred. MSB First MSBF Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 819 RAF is set when the receiver detects the beginning of a valid start bit, and RAF is cleared automatically when the receiver detects an idle line. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 820 . IDLE is set only once even if the receive line remains idle for an extended period. No idle line detected. Idle line was detected. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 821 MA2F. Received data is not equal to MA2 Received data is equal to MA2 Reserved This field is reserved. This read-only field is reserved and always has the value 0. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 822 (if any) before the receiver starts receiving data from the LPUART_TX pin. LPUART_TX pin is an input in single-wire mode. LPUART_TX pin is an output in single-wire mode. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 823 Hardware interrupt requested when TC flag is 1. Receiver Interrupt Enable Enables STAT[RDRF] to generate interrupt requests. Hardware interrupts from RDRF disabled; use polling. Hardware interrupt requested when RDRF flag is 1. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 824 Queue break character(s) to be sent. Match 1 Interrupt Enable MA1IE MA1F interrupt disabled MA1F interrupt enabled Match 2 Interrupt Enable MA2IE MA2F interrupt disabled MA2F interrupt enabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 825 • Address mark in the most significant bit position of a received data character, or • An idle condition on the receive pin input signal. Configures RWU for idle-line wakeup. Configures RWU with address-mark wakeup. Idle Line Type Select Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 826 1s in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including the parity bit, is even. Even parity. Odd parity. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 827 The dataword was received without noise. The data was received with noise. The current received dataword contained in DATA[R9:R0] was received with a parity error. PARITYE Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 828 Read receive data buffer 2 or write transmit data buffer 2. R2T2 Read receive data buffer 1 or write transmit data buffer 1. R1T1 Read receive data buffer 0 or write transmit data buffer 0. R0T0 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 829 BAUD[MAEN] bit is clear. 31.2.10 LPUART Modem IrDA Register (LPUARTx_MODIR) The MODEM register controls options for setting the modem configuration. Address: Base address + 24h offset IREN Reset RTSWATER Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 830 Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the polarity of the receiver RTS. RTS will remain negated in the active low state unless TXRTSE is set. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 831 If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 832 Asserts when there is no data in the Transmit FIFO/buffer. This field does not take into account data that is in the transmit shift register. Transmit buffer is not empty. Transmit buffer is empty. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 833 Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 834 Receive FIFO. Buffer Depth The maximum number of receive datawords that can be stored in the receive buffer before an overrun occurs. This field is read only. Receive FIFO/Buffer depth = 4 datawords. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 835 The transmitter and receiver operate independently, although they use the same baud rate generator. The following describes each of the blocks of the LPUART. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 836 The transmitter then remains idle until data is available in the transmit data buffer. Programs store data into the transmit data buffer by writing to the LPUART data register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 837 Normally, a program would wait for LPUART_STAT[TDRE] to become set to indicate the last character of a message has moved to the transmit shifter, then write 0 and then write 1 to the LPUART_CTRL[TE] K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 838 If the clear-to-send operation is disabled, the transmitter ignores the state of CTS. The transmitter's CTS signal can also be enabled even if the same LPUART receiver's RTS signal is disabled. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 839 A pullup can pull LPUART_RX to a non-floating value during this time. This option can be refined further by operating the LPUART in single wire mode, freeing the LPUART_RX pin for other uses. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 840 0, the receiver assumes it is synchronized to a received character. If another falling edge is detected before the receiver is considered synchronized, the receiver restarts the sampling from the first segment. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 841 During receiver address matching, the address matching is performed in hardware and the LPUART receiver will ignore all characters that do not meet the address match requirements. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 842 LPUART_STAT[RDRF] flag and generates an interrupt if enabled. When LPUART_STAT[RWUID] is one, any idle condition sets the LPUART_STAT[IDLE] flag and generates an interrupt if enabled, regardless of whether LPUART_CTRL[RWU] is zero or one. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 843 If both the LPUART_BAUD[MAEN1] and LPUART_BAUD[MAEN2] bits are negated, the receiver operates normally and all data received is transferred to the receive data buffer. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 844 LPUART_RX pin that matches MATCH[MA1] is received and transferred to the receive buffer, and LPUART_STAT[RDRF] is set. All subsequent characters are considered to be data and are also transferred to the receive K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 845 When STAT[RXINV] is cleared, the first falling edge of the received character corresponds to the start bit. The infrared decoder resets its counter. At this time, the receiver also begins its start bit detection process. After the start bit is detected, the K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 846 LPUART_CTRL[T8] and LPUART_CTRL[T9]. For the receiver, these bits are held in LPUART_CTRL[R8] and LPUART_CTRL[R9]. They are also accessible via 16-bit or 32-bit accesses to the LPUART_DATA register. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 847 When LPUART_CTRL[LOOPS] is set, the LPUART_CTRL[RSRC] bit in the same register chooses between loop mode (LPUART_CTRL[RSRC] = 0) or single-wire mode (LPUART_CTRL[RSRC] = 1). Loop mode is sometimes used to check software, K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 848 The infrared submodule receives its clock sources from the LPUART. One of these two clocks are selected in the infrared submodule to generate either 1/OSR, 2/OSR, 3/OSR, or 4/OSR narrow pulses during transmission. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 849 When a program detects that the receive data register is full (LPUART_STAT[RDRF] = 1), it gets the data from the receive data register by reading LPUART_DATA. The LPUART_STAT[RDRF] flag is cleared by reading LPUART_DATA. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 850 At any time, an active edge on the LPUART_RX serial data input pin causes the LPUART_STAT[RXEDGIF] flag to set. The LPUART_STAT[RXEDGIF] flag is cleared by writing a 1 to it. This function depends on the receiver being enabled (LPUART_CTRL[RE] = 1). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 851 • Supports 32-bit unsigned square root calculations • Simple programming model includes input data and result registers plus a control/ status register • Programming model interface optimized for activation from inline code or software library call K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 852 -Lite Peripherals Alt-Master PBRIDGE DMA_4ch Array Figure 32-1. Generic Cortex-M0+ Core Platform Block Diagram Next, a block diagram of the internal structure of the MMDVSQ module is presented. See Figure 32-2. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 853 MMDVSQ is only clocked when responding to bus requests to its programming model or is busy performing a calculation. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 854 Input dividend (numerator) for the divide Divisor (MMDVSQ_DSOR) Input divisor (denominator) for the divide Control/Status (MMDVSQ_CSR) Control for divide, status for divide and square root Result (MMDVSQ_RES) Output result Radicand (MMDVSQ_RCND) Input "square" data K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 855 If CSR[DFS] = 0, a write to this register inititates a divide operation. Any memory access (read or write) of the DSOR register while the module is busy during a calculation causes the access to be stalled (using wait states) until the calculation completes. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 856 Reset * Notes: • x = Undefined at reset. MMDVSQx_DSOR field descriptions Field Description DIVISOR Divisor This is the input divisor operand for divide calculations. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 857 This read-only bit is asserted when the MMDVSQ is performing a divide or square root. When an operation is initiated, the hardware sets this flag. It remains asserted until the operation completes and the Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 858 This indicator configures the MMDVSQ’s response to divide-by-zero calculations. If both CSR[DZ] and CSR[DZE] are set, then a subsequent read of the RES register is error terminated to signal the processor of the attempted divide-by-zero. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 859 CSR[DFS] = 0, it is ignored. This bit always reads as a zero. The state of the register write data defines this bit’s function. No operation initiated If CSR[DFS] = 1, then initiate a divide calculation, else ignore K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 860 Reset * Notes: • x = Undefined at reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 861 Arm Cortex-Mx definition and returns 0x8000_0000 (the lower 32 bits of the +2 result) as the quotient with no indication of the overflow condition. If the remainder is selected as the output of this calculation, it returns 0x0000_0000. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 862 32.4.1.2.2 Square root using Q notation Consider the use of Q notation for square root calculations returning fractional values. The following description is taken from http://en.wikipedia.org/wiki/Q_(number_format). K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 863 Q number left justified in the machine word. For a given Qm.n format, using an m+n+1 bit signed integer container with n fractional bits: • its range is [-2 • its resolution is 2 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 864 Stated differently, it represents the time CSR[BUSY] is asserted for a given calculation. In the following two tables, “x” signals a bit with a don’t care value. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 865 Table 32-5. Square Root Execution Times RCND[31:0] Execution Time with CSR[BUSY] = 1 [cycles] (01,1x)xx_xxxx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 00(01,1x)_xxxx_xxxx_xxxx_x_xxx_xxxx_xxxx_xxxx 0000_(01,1x)xx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 0000_00(01,1x)_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 0000_0000_(01,1x)xx_xxxx__xxxx_xxxx_xxxx_xxxx 0000_0000_00(01,1x)_xxxx__xxxx_xxxx_xxxx_xxxx 0000_0000_0000_(01,1x)xx__xxxx_xxxx_xxxx_xxxx 0000_0000_0000_00(01,1x)__xxxx_xxxx_xxxx_xxxx 0000_0000_0000_0000__(01,1x)xx_xxxx_xxxx_xxxx 0000_0000_0000_0000__00(01,1x)_xxxx_xxxx_xxxx 0000_0000_0000_0000__0000_(01,1x)xx_xxxx_xxxx 0000_0000_0000_0000__0000_00(01,1x)_xxxx_xxxx 0000_0000_0000_0000__0000_0000_(01,1x)xx_xxxx 0000_0000_0000_0000__0000_0000_00(01,1x)_xxxx 0000_0000_0000_0000__0000_0000_0000_(01,1x)xx 0000_0000_0000_0000__0000_0000_0000_00(01,1x) 0000_0000_0000_0000__0000_0000_0000_0000 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 866 (CSR[DZE] = 1), then a read of the RES register is error terminated. To avoid a zero-divide error termination during a context save, the following sequence can be used: 1. Read DEND, DSOR, and CSR registers and save the values as part of the task state. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 867 2. Reload DEND, DSOR, CSR, and RES registers from the saved state. Since the original context save of the control/status register is guaranteed to have CSR[SRT] = 0, there is no divide operation initiated when this register is reloaded in step K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 868 Integer square root K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 869 MCM memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Crossbar Switch (AXBS) Slave Configuration F000_3010 000Fh 33.2.1/870 (MCM0_PLASC) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 870 Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. A bus slave connection to AXBS input port n is absent. A bus slave connection to AXBS input port n is present. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 871 DFCS EFDS Description Speculation buffer is on for instruction and off for data. Speculation buffer is on for instruction and on for data. Speculation buffer is off. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 872 Cache is off. Address: F000_3008h base + Ch offset = F000_3014h ESFC Reset EFDS Reset * Notes: • MMCAU field: Reset value loaded during reset from Flash IFR. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 873 Writing a 1 to this field clears the cache. Writing a 0 to this field is ignored. This field always reads as 0. Arbitration select Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 874 This read-only field is reserved and always has the value 0. 33.2.4 Compute Operation Control Register (MCMx_CPO) This register controls the Compute Operation. Address: F000_3008h base + 40h offset = F000_3048h Reset Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 875 • ISCR[ETBN] is set, when • The ETB counter is enabled, ETBCC[CNTEN] = 1 • The ETB count expires • The response to counter expiration is an NMI, MCM_ETBCC[RSPT] = 10 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 876 • ISCR[ETBI] is set, when • The ETB counter is enabled, ETBCC[CNTEN] = 1 • The ETB count expires • The response to counter expiration is a normal interrupt, ETBCC[RSPT] = 01 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 877 Miscellaneous System Control Module (MSCM). It specifically includes multiple views of the processor configuration; one view that is available generically to the core, and other views that are available to any bus masters in the system. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 878 Processor 0 Type Register (MSCM_CP0TYPE) See section 34.4.7/883 4000_1024 Processor 0 Number Register (MSCM_CP0NUM) See section 34.4.8/884 4000_1028 Processor 0 Master Register (MSCM_CP0MASTER) See section 34.4.9/885 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 879 RYPZ field: See bit field description MSCM_CPxTYPE field descriptions Field Description 31–8 Processor x Personality PERSONALITY This read-only field defines the processor personality for CPx Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 880 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Processor x Number This zero-filled word defines the logical processor number for CPx CPN = 0 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 881 This read-only field is reserved and always has the value 0. Processor x Physical Port Number This read-only field defines the physical port number for the core. For the core, PPN = 0x00 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 882 The register provides information on the Level 1 caches (if present). NOTE Reset values for the 4 Processor X Configuration Registers: • MSCM_CPxCFG0 = 0x0000_0000 • MSCM_CPxCFG1 = 0x0000_0000 • MSCM_CPxCFG2 = 0x0001_0001 • MSCM_CPxCFG3 = 0x0000_0120 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 883 Arm’s rYpZ nomenclature. Address: 4000_1000h base + 20h offset = 4000_1020h PERSONALITY RYPZ Reset * Notes: • PERSONALITY field: See bit field description • RYPZ field: See bit field description K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 884 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Processor x Number This zero-filled word defines the logical processor number for CPx CPN = 0 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 885 This read-only field is reserved and always has the value 0. Processor x Physical Port Number This read-only field defines the physical port number for CPUx. For CPU0, PPN = 0x00 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 886 34.4.11 Processor 0 Configuration Register (MSCM_CP0CFGn) The register provides information on the Level 1 caches (if present). Address: 4000_1000h base + 30h offset + (4d × i), where i=0d to 3d ICSZ ICWY DCSZ DCWY Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 887 • Privileged writes from other bus masters are ignored. • Attempted user mode accesses or any access with a size other than 32 bits are terminated with an error. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 888 MSCM Memory Map/Register Definition Address: 4000_1000h base + 400h offset + (4d × i), where i=0d to 2d OCMSZ OCMW Reserved Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 889 25% of the address range, this bit is used. OCMEMn is a power-of-2 capacity. OCMEMn is not a power-of-2, with a capacity is 0.75 * OCMSZ. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 890 OCMEMn is a graphics RAM. Reserved OCMEMn is a ROM. Reserved Reserved Reserved Reserved OCMEM Memory Protection Unit. This field is reserved for this device. OCMPU Reserved This field is reserved. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 891 This document details the functionality of both the MTB_RAM and MTB_DWT capabilities. 35.1.1 Overview A generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers is shown as follows: K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 892 PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception entry. The processor can cause a trace packet to be generated for any instruction. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 893 For an exception return operation, two packets are generated: • The first packet has the: • Source address field set to the address of the instruction that causes the exception return, BX or POP. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 894 • Program trace information in RAM available to MCU's application code or external debugger • Program trace watchpoint configuration accessible by MCU's application code or debugger • Location and size of RAM trace buffer is configured by software K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 895 PC >> 1. ATOMIC Input Indicates the processor is performing non-instruction related activities. EDBGRQ Output Request for the processor to enter the Debug state, if enabled, and halt. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 896 MTB Master Register (MTB0_MASTER) See section 35.3.1.3/ F000_0008 MTB Flow Register (MTB0_FLOW) Undefined 35.3.1.4/ F000_000C MTB Base Register (MTB0_BASE) Undefined 35.3.1.5/ F000_0F00 Integration Mode Control Register (MTB0_MODECTRL) 0000_0000h Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 897 F000_0FF0 Component ID Register (MTB0_COMPID0) See section 35.3.1.15/ F000_0FF4 Component ID Register (MTB0_COMPID1) See section 35.3.1.15/ F000_0FF8 Component ID Register (MTB0_COMPID2) See section 35.3.1.15/ F000_0FFC Component ID Register (MTB0_COMPID3) See section K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 898 See the MTB_FLOW register description for more details. Address: F000_0000h base + 0h offset = F000_0000h POINTER Reset POINTER Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 899 If MTB_FLOW[WATERMARK] is used to stop tracing or to halt the processor, MTB_MASTER[MASK] must still be set to a value that prevents MTB_POSITION[POINTER] from wrapping before it reaches the MTB_FLOW[WATERMARK] value. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 900 1, then only privileged AHB read and write accesses to the RAM are permitted and user accesses are RAZ/WI. The HPROT[1] signal determines if an access is a user or privileged mode reference. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 901 Cortex-M0+ processor to enter the Debug state. To enter Debug state, the Cortex-M0+ processor might have to perform additional branch type operations. Therefore, the MTB_FLOW[WATERMARK] field must be set below the final entry in the trace buffer region. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 902 Cortex-M0+ processor by asserting the EDBGRQ signal. AUTOSTOP AUTOSTOP If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then MTB_MASTER[EN] is automatically set to 0. This stops tracing. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 903 It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + F00h offset = F000_0F00h MODECTRL Reset MTBx_MODECTRL field descriptions Field Description MODECTRL MODECTRL Hardwired to 0x0000_0000 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 904 0. It is hardwired to specific values used during the auto- discovery process by an external debug agent. Address: F000_0000h base + FA4h offset = F000_0FA4h TAGCLEAR Reset MTBx_TAGCLEAR field descriptions Field Description TAGCLEAR TAGCLEAR Hardwired to 0x0000_0000 K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 905 Where functionality changes on a given security level, this change must be reported in this register. It is connected to specific signals used during the auto-discovery process by an external debug agent. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 906 This register indicates the device architecture. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FBCh offset = F000_0FBCh DEVICEARCH Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 907 This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FCCh offset = F000_0FCCh DEVICETYPID Reset MTBx_DEVICETYPID field descriptions Field Description DEVICETYPID DEVICETYPID Hardwired to 0x0000_0031. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 908 Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. 35.3.2 MTB_DWT Memory Map The MTB_DWT programming model supports a very simplified subset of the v7M debug architecture and follows the standard Arm DWT definition. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 909 F000_1FF0 Component ID Register (MTB0_DWT_COMPID0) See section 35.3.2.10/ F000_1FF4 Component ID Register (MTB0_DWT_COMPID1) See section 35.3.2.10/ F000_1FF8 Component ID Register (MTB0_DWT_COMPID2) See section 35.3.2.10/ F000_1FFC Component ID Register (MTB0_DWT_COMPID3) See section K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 910 MTBDWT_CTRL[9] = CYCTAP = 0, cycle counter is not supported MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported MTBDWT_CTRL[0] = CYCCNTENA = 0, cycle counter is not supported K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 911 [0] is ignored by the hardware since all fetches must be at least halfword aligned. For MASK != 0 and regardless of watch type, address bits [x-1:0] are ignored in the address comparison. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 912 35.3.2.4 MTB_DWT Comparator Function Register 0 (MTBx0_DWT_FCT0) The MTBDWT_FCTn registers control the operation of comparator n. Address: F000_1000h base + 28h offset = F000_1028h Reset DATAVADDR0 DATAVSIZE FUNCTION Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 913 0000 Disabled. 0100 Instruction fetch. 0101 Data operand read. 0110 Data operand write. 0111 Data operand (read + write). others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 914 Reset FUNCTION Reset MTBx0_DWT_FCT1 field descriptions Field Description 31–25 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 915 MTB's control logic by setting the appropriate enable bits, MTB_MASTER[TSTARTEN, TSTOPEN]. In the event of simultaneous assertion of both TSTART and TSTOP, TSTART takes priority. Address: F000_1000h base + 200h offset = F000_1200h NUMCOMP Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 916 • Data match in MTBDWT_COMP0 and address match in MTBDWT_COMP1 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,1} Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 917 This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FCCh offset = F000_1FCCh DEVICETYPID Reset MTBx0_DWT_DEVICETYPID field descriptions Field Description DEVICETYPID DEVICETYPID Hardwired to 0x0000_0004. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 918 Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. 35.3.3 System ROM Memory Map The System ROM Table registers are also mapped into a sparsely-populated 4 KB address space. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 919 Entry (MTB0_ROM_ENTRY2) See section 35.3.3.1/ F000_200C Entry (MTB0_ROM_ENTRY3) See section 35.3.3.2/ F000_2010 End of Table Marker Register (MTB0_ROM_TABLEMARK) 0000_0000h 35.3.3.3/ F000_2FCC System Access Register (MTB0_ROM_SYSACCESS) 0000_0001h Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 920 Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 921 This register indicates system access. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FCCh offset = F000_2FCCh SYSACCESS Reset MTBx0_ROM_SYSACCESS field descriptions Field Description SYSACCESS SYSACCESS K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 922 Reset MTBx0_ROM_COMPIDn field descriptions Field Description COMPID Component ID Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0010; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 923 The following figure is a block diagram of the PCC clock source selection and clock gating. Some peripherals also have a clock divider available. See the peripheral's PCC register for more information. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 924 PCC registers can only be written in supervisor mode. NOTE Write accesses to unused PCC registers are blocked and result in a bus error. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 925 PCC ADC0 (PCC_ADC0) 80000000h 4007A1A8h PCC DAC0 (PCC_DAC0) 80000000h 4007A1B8h PCC CMP0 (PCC_CMP0) 80000000h 4007A1C8h PCC VREF (PCC_VREF) 80000000h 4007A1E0h PCC CRC (PCC_CRC) 80000000h 36.2.1.1 PCC Register Descriptions 36.2.1.2 PCC DMA0 (PCC_DMA0) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 926 This read-only bit field is reserved and always has the value 0. — 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 927 0 - Peripheral is not present. 1 - Peripheral is present. This read/write bit enables the clock for the peripheral. 0 - Clock disabled 1 - Clock enabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 928 This read-only bit field is reserved and always has the value 0. — 36.2.1.4 PCC DMAMUX0 (PCC_DMAMUX0) 36.2.1.4.1 Address Register Offset PCC_DMAMUX0 4007A084h PCC Register 36.2.1.4.2 Diagram Bits INUS Reserved Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 929 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.1.5 PCC INTMUX0 (PCC_INTMUX0) 36.2.1.5.1 Address Register Offset PCC_INTMUX0 4007A090h PCC Register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 930 — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.1.6 PCC TPM2 (PCC_TPM2) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 931 000 - Clock is off (or test clock is enabled). 001 - OSCCLK - System Oscillator Bus Clock. 010 - SCGIRCLK - Slow IRC Clock. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 932 This read-only bit field is reserved and always has the value 0. — 36.2.1.7 PCC LPIT0 (PCC_LPIT0) 36.2.1.7.1 Address Register Offset PCC_LPIT0 4007A0C0h PCC Register 36.2.1.7.2 Diagram Bits INUS Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 933 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.1.8 PCC LPTMR0 (PCC_LPTMR0) 36.2.1.8.1 Address Register Offset PCC_LPTMR0 4007A0D0h K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 934 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 935 This read-only bit field is reserved and always has the value 0. — 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 936 This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. 1 - Peripheral is present. This read/write bit enables the clock for the peripheral. 0 - Clock disabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 937 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.1.11 PCC LPI2C2 (PCC_LPI2C2) 36.2.1.11.1 Address Register Offset PCC_LPI2C2 4007A108h PCC Register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 938 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 939 This read/write bit enables the clock for the peripheral. 0 - Clock disabled 1 - Clock enabled This read-only bit indicates the peripheral is being used. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 940 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.1.13 PCC EMVSIM0 (PCC_EMVSIM0) 36.2.1.13.1 Address Register Offset PCC_EMVSIM0 4007A138h PCC Register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 941 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 942 This read/write bit enables the clock for the peripheral. 0 - Clock disabled 1 - Clock enabled This read-only bit indicates the peripheral is being used. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 943 010 - Divide by 3. 011 - Divide by 4. 100 - Divide by 5. 101 - Divide by 6. 110 - Divide by 7. 111 - Divide by 8. 36.2.1.15 PCC PORTA (PCC_PORTA) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 944 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 945 0 - Clock disabled 1 - Clock enabled This read-only bit indicates the peripheral is being used. INUSE 0 - Peripheral is not being used. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 946 This read-only bit field is reserved and always has the value 0. — 36.2.1.17 PCC PORTC (PCC_PORTC) 36.2.1.17.1 Address Register Offset PCC_PORTC 4007A170h PCC Register 36.2.1.17.2 Diagram Bits INUS Reserved Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 947 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.1.18 PCC PORTD (PCC_PORTD) 36.2.1.18.1 Address Register Offset PCC_PORTD 4007A174h PCC Register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 948 — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.1.19 PCC PORTE (PCC_PORTE) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 949 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 950 0 - Clock disabled 1 - Clock enabled This read-only bit indicates the peripheral is being used. INUSE 0 - Peripheral is not being used. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 951 This read-only bit field is reserved and always has the value 0. — 36.2.1.21 PCC ADC0 (PCC_ADC0) 36.2.1.21.1 Address Register Offset PCC_ADC0 4007A198h PCC Register 36.2.1.21.2 Diagram Bits INUS Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 952 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.1.22 PCC DAC0 (PCC_DAC0) 36.2.1.22.1 Address Register Offset PCC_DAC0 4007A1A8h K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 953 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 954 This read-only bit field is reserved and always has the value 0. — 23-4 This read-only bit field is reserved and always has the value 0. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 955 This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. 1 - Peripheral is present. This read/write bit enables the clock for the peripheral. 0 - Clock disabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 956 This read-only bit field is reserved and always has the value 0. — 36.2.1.25 PCC CRC (PCC_CRC) 36.2.1.25.1 Address Register Offset PCC_CRC 4007A1E0h PCC Register 36.2.1.25.2 Diagram Bits INUS Reserved Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 957 400FA0B4h PCC TPM1 (PCC_TPM1) 80000000h 400FA0D4h PCC LPTMR1 (PCC_LPTMR1) 80000000h 400FA0F0h PCC LPSPI0 (PCC_LPSPI0) 80000000h 400FA0F4h PCC LPSPI1 (PCC_LPSPI1) 80000000h 400FA100h PCC LPI2C0 (PCC_LPI2C0) 80000000h Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 958 36.2.2.1 PCC Register Descriptions 36.2.2.2 PCC TRNG (PCC_TRNG) 36.2.2.2.1 Address Register Offset PCC_TRNG 400FA094h 36.2.2.2.2 Function PCC Register 36.2.2.2.3 Diagram Bits INUS Reserved Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 959 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.2.3 PCC TPM0 (PCC_TPM0) 36.2.2.3.1 Address Register Offset PCC_TPM0 400FA0B0h PCC Register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 960 101 - Reserved. 110 - SCGPCLK System PLL clock . 111 - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 961 This bit shows whether the peripheral is present on this device. 0 - disabled 1 - enabled This read/write bit enables the clock gate for the peripheral. 0 - Clock disabled 1 - Clock enabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 962 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.2.5 PCC LPTMR1 (PCC_LPTMR1) 36.2.2.5.1 Address Register Offset PCC_LPTMR1 400FA0D4h PCC Register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 963 — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.2.6 PCC LPSPI0 (PCC_LPSPI0) K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 964 This field can only be written when the CGC bit is 0 (clock disabled). Likewise, if the INUSE flag is set, this field is locked. 000 - Clock is off (or test clock is enabled). 001 - OSCCLK - System Oscillator Bus Clock. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 965 This read-only bit field is reserved and always has the value 0. — 36.2.2.7 PCC LPSPI1 (PCC_LPSPI1) 36.2.2.7.1 Address Register Offset PCC_LPSPI1 400FA0F4h PCC Register 36.2.2.7.2 Diagram Bits INUS Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 966 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.2.8 PCC LPI2C0 (PCC_LPI2C0) 36.2.2.8.1 Address Register Offset PCC_LPI2C0 400FA100h K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 967 010 - SCGIRCLK - Slow IRC Clock. 011 - SCGFIRCLK - Fast IRC Clock. 100 - Reserved. 101 - Reserved. 110 - SCGPCLK System PLL clock . Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 968 Reserved Reserved rved Reset 36.2.2.9.3 Fields Field Function This bit shows whether the peripheral is present on this device. 0 - disabled 1 - enabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 969 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.2.10 PCC LPUART0 (PCC_LPUART0) 36.2.2.10.1 Address Register Offset PCC_LPUART0 400FA110h PCC Register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 970 101 - Reserved. 110 - SCGPCLK System PLL clock . 111 - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 971 This bit shows whether the peripheral is present on this device. 0 - disabled 1 - enabled This read/write bit enables the clock gate for the peripheral. 0 - Clock disabled 1 - Clock enabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 972 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 36.2.2.12 PCC FLEXIO0 (PCC_FLEXIO0) 36.2.2.12.1 Address Register Offset PCC_FLEXIO0 400FA128h PCC Register K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 973 101 - Reserved. 110 - SCGPCLK System PLL clock . 111 - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 974 This bit shows whether the peripheral is present on this device. 0 - disabled 1 - enabled This read/write bit enables the clock gate for the peripheral. 0 - Clock disabled 1 - Clock enabled Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 975 LPO. Not all peripherals will make use of all available peripheral functional clocks. The peripheral interface clock can be either DIVSLOW_CLK or DIVCORE_CLK. See each peripherals PCCn register for details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 976 Functional description K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 977 When the VDD supply falls below a specific trip point, the LVD circuit puts the device into a reset state, preventing the device from attempting to operate below its operating voltage range. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 978 The LVD system that monitors the VDD supply contains a Low-Voltage Warning Flag (LVWF) in the Low Voltage Detect Status and Control 2 Register to indicate that the supply voltage is approaching, but is above, the LVD voltage. The LVW also has an K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 979 HVDSC1[HVDV]. After an HVD reset occurs, the HVD system holds the MCU in reset until the supply voltage falls below this threshold. The LVD field in the SRS register of the RCM module (RCM_SRS[LVD]) is set following an HVD reset. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 980 Reset section details. The PMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 981 MINOR This read only field returns the minor version number for the module specification. FEATURE Feature Specification Number This read only field returns the feature set number. 0x0000 Standard features implemented K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 982 This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 983 Reset LVDV Reset PMC_LVDSC1 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 984 While the device is in the very low power or low leakage modes, the LVD system is disabled regardless of LVDSC2 settings. See the device's data sheet for the exact LVD trip voltages. NOTE The LVW trip voltages depend on LVWV and LVDV. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 985 LVW interrupt function, before enabling LVWIE, LVWF must be cleared by writing LVWACK first. Low-voltage warning event not detected Low-voltage warning event detected Low-Voltage Warning Acknowledge LVWACK Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 986 This register is reset on Chip Reset Not VLLS and by reset types that trigger Chip Reset not VLLS. See the Reset section details for more information. Address: 4007_D000h base + 10h offset = 4007_D010h Reset K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 987 ACKISO. In particular, pin configuration for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from being falsely set when ACKISO is cleared. Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 988 See the device's data sheet for the exact HVD trip voltages. NOTE This register is reset solely on a POR Only event.For more information about these reset types, refer to the Reset section details. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 989 HVDIE Enables hardware interrupt requests for HVDF. Hardware interrupt disabled (use polling) Request a hardware interrupt when HVDF = 1 High-Voltage Detect Reset Enable HVDRE Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 990 This read-only field is reserved and always has the value 0. High-Voltage Detect Voltage Select HVDV Selects the HVD trip point voltage (V Low trip point selected (V HVDL High trip point selected (V HVDH K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 991 Disabled Disabled after reset Drive strength PTB0/PTB1 only PTC3/PTC4 only PTD4/PTD5/PTD6/ enable control PTD7 only Drive strength Disabled Disabled Disabled Disabled Disabled enable after reset Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 992 • Digital input filter on selected pins • Digital input filter for each pin, usable by any digital peripheral muxed onto the • Individual enable or bypass control field per pin K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 993 In Stop mode, the PORT can be configured to exit the Low-Power mode via an asynchronous wake-up signal if an enabled interrupt is detected. In Stop mode, the digital input filters are bypassed unless they are configured to run from the LPO clock source. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 994 38.5 Memory map and register definition Any read or write access to the PORT memory space that is outside the valid memory map results in a bus error. All register accesses complete with zero wait states. K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 995 38.5.1/1001 4005_A080 Global Pin Control Low Register (PORTA_GPCLR) (always 0000_0000h 38.5.2/1004 reads 0) 4005_A084 Global Pin Control High Register (PORTA_GPCHR) (always 0000_0000h 38.5.3/1004 reads 0) Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 996 Pin Control Register n (PORTB_PCR26) See section 38.5.1/1001 4005_B06C Pin Control Register n (PORTB_PCR27) See section 38.5.1/1001 4005_B070 Pin Control Register n (PORTB_PCR28) See section 38.5.1/1001 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 997 4005_C048 Pin Control Register n (PORTC_PCR18) See section 38.5.1/1001 4005_C04C Pin Control Register n (PORTC_PCR19) See section 38.5.1/1001 4005_C050 Pin Control Register n (PORTC_PCR20) See section 38.5.1/1001 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 998 4005_D028 Pin Control Register n (PORTD_PCR10) See section 38.5.1/1001 4005_D02C Pin Control Register n (PORTD_PCR11) See section 38.5.1/1001 4005_D030 Pin Control Register n (PORTD_PCR12) See section 38.5.1/1001 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 999 Pin Control Register n (PORTE_PCR2) See section 38.5.1/1001 4005_E00C Pin Control Register n (PORTE_PCR3) See section 38.5.1/1001 4005_E010 Pin Control Register n (PORTE_PCR4) See section 38.5.1/1001 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 NXP Semiconductors...
Page 1000 0000_0000h 38.5.4/1005 reads 0) 4005_E08C Global Interrupt Control High Register (PORTE_GICHR) (always 0000_0000h 38.5.5/1005 reads 0) 4005_E0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 38.5.6/1006 Table continues on the next page... K32 L2A Reference Manual, Rev. 2, 01/2020 1000 NXP Semiconductors...

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K32l2a41vll1a K32l2a31vll1a K32l2a41vlh1a K32l2a31vlh1a

NXP Semiconductors K32 L2A Series Reference Manual

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Chip Configuration

Chapter 4 Memory Map

Chapter 5 Clock Distribution

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10 Signal Multiplexing and Signal Descriptions

Chapter 11 Analog-To-Digital Converter (ADC)

Chapter 12 Crossbar Switch Lite (AXBS-Lite)

Chapter 13 Bit Manipulation Engine2 (BME2)

Chapter 14 Kinetis ROM Bootloader

Chapter 15 Cryptographic Acceleration Unit (CAU)

Chapter 16 Comparator (CMP)

Chapter 17 Cyclic Redundancy Check (CRC)

Chapter 18 12-Bit Digital-To-Analog Converter (DAC)

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Summary of Contents for NXP Semiconductors K32 L2A Series