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NXP Semiconductors K32L2A31VLL1A Reference Manual (1379 pages)

Brand: NXP Semiconductors | Category: Motherboard | Size: 12 MB

Table of Contents
3
Chapter 1 About this Document

43
- Overview
  43
  - Purpose
    43
  - Audience
    43
- Conventions
  43
  - Numbering Systems
    43
  - Typographic Notation
    44
  - Special Terms
    44
Chapter 2 Introduction

45
- Overview
  45
- K32 L2A Introduction
  45
- Feature Summary
  45
- Block Diagram
  49
Chapter 3 Chip Configuration

51
- Introduction
  51
- Clock Gating
  51
- Module to Module Interconnects
  52
  - Interconnection Overview
    52
  - Analog Reference Options
    52
- Core Modules
  53
  - Introduction
    53
  - Arm Cortex M0+ Core
    53
  - Debug Facilities
    54
  - Buses, Interconnects, and Interfaces
    54
  - System Tick Timer
    54
  - Caches
    54
  - Interrupt Connections
    55
  - Asynchronous Wake-Up Interrupt Controller (AWIC)
    59
- System Modules
  60
  - Crossbar Switch
    60
  - Low-Leakage Wake-Up Unit (LLWU)
    61
  - Dmamux
    62
  - Watchdog (WDOG)
    64
  - System Register File Configuration
    64
  - Peripheral Clock Control (PCC) Configuration
    65
  - System Register File Configuration
    66
- Security
  67
  - CAU Configuration
    67
- Analog
  68
  - 16-Bit SAR ADC Configuration
    68
  - CMP Configuration
    70
  - Vref
    72
  - 12-Bit DAC Configuration
    74
- Timers
  75
  - Timer/Pwm Module Configuration
    75
  - Lpit
    77
  - Low Power Timer (LPTMR)
    78
  - RTC Configuration
    79
- Communication Interfaces
  80
  - Universal Serial Bus (USB) FS Subsystem
    80
  - LPSPI Configuration
    86
  - Lpi2C
    87
  - LPUART Configuration
    88
  - EMVSIM Configuration
    89
  - K32 L2A Reference Manual, Rev
    89
  - Flexio
    89
- Human-Machine Interfaces (HMI)
  90
  - GPIO Configuration
    90
  - TSI Configuration
    91
- Signal Multiplexing Integration
  93
  - Signal Multiplexing Configuration
    93
Chapter 4 Memory Map

95
- SRAM Sizes
  95
- System Memory Map
  95
- Flash Memory Maps
  97
  - Flash Memory Map
    97
- SRAM Memory Map
  98
- Bit Manipulation Engine
  98
- Peripheral Bridge (AIPS-Lite) Memory Map
  99
  - AIPS0 Peripheral Slot Assignments
    99
  - AIPS1 Peripheral Slot Assignments
    103
Chapter 5 Clock Distribution

107
- Introduction
  107
- Clock Sources
  108
- SCG Output Clocks
  109
  - Divcore_Clk
    109
  - Divslow_Clk
    109
  - Peripheral Functional Clocks
    109
- Peripheral Clock Summary
  112
- DIV3 Peripheral Clocking
  114
- DIV1 Peripheral Clocking
  115
- Programming Model
  116
- Other Clock Sources
  117
  - Osc32Kclk
    117
  - LPO Low Power Oscillator
    117
- Clock Definitions
  117
- Clocking Details
  118
- Internal Clocking Requirements
  119
- Clock Divider Values after Reset
  120
- Clock Gating
  121
- Flash Memory Clock
  121
Chapter 6 Reset and Boot

123
- Introduction
  123
- Reset
  124
  - Power-On Reset (POR)
    124
  - System Reset Sources
    124
  - MCU Resets
    127
  - Reset_B Pin
    128
  - Debug Resets
    129
- Boot
  129
  - Boot Sources
    129
  - FOPT Boot Options
    130
  - Boot Sequence
    132
Chapter 7 Power Management

135
- Introduction
  135
- Clocking Modes
  135
  - Partial Stop
    135
  - DMA Wakeup
    136
  - Compute Operation
    137
  - Peripheral Doze
    138
  - Clock Gating
    139
- Power Mode Architecture
  139
- Power Modes
  139
- Entering and Exiting Power Modes
  142
- Module Operation in Low-Power Modes
  142
Chapter 8 Security

147
- Introduction
  147
  - Debug Security
    147
  - Flash Security
    147
Chapter 9 Debug

149
- Introduction
  149
- Debug Port Pin Descriptions
  149
- Debug and Trace Block Diagram
  150
- SWD Status and Control Registers
  151
  - MDM-AP Control Register
    152
  - MDM-AP Status Register
    153
- Debug Resets
  155
- Micro Trace Buffer (MTB)
  156
- Debug in Low-Power Modes
  156
- Debug and Security
  157
Chapter 10 Signal Multiplexing and Signal Descriptions

159
- Introduction
  159
- Pinout
  159
  - Package Types
    159
  - Signal Multiplexing and Pin Assignments
    159
  - K32 L2A Pinouts
    164
- Module Signal Description Tables
  166
  - Core Modules
    167
  - System Modules
    167
  - Clock Modules
    167
  - Memories and Memory Interfaces
    167
  - Analog
    168
  - Timer Modules
    168
  - Communication Interfaces
    170
  - Human-Machine Interfaces (HMI)
    173
Chapter 11 Analog-To-Digital Converter (ADC)

175
Chapter 12 Crossbar Switch Lite (AXBS-Lite)

227
- Introduction
  227
  - Features
    227
- Memory Map / Register Definition
  228
- Functional Description
  228
  - General Operation
    228
Chapter 13 Bit Manipulation Engine2 (BME2)

229
- Introduction
  229
  - Features
    230
  - Modes of Operation
    230
- Memory Map and Register Definition
  230
- Functional Description
  231
  - BME Decorated Stores
    231
  - BME Decorated Loads
    238
- Application Information
  244
Chapter 14 Kinetis ROM Bootloader

247
- Chip-Specific Information
  247
  - Kinetis Bootloader Peripheral Pinmux
    247
  - Bootloader Memory Access
    248
- Introduction
  248
- Functional Description
  250
  - Memory Maps
    250
  - The Kinetis Bootloader Configuration Area (BCA)
    251
  - Start-Up Process
    253
  - Clock Configuration
    256
  - Bootloader Entry Point / API Tree
    256
  - Bootloader Protocol
    257
  - Bootloader Packet Types
    262
  - Bootloader Command API
    270
  - Bootloader Exit State
    293
- Peripherals Supported
  294
  - LPI2C Peripheral
    294
  - LPSPI Peripheral
    296
  - Quadspi Peripheral
    299
  - LPUART Peripheral
    307
  - USB Peripheral
    309
- Get/Setproperty Command Properties
  313
  - Property Definitions
    315
- SB File Decryption Support
  316
  - Decryption Using MMCAU
    317
- Verifying the Application in Flash Using CRC-32
  318
- Kinetis Bootloader Status Error Codes
  319
Chapter 15 Cryptographic Acceleration Unit (CAU)

323
- Introduction
  323
- CAU Block Diagram
  323
- Overview
  325
- Features
  326
- Memory Map/Register Definition
  326
  - Status Register (Caux_Casr)
    328
  - Accumulator (Caux_Caa)
    329
  - General Purpose Register (Caux_Can)
    329
- Functional Description
  330
  - CAU Programming Model
    330
  - CAU Integrity Checks
    332
  - CAU Commands
    334
- Application/Initialization Information
  341
  - Code Example
    341
  - Assembler Equate Values
    342
Chapter 16 Comparator (CMP)

345
- Introduction
  345
  - CMP Features
    345
  - 6-Bit DAC Key Features
    346
  - ANMUX Key Features
    346
  - CMP, DAC and ANMUX Diagram
    347
  - CMP Block Diagram
    348
- Memory Map/Register Definitions
  350
- Functional Description
  356
  - CMP Functional Modes
    356
  - Power Modes
    366
  - Startup and Operation
    367
  - Low-Pass Filter
    368
- CMP Interrupts
  370
- DMA Support
  370
- CMP Asynchronous DMA Support
  371
- Digital-To-Analog Converter
  372
- DAC Functional Description
  372
  - Voltage Reference Source Select
    372
- DAC Resets
  373
- DAC Clocks
  373
- DAC Interrupts
  373
- CMP Trigger Mode
  373
Chapter 17 Cyclic Redundancy Check (CRC)

375
- Introduction
  375
  - Features
    375
  - Block Diagram
    375
  - Modes of Operation
    376
- Memory Map and Register Descriptions
  376
- Functional Description
  379
  - CRC Initialization/Reinitialization
    379
  - CRC Calculations
    380
  - Transpose Feature
    381
  - CRC Result Complement
    383
Chapter 18 12-Bit Digital-To-Analog Converter (DAC)

385
- Introduction
  385
- Features
  385
- Block Diagram
  385
- Memory Map/Register Definition
  386
  - DAC Data Low Register (Dacx_Datnl)
    388
  - DAC Data High Register (Dacx_Datnh)
    388
  - DAC Status Register (Dacx_Sr)
    388
  - DAC Control Register (Dacx_C0)
    389
  - DAC Control Register 1 (Dacx_C1)
    391
  - DAC Control Register 2 (Dacx_C2)
    392
- Functional Description
  392
  - DAC Data Buffer Operation
    392
  - DMA Operation
    393
  - Resets
    394
  - Low-Power Mode Operation
    394
Chapter 19 Direct Memory Access Multiplexer (DMAMUX)

395
- Introduction
  395
  - Overview
    395
  - Features
    396
  - Modes of Operation
    396
- External Signal Description
  397
- Memory Map/Register Definition
  397
  - Channel Configuration Register (Dmamuxx_Chcfgn)
    398
- Functional Description
  398
- Initialization/Application Information
  403
  - Reset
    403
  - Enabling and Configuring Sources
    403
Enhanced Direct Memory Access (Edma)

407
Chapter 21 Smart Card Interface Module (EMV SIM)

481
- Introduction
  481
  - Features
    481
- Block Diagram
  482
- Design Overview
  482
- Signal Description
  484
- Memory Map and Registers
  485
- Functional Description
  510
  - Initialization
    510
  - Smart Card Interface and Control
    512
  - EMV SIM Receiver
    515
  - EMV SIM Transmitter
    519
  - LRC and CRC
    521
  - Message Handling
    523
  - Protocol Timers
    525
  - Answer to Reset (ATR) Detection
    528
Chapter 22 Flexible I/O (Flexio)

533
- Introduction
  533
  - Overview
    533
  - Features
    533
  - Block Diagram
    534
  - Modes of Operation
    535
  - Flexio Signal Descriptions
    535
- Memory Map and Registers
  535
  - FLEXIO Register Descriptions
    535
- Functional Description
  565
  - Shifter Operation
    565
  - Timer Operation
    571
  - Pin Operation
    573
- Application Information
  575
  - UART Transmit
    575
  - UART Receive
    576
  - SPI Master
    578
  - SPI Slave
    580
  - I2C Master
    582
  - I2S Master
    583
  - I2S Slave
    585
  - Camera Interface
    586
  - Motorola 68K/Intel 8080 Bus Interface
    587
  - Low Power State Machine
    589
Chapter 23 Flash Memory Controller (FMC)

593
- Introduction
  593
  - Overview
    593
  - Features
    594
- Modes of Operation
  594
- External Signal Description
  594
- Memory Map and Register Descriptions
  594
- Flash Access Control (FAC) Function
  595
  - Memory Map and Register Definitions
    595
  - FAC Functional Description
    595
- Initialization and Application Information
  601
Chapter 24 Flash Memory Module (FTFA)

603
- Introduction
  603
  - Features
    604
  - Block Diagram
    604
  - Glossary
    605
- External Signal Description
  606
- Memory Map and Registers
  607
  - Flash Configuration Field Description
    607
  - Program Flash IFR Map
    607
  - Program Flash Erasable IFR Map
    608
  - Register Descriptions
    609
- Functional Description
  622
  - Flash Protection
    623
  - Flash Access Protection
    623
  - Interrupts
    625
  - Flash Operation in Low-Power Modes
    625
  - Functional Modes of Operation
    626
  - Flash Reads and Ignored Writes
    626
  - Read While Write (RWW)
    626
  - Flash Program and Erase
    626
  - Flash Command Operations
    627
  - Margin Read Commands
    632
  - Flash Command Description
    633
  - Security
    653
  - Reset Sequence
    655
Chapter 25 Interrupt Multiplexer (INTMUX)

657
- About this Module
  657
  - Introduction
    657
  - Features
    657
  - Block Diagram
    657
- Memory Map and Register Definition
  658
- Functional Description
  662
  - Configuring Output Channels
    662
  - INTMUX Vectors
    663
Chapter 26 Low-Leakage Wakeup Unit (LLWU)

665
- Introduction
  665
  - Features
    665
  - Modes of Operation
    666
  - Block Diagram
    667
- LLWU Signal Descriptions
  668
- Memory Map/Register Definition
  669
- Functional Description
  691
  - LLS Mode
    691
  - VLLS Modes
    692
  - Initialization
    692
Chapter 27 Low Power Inter-Integrated Circuit (LPI2C)

693
- Introduction
  693
  - Overview
    693
  - Features
    693
  - Block Diagram
    695
  - Modes of Operation
    695

NXP Semiconductors Categories

Motherboard Microcontrollers Computer Hardware Control Unit Controller

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NXP Semiconductors K32L2A31VLL1A Manuals

NXP Semiconductors K32L2A31VLL1A Reference Manual (1379 pages)

Table of Contents

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Chip Configuration

Chapter 4 Memory Map

Chapter 5 Clock Distribution

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10 Signal Multiplexing and Signal Descriptions

Chapter 11 Analog-To-Digital Converter (ADC)

Chapter 12 Crossbar Switch Lite (AXBS-Lite)

Chapter 13 Bit Manipulation Engine2 (BME2)

Chapter 14 Kinetis ROM Bootloader

Chapter 15 Cryptographic Acceleration Unit (CAU)

Chapter 16 Comparator (CMP)

Chapter 17 Cyclic Redundancy Check (CRC)

Chapter 18 12-Bit Digital-To-Analog Converter (DAC)

Chapter 19 Direct Memory Access Multiplexer (DMAMUX)

Enhanced Direct Memory Access (Edma)

Chapter 21 Smart Card Interface Module (EMV SIM)

Chapter 22 Flexible I/O (Flexio)

Chapter 23 Flash Memory Controller (FMC)

Chapter 24 Flash Memory Module (FTFA)

Chapter 25 Interrupt Multiplexer (INTMUX)

Chapter 26 Low-Leakage Wakeup Unit (LLWU)

Chapter 27 Low Power Inter-Integrated Circuit (LPI2C)

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