Preparation And Setup - Broadcom ACPL-C799 User Manual

ACPL-C799 Evaluation Kit Board
User Guide
Table 1 Input Voltage with Ideal Corresponding Density of 1s at Module Data Output, and ADC Code
Analog Input
+Full-Scale
+Recommended Input Range
Zero
–-Recommended Input Range
–Full-Scale
A digital filter converts the single-bit data stream from the modulator into a multi-bit output word similar to the digital output of a
conventional A/D converter. With this conversion, the data rate of the word output is also reduced (decimation). A Sinc3 filter is
recommended to work together with the ACPL-C799. With a 10-MHz internal clock frequency, 256 decimation ratio and 16-bit
word settings, the output data rate is 39 kHz (= 10 MHz/256). This filter can be implemented in an ASIC, an FPGA, or a DSP.
In this evalboard, Sinc3 filter is implemented using Xilinx Spartan XC3S250E FPGA. The FPGA hardware is designed in Verilog/VHDL
environment. Major building block are the Digital Filter and USB interface control as shown in
and implemented using Xilinx Tool to a bitstream file. This bitstream file can be loaded to FPGA through USB, which is already done
for each evalboard kit shipped to customer.
Figure 2 Digital Filter and USB Interface Control
C799

Preparation and Setup

1. Each complete ACPL-C799 evaluation kit shipment will come with the following items:
ACPL-C799 evalboard
—
Cable with USB / mini USB terminations
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Cable with 3.5mm audio jack / crocodile clip connectors
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Softcopy folder containing drivers and application software programs
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2. The softcopy folder contains the following document or software programs:
ACPL-C799 Xilinx FPGA Evbd Kit User Guide.pdf – evalboard user guide
—
CDM20830_Setup.exe – FTDI USB chipset driver for Windows 32-bit and 64-bit operating systems. For other OS, you can
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download om the manufacturer's website: http://www.ftdichip.com/Drivers/VCP.htm
dig_filter_50_rev1.exe – Avago application GUI software.
—
dig_filter_50_rev1.bit – FPGA bitfile
—
Sinc3_verilog.txt – Sinc3filter codes in Verilog
—
Voltage Input Density of 1s
+80mV 100%
+50mV 81.25%
0mV 50%
–50mV 18.75%
–80mV 0%
Density of 0s
0%
18.75%
50%
81.25%
100%
Broadcom
- 2 -
ADC Code (16-bit unsigned decimation)
65,535
53,248
32,768
12,288
0
Figure 2. The design is synthesized
Preparation and Setup