Elitegroup Computer Systems P6VXM2T Manual page 55

AGP Master 1 WS Write (Disabled)
This implements a single delay when writing to the AGP Bus.
By default, two-wait states are used by the system, allowing
for greater stability.
AGP Master 1 WS Read (Disabled)
This implements a single delay when reading to the AGP Bus.
By default, two-wait states are used by the system, allowing
for greater stability.
Memory Parity/ECC Check (Disabled)
Enable this item to allow BIOS to perform a parity check to the
POST memory tests. Select Enabled only if the system DRAM
supports parity checking.
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