Seco Q7-A29 User Manual page 40

Qseven rel.2.0 compliant module with the amd embedded g-series family socs

3.2.3.12 LPC interface signals

According to Qseven

specifications rel. 2.0, on the golden card edge connector there are 8 pins that are used for implementation of Low Pin Count (LPC) Bus

interface.

Warning: Although the Qseven

option is intended only for the manufacturers of the modules who are free to choose the option they deem more appropriate.

On the Q7-A29 module, the aforementioned pins have been dedicated to the LPC bus; use of these pins for different implementations other than

LPC (i.e. as GPIOs) is therefore not possible.

The following signals are available:

LPC_AD[0÷3]: LPC address, command and data bus, bidirectional signal, +3.3V_A electrical level.

LPC_CLK: LPC Clock Output line, +3.3V_A electrical level. Since only a clock line is available, if more LPC devices are available on the carrier board, then it is

necessary to provide for a zero-delay clock buffer to connect all clock lines to the single clock output of Qseven

LPC_LDRQ#: LPC DMA Request line, +3.3V_A electrical level input.

LPC_FRAME#: LPC Frame indicator, active low output line, +3.3V_A electrical level. This signal is used to signal the start of a new cycle of transmission, or the

termination of existing cycles due to abort or time-out condition.

SERIRQ: LPC Serialised IRQ request, bidirectional line, +3.3V_S electrical level. This signal is used only by peripherals requiring Interrupt support.

3.2.3.13 SPI interface signals

According to newest Qseven

Rel. 2.0 specifications, Q7-A29 can optionally offer one SPI interface, which is derived from AMD G-series SOC's USB port #6 by

using the same USB-to-Serial bridge (Cypress CY7C65215) used for deriving the UART interface (see par. 3.2.3.2). The SPI interface is derived by device's serial

port #1.

This interface can be used for connection of EEPROMs and Serial Flash devices, but it does not support platform firmware (BIOS).

SPI interface supports master mode, with speed up to 3MHz.

Signals involved with SPI management are the following:

SPI_MOSI: SPI Master Out Slave In, Output from Qseven

resistor.

SPI_MISO: SPI Master In Slave Out, Input to Qseven

SPI_CLK: SPI Clock Output to carrier board's SPI embedded devices. Electrical level +3.3V_S.

SPI_CS0#: SPI Chip select, active low output signal, +3.3V_S electrical level.

Q7-A29

specification states that pins 185-192 can be used for the implementation of the LPC bus or as 8 GPIOs, this

module to SPI devices embedded on the Carrier Board. Electrical level +3.3V_S with 10kΩ pull-up