Seco Q7-A29 User Manual page 27

Qseven rel.2.0 compliant module with the amd embedded g-series family socs

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3.2.3.1 PCI Express interface signals

Q7-A29 can offer externally up to four PCI Express lanes Gen 2 (5Gbps), which are managed by AMD G-series SOC.

Here following the signals involved in PCI express management:

PCIE0_TX+/PCIE0_TX-: PCI Express lane #0, Transmitting Output Differential pair.

PCIE0_RX+/PCIE0_RX-: PCI Express lane #0, Receiving Input Differential pair.

PCIE1_TX+/PCIE1_TX-: PCI Express lane #1, Transmitting Output Differential pair.

PCIE1_RX+/PCIE1_RX-: PCI Express lane #1, Receiving Input Differential pair.

PCIE2_TX+/PCIE2_TX-: PCI Express lane #2, Transmitting Output Differential pair.

PCIE2_RX+/PCIE2_RX-: PCI Express lane #2, Receiving Input Differential pair.

PCIE3_TX+/PCIE3_TX-: PCI Express lane #3, Transmitting Output Differential pair. This lane is not externally available with GX-210JA SOC.

PCIE3_RX+/PCIE3_RX-: PCI Express lane #3, Receiving Input Differential pair. This lane is not externally available with GX-210JA SOC.

PCIE_CLK_REF+/ PCIE_CLK_REF-: PCI Express Reference Clock, Differential Pair. Please consider that only one reference clock is supplied, while there are three

different PCI express lanes. When more than one PCI Express lane is used on the carrier board, then a zero-delay buffer must be used to replicate the reference

clock to all the devices.

PCIE_WAKE#: Qseven

Module's Wake Input, it must be externally driven by devices requiring waking up the system. Since it is an Active-Low Input to the

module, this signal is pulled-up with a 100kΩ resistor to +3.3V_A power rail. On the carrier board, connect it directly to the PCI-e/miniPCI-e connector's WAKE#

signal, or to WAKE# signal of any eventual PCI-e Controller present on the Carrier Board.

PCIE_RST#: Reset Signal that is sent from Qseven

to drive externally a single RESET Signal. In case it is necessary to supply Reset signal to multiple devices, then a buffer on the carrier board could be necessary.

PCI-e lanes can be managed as 4 PCI-e x1 ports, 1 PCI-e x2 + 2 PCI-e x1, 2 PCI-e x 2 or 1 PCI-e x4 ports. PCI-e x4 grouping is not possible using GX-210JA

SOC.

Q7-A29

+5V_S

Module to any PCI-e device available on the carrier board. It is a 3.3V active-low signal; it can be used directly

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+5V_S

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+5V_S

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