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Arrow Central Europe GmbH
User Guide
3.3
Design Implementation
The following table lists the clock frequencies used in the design.
Table 2: Hardware Design Clock Frequencies
Clock
PF_OSC
PF_CCC OUT0_FABCLK
HCLK / PCLK
PF_TX_PLL
DIV_CLK
The top-level design implementation for Everest DEV Board PROTO is shown in Figure 4.
Figure 4: Design Implementation – Top Level Everest DEV Board PROTO
The top-level design implementation for Everest DEV Board Rev. A and B has an extra
CoreGPIO called SFP_CTRL that receives the signal SFP_MOD, SFP_TX_FAULT and
SFP_RX_LOS, including interrupt generation for those signal, and drives the signals
SFP_TX_DIS, SFP_RS0 and SFP_RS1.
Frequency (MHz)
160
27.5
27.5
156.25
125
page 13
Everest-CortexM1-Demo
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