Table of Contents
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A
<11>
DDR_A_D[0..63]
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
1
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
2
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
<11>
DDR_A_BS0
3
<11>
DDR_A_BS1
<11>
DDR_A_BS2
<11>
DDR_A_CAS#
<11>
DDR_A_RAS#
<11>
DDR_A_WE#
Follow CRB1.0
R19
0_0402_5%
1
@
通 通
做
CPU
D IMM
r eset
3
1
SM_DRAMRST#
<5>
SM_DRAMRST#
Q1
BSS138_NL_SOT23-3
R22
4.99K_0402_1%
4
R23
RST_GATE_R
0_0402_5%
1
2
<14>
RST_GATE
DS3@
R24
0_0402_5%
1
2
<29>
EC_RST_GATE
DS3@
1
C68
0.047U_0402_16V7K
2
A
B
UCPU1C
AG6
SA_DQ[0]
AJ6
AU36
SA_DQ[1]
SA_CK[0]
AP11
AV36
SA_DQ[2]
SA_CK#[0]
AL6
AY26
SA_DQ[3]
SA_CKE[0]
AJ10
SA_DQ[4]
AJ8
SA_DQ[5]
AL8
SA_DQ[6]
AL7
SA_DQ[7]
AR11
SA_DQ[8]
AP6
AT40
SA_DQ[9]
SA_CK[1]
AU6
AU40
SA_DQ[10]
SA_CK#[1]
AV9
BB26
SA_DQ[11]
SA_CKE[1]
AR6
SA_DQ[12]
AP8
SA_DQ[13]
AT13
SA_DQ[14]
AU13
SA_DQ[15]
BC7
SA_DQ[16]
BB7
BB40
SA_DQ[17]
SA_CS#[0]
BA13
BC41
SA_DQ[18]
SA_CS#[1]
BB11
SA_DQ[19]
BA7
SA_DQ[20]
BA9
SA_DQ[21]
BB9
SA_DQ[22]
AY13
SA_DQ[23]
AV14
AY40
SA_DQ[24]
SA_ODT[0]
AR14
BA41
SA_DQ[25]
SA_ODT[1]
AY17
SA_DQ[26]
AR19
SA_DQ[27]
BA14
SA_DQ[28]
AU14
SA_DQ[29]
BB14
SA_DQ[30]
BB17
AL11
DDR_A_DQS#0
SA_DQ[31]
SA_DQS#[0]
BA45
AR8
DDR_A_DQS#1
SA_DQ[32]
SA_DQS#[1]
AR43
AV11
DDR_A_DQS#2
SA_DQ[33]
SA_DQS#[2]
AW48
AT17
DDR_A_DQS#3
SA_DQ[34]
SA_DQS#[3]
BC48
AV45
DDR_A_DQS#4
SA_DQ[35]
SA_DQS#[4]
BC45
AY51
DDR_A_DQS#5
SA_DQ[36]
SA_DQS#[5]
AR45
AT55
DDR_A_DQS#6
SA_DQ[37]
SA_DQS#[6]
AT48
AK55
DDR_A_DQS#7
SA_DQ[38]
SA_DQS#[7]
AY48
SA_DQ[39]
BA49
SA_DQ[40]
AV49
SA_DQ[41]
BB51
SA_DQ[42]
AY53
SA_DQ[43]
BB49
SA_DQ[44]
AU49
AJ11
DDR_A_DQS0
SA_DQ[45]
SA_DQS[0]
BA53
AR10
DDR_A_DQS1
SA_DQ[46]
SA_DQS[1]
BB55
AY11
DDR_A_DQS2
SA_DQ[47]
SA_DQS[2]
BA55
AU17
DDR_A_DQS3
SA_DQ[48]
SA_DQS[3]
AV56
AW45
DDR_A_DQS4
SA_DQ[49]
SA_DQS[4]
AP50
AV51
DDR_A_DQS5
SA_DQ[50]
SA_DQS[5]
AP53
AT56
DDR_A_DQS6
SA_DQ[51]
SA_DQS[6]
AV54
AK54
DDR_A_DQS7
SA_DQ[52]
SA_DQS[7]
AT54
SA_DQ[53]
AP56
SA_DQ[54]
AP52
SA_DQ[55]
AN57
SA_DQ[56]
AN53
SA_DQ[57]
AG56
SA_DQ[58]
AG53
SA_DQ[59]
AN55
SA_DQ[60]
AN52
BG35
DDR_A_MA0
SA_DQ[61]
SA_MA[0]
AG55
BB34
DDR_A_MA1
SA_DQ[62]
SA_MA[1]
AK56
BE35
DDR_A_MA2
SA_DQ[63]
SA_MA[2]
BD35
DDR_A_MA3
SA_MA[3]
AT34
DDR_A_MA4
SA_MA[4]
AU34
DDR_A_MA5
SA_MA[5]
BB32
DDR_A_MA6
SA_MA[6]
BD37
AT32
DDR_A_MA7
SA_BS[0]
SA_MA[7]
BF36
AY32
DDR_A_MA8
SA_BS[1]
SA_MA[8]
BA28
AV32
DDR_A_MA9
SA_BS[2]
SA_MA[9]
BE37
DDR_A_MA10
SA_MA[10]
BA30
DDR_A_MA11
SA_MA[11]
BC30
DDR_A_MA12
SA_MA[12]
BE39
AW41
DDR_A_MA13
SA_CAS#
SA_MA[13]
BD39
AY28
DDR_A_MA14
SA_RAS#
SA_MA[14]
AT41
AU26
DDR_A_MA15
SA_WE#
SA_MA[15]
IVY-BRIDGE_BGA1023
C867@
+1.5V
R20
2
1K_0402_5%
1
2
DIMM_DRAMRST#_R
DIMM_DRAMRST#
R21
1K_0402_5%
S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
Dimm not reset
S3
RST_GATE_R
<11,12>
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
Dimm not reset
S4,5
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# low
Dimm reset
B
C
<12>
DDR_B_D[0..63]
SA_CLK_DDR0
<11>
SA_CLK_DDR#0
<11>
DDRA_CKE0_DIMMA
<11>
SA_CLK_DDR1
<11>
SA_CLK_DDR#1
<11>
DDRA_CKE1_DIMMA
<11>
DDRA_CS0_DIMMA#
<11>
DDRA_CS1_DIMMA#
<11>
SA_ODT0
<11>
SA_ODT1
<11>
DDR_A_DQS#[0..7]
<11>
DDR_A_DQS[0..7]
<11>
DDR_A_MA[0..15]
<11>
<12>
DDR_B_BS0
<12>
DDR_B_BS1
<12>
DDR_B_BS2
<12>
DDR_B_CAS#
<12>
DDR_B_RAS#
<12>
DDR_B_WE#
<11,12>
Security Classification
Security Classification
Security Classification
2011/11/22
2011/11/22
2011/11/22
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
UCPU1D
AL4
DDR_B_D0
SB_DQ[0]
AL1
BA34
DDR_B_D1
SB_DQ[1]
SB_CK[0]
DDR_B_D2
AN3
AY34
SB_DQ[2]
SB_CK#[0]
DDR_B_D3
AR4
AR22
SB_DQ[3]
SB_CKE[0]
DDR_B_D4
AK4
SB_DQ[4]
DDR_B_D5
AK3
SB_DQ[5]
DDR_B_D6
AN4
SB_DQ[6]
DDR_B_D7
AR1
SB_DQ[7]
DDR_B_D8
AU4
SB_DQ[8]
AT2
BA36
DDR_B_D9
SB_DQ[9]
SB_CK[1]
DDR_B_D10
AV4
BB36
SB_DQ[10]
SB_CK#[1]
DDR_B_D11
BA4
BF27
SB_DQ[11]
SB_CKE[1]
DDR_B_D12
AU3
SB_DQ[12]
DDR_B_D13
AR3
SB_DQ[13]
DDR_B_D14
AY2
SB_DQ[14]
DDR_B_D15
BA3
SB_DQ[15]
DDR_B_D16
BE9
SB_DQ[16]
DDR_B_D17
BD9
BE41
SB_DQ[17]
SB_CS#[0]
BD13
BE47
DDR_B_D18
SB_DQ[18]
SB_CS#[1]
DDR_B_D19
BF12
SB_DQ[19]
DDR_B_D20
BF8
SB_DQ[20]
DDR_B_D21
BD10
SB_DQ[21]
DDR_B_D22
BD14
SB_DQ[22]
DDR_B_D23
BE13
SB_DQ[23]
DDR_B_D24
BF16
AT43
SB_DQ[24]
SB_ODT[0]
DDR_B_D25
BE17
BG47
SB_DQ[25]
SB_ODT[1]
DDR_B_D26
BE18
SB_DQ[26]
BE21
DDR_B_D27
SB_DQ[27]
DDR_B_D28
BE14
SB_DQ[28]
DDR_B_D29
BG14
SB_DQ[29]
DDR_B_D30
BG18
SB_DQ[30]
DDR_B_D31
BF19
AL3
SB_DQ[31]
SB_DQS#[0]
DDR_B_D32
BD50
AV3
SB_DQ[32]
SB_DQS#[1]
DDR_B_D33
BF48
BG11
SB_DQ[33]
SB_DQS#[2]
DDR_B_D34
BD53
BD17
SB_DQ[34]
SB_DQS#[3]
DDR_B_D35
BF52
BG51
SB_DQ[35]
SB_DQS#[4]
DDR_B_D36
BD49
BA59
SB_DQ[36]
SB_DQS#[5]
DDR_B_D37
BE49
AT60
SB_DQ[37]
SB_DQS#[6]
DDR_B_D38
BD54
AK59
SB_DQ[38]
SB_DQS#[7]
DDR_B_D39
BE53
SB_DQ[39]
DDR_B_D40
BF56
SB_DQ[40]
DDR_B_D41
BE57
SB_DQ[41]
DDR_B_D42
BC59
SB_DQ[42]
AY60
DDR_B_D43
SB_DQ[43]
DDR_B_D44
BE54
SB_DQ[44]
DDR_B_D45
BG54
SB_DQ[45]
DDR_B_D46
BA58
AM2
SB_DQ[46]
SB_DQS[0]
DDR_B_D47
AW59
AV1
SB_DQ[47]
SB_DQS[1]
DDR_B_D48
AW58
BE11
SB_DQ[48]
SB_DQS[2]
DDR_B_D49
AU58
BD18
SB_DQ[49]
SB_DQS[3]
DDR_B_D50
AN61
BE51
SB_DQ[50]
SB_DQS[4]
DDR_B_D51
AN59
BA61
SB_DQ[51]
SB_DQS[5]
AU59
AR59
DDR_B_D52
SB_DQ[52]
SB_DQS[6]
DDR_B_D53
AU61
AK61
SB_DQ[53]
SB_DQS[7]
DDR_B_D54
AN58
SB_DQ[54]
DDR_B_D55
AR58
SB_DQ[55]
DDR_B_D56
AK58
SB_DQ[56]
DDR_B_D57
AL58
SB_DQ[57]
DDR_B_D58
AG58
SB_DQ[58]
DDR_B_D59
AG59
SB_DQ[59]
AM60
DDR_B_D60
SB_DQ[60]
AL59
BF32
DDR_B_D61
SB_DQ[61]
SB_MA[0]
DDR_B_D62
AF61
BE33
SB_DQ[62]
SB_MA[1]
DDR_B_D63
AH60
BD33
SB_DQ[63]
SB_MA[2]
AU30
SB_MA[3]
BD30
SB_MA[4]
AV30
SB_MA[5]
BG30
SB_MA[6]
BG39
BD29
SB_BS[0]
SB_MA[7]
BD42
BE30
SB_BS[1]
SB_MA[8]
AT22
BE28
SB_BS[2]
SB_MA[9]
BD43
SB_MA[10]
AT28
SB_MA[11]
AV28
SB_MA[12]
AV43
BD46
SB_CAS#
SB_MA[13]
BF40
AT26
SB_RAS#
SB_MA[14]
BD45
AU22
SB_WE#
SB_MA[15]
IVY-BRIDGE_BGA1023
C867@
Compal Secret Data
Compal Secret Data
Compal Secret Data
2012/11/22
2012/11/22
2012/11/22
Deciphered Date
Deciphered Date
Deciphered Date
D
E
SB_CLK_DDR0
<12>
SB_CLK_DDR#0
<12>
DDRB_CKE0_DIMMB
<12>
SB_CLK_DDR1
<12>
SB_CLK_DDR#1
<12>
DDRB_CKE1_DIMMB
<12>
DDRB_CS0_DIMMB#
<12>
DDRB_CS1_DIMMB#
<12>
SB_ODT0
<12>
SB_ODT1
<12>
DDR_B_DQS#[0..7]
<12>
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7
DDR_B_DQS[0..7]
<12>
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_MA[0..15]
<12>
DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
PROCESSOR(3/7) DDRIII
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
1.0
1.0
1.0
Q1VZC M/B LA-8941P Schematic
Q1VZC M/B LA-8941P Schematic
Q1VZC M/B LA-8941P Schematic
Date:
Date:
Date:
Friday, April 20, 2012
Friday, April 20, 2012
Friday, April 20, 2012
Sheet
Sheet
Sheet
6
6
6
of
of
of
45
45
45
E
1
2
3
4
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