Acer Q1VZC Schematics Document page 18

A
HDA_SYNC PH(PLL =+1.5VS)
GPIO28
On-Die PLL Voltage Regulator
This signal has a weak internal pull up
* H ： ： ： ： O n-Die PLL voltage regulator enable
L ： ： ： ： O n-Die PLL Voltage Regulator disable
+VCCSUS3_3
1
R202
4.7K_0402_5%
PCH_GPIO28
R205
@ 1K_0402_5%
Debug Port DG 1.2 PU 4.7K +3VALW_PCH
Deep S4,S5 wake event signal
RTC alarm,Power BTN,GPIO27
PCH_GPIO27 (Have internal Pull-High)
Deep S4,S5 wake event signal
R209 1 @ 2 10K_0402_5% PCH_GPIO27
2 +3VS
R211 2 1 200K_0402_5% PCH_GPIO36
+3VALW_PCH
R214 1 @ 2 1K_0402_5% EC_SMI#
SATA2GP/GPIO36 & SATA3GP/GPIO37
Sampled at Rising edge of PWROK.
Weak internal pull-down.
(weak internal pull-down is disabled
after PLTRST# de-asserts)
NOTE: This signal should NOT be
pulled high when strap is sampled
+3VS
1 2 PCH_GPIO0
R216 10K_0402_5%
1 2 PCH_GPIO1
R218 10K_0402_5%
3
R219 1 2 10K_0402_5% PCH_GPIO6
R220 1 2 10K_0402_5% PCH_GPIO16
R221 1 2 10K_0402_5% PCH_GPIO17
1 2 PCH_GPIO38
R522 10K_0402_5%
12/13 Add
R222 1 2 10K_0402_5% PCH_GPIO34
R223 1 2 10K_0402_5% PCH_GPIO48
1 2 PCH_GPIO49
R225 10K_0402_5%
+VCCSUS3_3
+VCCSUS3_3
1 2 PCH_GPIO12
R227 10K_0402_5%
R228 1 2 1K_0402_5% EC_LID_OUT#
R232 1 2 10K_0402_5% PCH_GPIO57
GPIO36/GPIO37 is Strap functionality
4
GPIO24 Unmultiplexed
that requires internal pull down to be sampled at rising PWROK.
NOTE: GPIO24 configuration
When uses as SATA2GP/SATA3GP for mechanical presence detect
register bits are not cleared by -use a external pull up 150K-200K ohm to Vcc3_3
CF9h reset event. When used as GP input
-ensure GPI is not driven high during strap sampling window
CRB1.0 PU 10K to +3VALW
When Unused as GPIO or SATA*GP
-use 8.2K-10K pull-down
check list page 47
A
B
Fan Tachometer Inputs
TACH1~7 only on server
can insted to GPIO
No use PU 10K +3VS
No use PU 10K +3VS
No use PU 10K +3VS
No use PU 10K +3VS
<29> EC_SCI#
No use PU 10K +3VALW
<29> EC_SMI#
No use PU +3VALW
No use PU +3VALW
<29> EC_LID_OUT#
No use PU +3VS
No use PU +3VS
No use PU 10K +3VS RAM flag
No use PU +3VALW DDR3/DDR3L
No use PD 10K to GND
No use PU 10K +3VALW
No use PU 10K +3VS BT ON/OFF
No use can NC PAD T20 @
Can't PU
Can't PU PAD T21 @
No use PU 10K +3VS
No use PU 10K +3VS RAM flag
No use PU 10K +3VS
SATA5GP&TEMP_ALERT# CRB PU 10K +3VS
No use PU +3VALW
9/15 Layout
request remove
Test point
They will route
by itself
1 2 PCH_GPIO24
R224 10K_0402_5%
1 2
R226 @ 10K_0402_5%
B
C
11/21 EDP@->POP
LVDS/eDP
GPIO71
LVDS 1
eDP 0
U16F
PCH_GPIO0 T7
BMBUSY# / GPIO0 TACH4 / GPIO68
PCH_GPIO1 A42
TACH1 / GPIO1 TACH5 / GPIO69
PCH_GPIO6 H36
TACH2 / GPIO6 TACH6 / GPIO70
E38
EC_SCI#
TACH3 / GPIO7 TACH7 / GPIO71
EC_SMI# C10
GPIO8
PCH_GPIO12 C4
LAN_PHY_PWR_CTRL / GPIO12
EC_LID_OUT# G2
GPIO15 A20GATE
U2
PCH_GPIO16
SATA4GP / GPIO16
RCIN#
PCH_GPIO17 D40
TACH0 / GPIO17 PROCPWRGD
PCH_GPIO22 T5
SCLOCK / GPIO22 THRMTRIP#
PCH_GPIO24 E8
GPIO24 / MEM_LED INIT3_3V#
PCH_GPIO27 E16
GPIO27
PCH_GPIO28 P8
GPIO28
NC_1
PCH_GPIO34 K1
STP_PCI# / GPIO34
NC_2
PCH_GPIO35 K4
GPIO35
NC_3
PCH_GPIO36 V8
SATA2GP / GPIO36
NC_4
PCH_GPIO37 M5
SATA3GP / GPIO37
NC_5
PCH_GPIO38 N2
SLOAD / GPIO38
PCH_GPIO39 M3
SDATAOUT0 / GPIO39
V13
PCH_GPIO48
SDATAOUT1 / GPIO48 VSS_NCTF_15
PCH_GPIO49 V3
SATA5GP / GPIO49 VSS_NCTF_16
PCH_GPIO57 D6
GPIO57 VSS_NCTF_17
VSS_NCTF_18
A4
VSS_NCTF_1 VSS_NCTF_19
A44
VSS_NCTF_2 VSS_NCTF_20
A45
VSS_NCTF_3 VSS_NCTF_21
A46
VSS_NCTF_4 VSS_NCTF_22
A5
VSS_NCTF_5 VSS_NCTF_23
A6
VSS_NCTF_6 VSS_NCTF_24
B3
VSS_NCTF_7 VSS_NCTF_25
B47
VSS_NCTF_8 VSS_NCTF_26
BD1
VSS_NCTF_9 VSS_NCTF_27
BD49
VSS_NCTF_10 VSS_NCTF_28
BE1
VSS_NCTF_11 VSS_NCTF_29
BE49
VSS_NCTF_12 VSS_NCTF_30
BF1
VSS_NCTF_13 VSS_NCTF_31
BF49
VSS_NCTF_14 VSS_NCTF_32
COUGARPOINT_FCBGA989
HM77@
Security Classification Security Classification Security Classification
2011/11/22 2011/11/22 2011/11/22
Issued Date Issued Date Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
D
+3VS +3VS +3VS
R198 R199 R200
10K_0402_5% 10K_0402_5% 10K_0402_5%@
LVDS@ @
PCH_GPIO71 PCH_GPIO69 PCH_GPIO70
R201 R203 R204
10K_0402_5% 10K_0402_5% 10K_0402_5%
EDP@
C40 PCH_GPIO68
B41 PCH_GPIO69
C41 PCH_GPIO70 +3VS
A40
PCH_GPIO71
R206
10K_0402_5%
P4
AU16 PCH_PECI_R 1 2
@
H_PECI <5,29>
PECI
0_0402_5% R207
P5 EC_KBRST#
EC_KBRST# <29>
AY11
H_CPUPWRGD <5>
AY10 PCH_THRMTRIP#_R 1 2 H_THRMTRIP#
R210 390_0402_5%
T14
INIT3_3V Checklist1.5 P.69
This signal has weak internal
PU, can't pull low,leave NC
AH8
AK11
AH10
TS_VSS1~4
PD to GND
AK10
P37
BG2
BG48 9/15 Layout
request remove
BH3
Test point
BH47
They will route
by itself
BJ4
BJ44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49
Compal Secret Data Compal Secret Data Compal Secret Data
2012/11/22 2012/11/22 2012/11/22
Deciphered Date Deciphered Date Deciphered Date
D
E
GATEA20 <29>
PECI CPU-EC
CTRL+ALT+DEL
non CPU power ok
130c shut down
H_THRMTRIP# <5>
+3VS
EC_KBRST# 1 2
R212 10K_0402_5%
1 2
PCH_GPIO68 R213 10K_0402_5%
+3VS +3VS
R229 R231
10K_0402_5% 10K_0402_5%
PCH_GPIO39 PCH_GPIO22
R233 R235
10K_0402_5%
10K_0402_5%
@ @
Compal Electronics, Inc. Compal Electronics, Inc. Compal Electronics, Inc.
Title Title Title
PCH (6/9) GPIO, CPU, MISC PCH (6/9) GPIO, CPU, MISC PCH (6/9) GPIO, CPU, MISC
Size Size Size Document Number Document Number Document Number Rev Rev Rev
Custom Custom Custom
Q1VZC M/B LA-8941P Schematic Q1VZC M/B LA-8941P Schematic Q1VZC M/B LA-8941P Schematic
Date: Date: Date: Friday, April 20, 2012 Friday, April 20, 2012 Friday, April 20, 2012 Sheet Sheet Sheet 18 18 18 of of of 45 45 45
E
1
2
3
4
1.0 1.0 1.0