Connector J2 - Texas Instruments ADS1174EVM User Manual

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Pin No.
J5.9
J5.10
J5.11
J5.12
J5.13
J5.14
J5.15
J5.16
J5.17
J5.18
J5.19
J5.20
Many pins on J5 have weak pull-up/pull-down resistors. These resistors provide default settings for many
of the control pins. Many pins on J5 correspond directly to ADS1274 pins. See the
sheet for complete details on these pins.
3.2 Data Output
Most data communications are directed through DOUT1. The data from all eight channels can be
observed on the DOUT1 pin using the TDM mode. That is the signal used by the ADS1274EVM-PDK to
read back and display all the channels. All the data output signals (DOUT1 to DOUT4) can be monitored
on J2. Figure 2 illustrates the pinout for J2.
SBAU134A – August 2008 – Revised May 2009
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Table 2. J5: Serial Interface Pins (continued)
Pin Name Signal Name
FSR /DRDY/FSYNC
DGND DGND
DX DIN
GPIO3 FORMAT1
DR DOUT1
GPIO4 FORMAT2
/INT /DRDY/FSYNC
SCL SCL
TOUT CLK
DGND DGND
GPIO5 CLK Select
SDA SDA
Figure 2. Connector J2
ADS1174EVM, ADS1274EVM, ADS1174EVM-PDK, and ADS1274EVM-PDK
I/O Type Pullup
In/Out None
In/Out None
In None
In High
Out None
In None
Out None
2
I C n/a
In None
In/Out None
None
2
I C n/a
Digital Interface
Function
Digital Ground
ADS1274 SPI data
in
ADS1274 data out
2
I C clock
Can be used to
provide a clock from
a processor
Digital Ground
2
I C data
ADS1274 product data
5