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AT91SAM9 LCD Controller
1. Scope
This application note explains how to connect the Atmel
AT91SAM9 LCD Controller to an STN or TFT display. It includes display selection
guidelines, describes the hardware and software configurations and gives perfor-
mance results and software examples.
®
®
®
ARM
Thumb
-based
AT91 ARM
Thumb
Microcontrollers
Application Note
6300A–ATARM–09-Jul-07
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Summary of Contents for Atmel AT91SAM9
- Page 1 This application note explains how to connect the Atmel Thumb -based Thumb AT91SAM9 LCD Controller to an STN or TFT display. It includes display selection guidelines, describes the hardware and software configurations and gives perfor- Microcontrollers mance results and software examples.
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Page 2: Display Overview
2. Display Overview TFT and STN Technologies The most commonly used display technologies are TFT (Thin Film Transistor) and STN (Super Twisted Nematic). STN displays use a passive matrix screen technology that has no active or controlling element inside the display cell. Pixels are controlled by energizing the appropriate row and column drive lines of the matrix from outside the display, resulting in a slow frame rate. - Page 3 Application Note Vertical Front Porch Real image Horizontal Front Porch Horizontal Back Porch Dummy pixel area Vertical Back Porch The dummy pixels/lines are not part of the frame buffer; they are managed by the LCD Control- ler. Some delays must be introduced in vertical and horizontal timings to support it. These delays are often described as vertical/horizontal front/back porch delays in the display datasheets.
- Page 4 3. Display Selection Guide In order to verify the compatibility of a display with the AT91SAM9 LCD Controller, a list of items to check is given below. Technology Type The LCD controller supports TFT RGB (up to 16M colors), color STN (up to 4096 colors) and Monochrome STN (up to 16 gray shades) displays.
- Page 5 Application Note According to the AT91SAM9 features, the maximum LCDDOTCK frequency is equal to the mas- ter clock (in bypass mode). The signal timings provided by the display specification must respect the timings supported by the LCD Controller. • Vertical pulse width from 1 to 64 lines.
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Page 6: Display Description
4. TFT Display Selection Guide Example Display Description An example of a display specification (TX09D71VM1CCA on AT91SAM9261-EK): • TFT QVGA • RGB 262K colors • VCC [3.0 to 3.6V] • Frame rate: 60 Hz • Vertical Pulse Width : typ = 1 (in lines) •... - Page 7 Application Note DCLK to LCDDOTCK DTMG to LCDDEN Add a passive filter between LCDCC and Vctrl. Use a PIO for PCI control. This interface is compatible. 4.2.4 Timings Frame rate 60 Hz: LCDDOTCKfreq = 60 x 320 x 240 = 4.608 MHz < LCDDOTCKfreq max. The delays are all between 1 and 17.
- Page 8 In STN mode, vertical timings should be set to The timings are compatible. 5.2.5 Conclusion The display given in the example is compatible with the AT91SAM9 LCD Controller. 6. Configuration TFT Hardware Connection The AT91SAM9 LCD Controller is based on Blue-Green-Red (BGR) standard while most graph- ical layers use RGB color map.
- Page 9 Application Note – I is Intensity Bit – R[4:0], G[4:0] and B[4:0] are respectively red, green and blue video components. Most graphical layers use RGB 5-6-5: This leads to a swap between blue and red components. There are two solutions to correct, via software or via hardware.
- Page 10 In 24-bit mode, as only 18 bits are wired to the LCD device, the number of colors available is 262,144. Figure 6-1. 18-bit TFT Display Hardware Connection (Software Swap) in 24-bit Mode Application Note 6300A–ATARM–09-Jul-07...
- Page 11 Application Note 6.1.1.2 24-bit TFT Display Figure 6-2. 24-bit TFT Display Hardware Connection (Software Swap) 6300A–ATARM–09-Jul-07...
- Page 12 6.1.2 Hardware Swap The CPU time for swapping can be reduced by the hardware solution for swapping of the red and blue signals. The LCD device is connected as follows to the PIOB lines. 6.1.2.1 18-bit TFT Display In this mode, the LCD Controller can be programmed in 16-bit or 24-bit mode. In 16-bit mode, some framebuffer memory is saved.
- Page 13 Application Note Figure 6-3. 18-bit TFT Display Hardware Connection in 16-bit Mode: RGB 5-6-5 Format 6300A–ATARM–09-Jul-07...
- Page 14 In 24-bit mode, as only 18 bits are wired to the LCD device, the number of colors available is 262,144. Figure 6-4. 18-bit TFT Display Hardware Connection in 24-bit Mode Application Note 6300A–ATARM–09-Jul-07...
- Page 15 24-bit TFT Display Hardware Connection in 24-bit Mode STN Hardware Connection STN display data bus is not based on RGB or BGR bus. It is based on data bus D0 to Dn. Refer to the AT91SAM9 datasheet for more details. Software 6.3.1 Initialization Sequence for AT91SAM9261 device example 6.3.1.1...
- Page 16 6.3.1.2 I/O Lines The pins used for interfacing the LCD Controller are multiplexed with PIO lines. The programmer must first program the PIO Controller to assign the pins to their peripheral function. If some I/O lines of the LCD Controller are not used by the application, they can be used for other purposes by the PIO Controller.
- Page 17 Application Note LCDDOTCK = 320 x 240 x 60 = 4.608 MHz theo CLKVAL = 100 / (2 x 4.608) - 1 = 9.85 theo CLKVAL = 9 LCDDOTCK = 100 / (2 x (9+1)) = 5 MHz. An STN QVGA display has the following features: 320 x 240, 75 Hz, 4-bit data bus. LCDC Clock is 100 MHz.
- Page 18 The other display parameters are configured in the LCDCON2 register: Type, Scan mode, Interface width, Pixel size, etc. 6.3.1.7 LCDCON2 and LCDFRMCFG for Other AT91SAM9 Products The display resolution is set in the LCDFRMCFG register. The LINEVAL field corresponds to the number of lines of the display - 1.
- Page 19 If the frame buffer is located in the SRAM memory, use the address base 0x0030 000. If the frame buffer is located in the SDRAM, it is recommended to store it in a different bank than the application in order to optimize the SDRAM access. Refer to the Atmel application ”, note”Using the SDRAM on AT91SAM9 Microcontrollers...
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Page 20: Matrix Configuration
6.3.1.15 DMA Enable Reset and enable the DMA by setting the DMARST and DMAEN bits in the DMACON register. It must be done in 2 steps. 6.3.1.16 LCD Enable Enable the LCD Controller by setting the LCD_PWR bit in the PWRCON register. At this moment, the LCD Controller is running and is sending frames to the displays via the LCD Con- troller interface. - Page 21 Application Note 7.2.5 Bus Bandwidth Summary Some performance measurements have been done on a AT91SAM9261-EK board. The proces- sor clock is set to 200 MHz, the master clock is set to 100 MHz. The TCM, the MMU and the Caches are not activated. The applied algorithm is Dhrystone 2.1. The Matrix configuration is the default configuration: No Default Master.
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Page 22: Revision History
8. Revision History Revision History Doc. Rev Comments Change Request Ref. Section 6.3.1.7 ”LCDCON2 and LCDFRMCFG for Other Added new 6300B 4510 AT91SAM9 Products” on page 18 6300A First issue. Application Note 6300A–ATARM–09-Jul-07... - Page 23 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...
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