Atmel AT91 ARM Series Application Note

Using the ECC Controller on AT91SAM9260/9263
and AT91SAM7SE Microcontrollers
1. Scope
The purpose of this document is to explain how to use the Error Corrected Code
(ECC) Controller embedded in the AT91SAM9260/9263 and AT91SAM7SE family of
® ®
ARM Thumb -based microcontrollers. The ECC controller performs 2-bit data error
identification and single-bit correction to maintain integrity of data stored in NAND
®
Flash and SmartMedia
2. NAND Flash Device Overview
2.1 Internal Array Architecture
The NAND Flash array is organized in a series of blocks which are divided in several
pages. Data is stored either in byte (8 bits) or half-word (16 bits) format depending on
the device type. Each page consists of a main area for storing data and a spare area
(physically similar) typically used for data error identification and correction, wear lev-
elling, etc...
One particularity of NAND Flash devices is that they may contain a percentage of
invalid blocks in the memory array. Before delivering the chip, these blocks are identi-
fied and marked as "Invalid Blocks" in the first or second page of each block. The
existence of bad blocks does not affect the good ones because each block is indepen-
dent and individually isolated from the bit lines by block select transistors.
Because NAND Flash devices have a finite lifetime (approximately 100 000
write/erase cycles), additional invalid blocks may develop while being used. Storing
data requires bad-block management and data error identification and correction.
Refer to Section 3. "Invalid Block
2.2 Basic Operation Principle
NAND Flash operations are fully controlled through a multiplexed I/O interface and
additional control signals. Commands, addresses and data are transferred through
the external input/output bus (8-bit or 16-bit) to the dedicated internal registers. In 16-
bit devices, commands, addresses and data use the lower 8 bits (7 - 0), the upper 8
bits are only used during data-transfer cycles.
Read and program operations are performed on a per page basis whereas erase
operations are performed on a block basis. To read or write from NAND Flash, a com-
mand sequence is issued to select a block and a page. After this selection, the entire
page can be read or written.
The command sequence normally consists of a Command Latch Cycle, an Address
Latch Cycle and a Data Cycle — either read or write.
devices.
Management".
AT91 ARM
Thumb
Microcontrollers
Application Note
6320B–ATARM–05-Nov-07