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Atmel ATmega256RFR2 Manual

Atmel ATmega256RFR2 Manual

8-bit microcontroller with low power 2.4ghz transceiver for zigbee and ieee 802.15.4

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Features

• Network support by hardware assisted Multiple PAN Address Filtering

• Advanced Hardware assisted Reduced Power Consumption

• High Performance, Low Power AVR

• Advanced RISC Architecture

- 135 Powerful Instructions – Most Single Clock Cycle Execution

- 32x8 General Purpose Working Registers / On-Chip 2-cycle Multiplier

- Up to 16 MIPS Throughput at 16 MHz and 1.8V – Fully Static Operation

• Non-volatile Program and Data Memories

- 256K/128K/64K Bytes of In-System Self-Programmable Flash

• Endurance: 10'000 Write/Erase Cycles @ 125° C (25'000 Cycles @ 85° C)

- 8K/4K/2K Bytes EEPROM

• Endurance: 20'000 Write/Erase Cycles @ 125° C (100'000 Cycles @ 25° C)

- 32K/16K/8K Bytes Internal SRAM

• JTAG (IEEE std. 1149.1 compliant) Interface

- Boundary-scan Capabilities According to the JTAG Standard

- Extensive On-chip Debug Support

- Programming of Flash EEPROM, Fuses and Lock Bits through the JTAG interface

• Peripheral Features

- Multiple Timer/Counter & PWM channels

- Real Time Counter with Separate Oscillator

- 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor

- Master/Slave SPI Serial Interface

- Two Programmable Serial USART

- Byte Oriented 2-wire Serial Interface

• Advanced Interrupt Handler and Power Save Modes

• Watchdog Timer with Separate On-Chip Oscillator

• Power-on Reset and Low Current Brown-Out Detector

• Fully integrated Low Power Transceiver for 2.4 GHz ISM Band

- High Power Amplifier support by TX spectrum side lobe suppression

- Supported Data Rates: 250 kb/s and 500 kb/s, 1 Mb/s, 2 Mb/s

- -100 dBm RX Sensitivity; TX Output Power up to 3.5 dBm

- Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)

- 32 Bit IEEE 802.15.4 Symbol Counter

- SFD-Detection, Spreading; De-Spreading; Framing ; CRC-16 Computation

- Antenna Diversity and TX/RX control / TX/RX 128 Byte Frame Buffer

- Phase measurement support

• PLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4 GHz ISM Band

• Hardware Security (AES, True Random Generator)

• Integrated Crystal Oscillators (32.768 kHz & 16 MHz, external crystal needed)

• I/O and Package

- 38 Programmable I/O Lines

- 64-pad QFN (RoHS/Fully Green)

• Temperature Range: -40° C to 125° C Industrial

• Ultra Low Power consumption (1.8 to 3.6V) for AVR & Rx/Tx: 10.1mA/18.6 mA

- CPU Active Mode (16MHz): 4.1 mA

- 2.4GHz Transceiver: RX_ON 6.0 mA / TX 14.5 mA (maximum TX output power)

- Deep Sleep Mode: <700nA @ 25° C

• Speed Grade: 0 – 16 MHz @ 1.8 – 3.6V range with integrated voltage regulators

Applications

®

• ZigBee

/ IEEE 802.15.4-2011/2006/2003

• General Purpose 2.4GHz ISM Band Transceiver with Microcontroller

• RF4CE, SP100, WirelessHART

8393C-MCU Wireless-09/14

®

8-Bit Microcontroller

™

– Full and Reduced Function Device

™

, ISM Applications and IPv6 / 6LoWPAN

ATmega256/128/64RFR2

8-bit

Microcontroller

with Low Power

2.4GHz

Transceiver for

ZigBee and

IEEE 802.15.4

ATmega256RFR2

ATmega128RFR2

ATmega64RFR2

8393C-MCU Wireless-09/14

1

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Summary of Contents for Atmel ATmega256RFR2

Page 1: Features
- 10-bit, 330 ks/s A/D Converter; Analog Comparator; On-chip Temperature Sensor - Master/Slave SPI Serial Interface - Two Programmable Serial USART - Byte Oriented 2-wire Serial Interface ATmega256RFR2 • Advanced Interrupt Handler and Power Save Modes ATmega128RFR2 • Watchdog Timer with Separate On-Chip Oscillator •...
Page 2: Pin Configurations
1 Pin Configurations Figure 1-1. Pinout ATmega256/128/64RFR2 64 63 56 55 54 53 52 51 50 49 62 61 60 59 58 57 [PF2:ADC2:DIG2] [PE2:XCK0:AIN0] [PF3:ADC3:DIG4] [PE1:TXD0] [PF4:ADC4:TCK] Index corner [PE0:RXD0:PCINT8] [PF5:ADC5:TMS] [DVSS] [PF6:ADC6:TDO] [DEVDD] [PF7:ADC7:TDI] [PB7:OC0A:OC1C:PCINT7] ATmega256/128/64RFR2 [AVSS_RFP] [PB6:OC1B:PCINT6] [RFP] [PB5:OC1A:PCINT5] [RFN]...
Page 3: Overview
ATmega256/128/64RFR2 3 Overview The ATmega256/128/64RFR2 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture combined with a high data rate transceiver for the 2.4 GHz ISM band. By executing powerful instructions in a single clock cycle, the device achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Page 4 Spectrum Signal (DSSS) processing with spreading and despreading. The device is fully compatible with IEEE802.15.4-2011/2006/2003 and ZigBee standards. The ATmega256/128/64RFR2 provides the following features: 256K/128K/64K Bytes of In-System Programmable (ISP) Flash with read-while-write capabilities, 8K/4K/2K Bytes EEPROM, 32K/16K/8K Bytes SRAM, up to 35 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), 6 flexible Timer/Counters with compare modes and PWM, a 32 bit Timer/Counter, 2 USART, a byte oriented 2-wire Serial Interface, a 8 channel, 10 bit analog to digital converter (ADC) with an optional...
Page 5: Pin Descriptions
Software in the boot Flash section will continue to run while the application Flash section is updated, providing true Read-While-Write operation. By combining an 8 bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega256/128/64RFR2 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
Page 6 current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port also provides functions various special features ATmega256/128/64RFR2. 3.2.10 Port F (PF7...PF0) Port F is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
Page 7: Unused Pins
The ATmega256/128/64RFR2 uses the same package as the ATmega128RFA1. 4 Resources A comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com. 5 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device.
Page 8: Endurance Of The Data Memory (Eeprom)
• 125°C – 10,000 Write/Erase cycles • 85° C – 25,000 Write/Erase cycles 6.3 Endurance of the Data Memory (EEPROM) The endurance of the entire data memory (EEPROM) is • 125°C – 20,000 Write/Erase cycles • 85° C – 50,000 Write/Erase cycles •...
Page 9: Avr Cpu Core
ATmega256/128/64RFR2 7 AVR CPU Core 7.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculation, control peripherals, and handle interrupts. 7.2 Architectural Overview Figure 7-1.Block Diagram of the AVR Architecture Data Bus 8-bit...
Page 10: Alu - Arithmetic Logic Unit
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File –...
Page 11: Status Register
ATmega256/128/64RFR2 7.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference.
Page 12: General Purpose Register File
stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. 7.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: •...
Page 13: Stack Pointer
ATmega256/128/64RFR2 Figure 7-2. The X-, Y-, Z-registers In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls.
Page 14 The AVR Stack Pointer is implemented as two 8-bit registers SPL and SPH in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed.
Page 15: Instruction Execution Timing
ATmega256/128/64RFR2 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. 7.6.4 EIND – Extended Indirect Register $3C ($5C) EIND0 EIND Read/Write...
Page 16 interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security.
Page 17 ATmega256/128/64RFR2 Assembly Code Example C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMPE); /* start EEPROM write */ EECR |= (1<<EEPE); SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
Page 18: Avr Memories
8 AVR Memories This section describes the different memories in the ATmega256/128/64RFR2. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega256/128/64RFR2 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.1 In-System Reprogrammable Flash Program Memory The ATmega256/128/64RFR2 contains 256K/128K/64K Bytes On-chip In-System Reprogrammable Flash memory for program storage, see...
Page 19 ATmega256/128/64RFR2 the IN and OUT instructions. For the Extended I/O space from $060 – $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The first Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 416 locations of Extended I/O memory and the following locations address the internal data SRAM.
Page 20: Eeprom Data Memory
Figure 8-8. On-Chip Data SRAM Access Cycles Address Address valid Compute Address Data Data Memory Access Instruction Next Instruction 8.3 EEPROM Data Memory The ATmega256/128/64RFR2 contains 8K/4K/2K Bytes of data EEPROM memory. It is organized as a separate data space. Read access is byte-wise. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
Page 21 ATmega256/128/64RFR2 The subsequent code examples show assembly and C functions for programming the EEPROM with separate and combined (atomic) erase/write operations respectively. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software.
Page 22 call EEPROM_write … C Code Example (Single Byte Programming) void EEPROM_write(unsigned int uiAddress, unsigned char ucData) /* Wait for completion of previous erase/write */ while(EECR & (1<<EEPE)) /* Set up address */ EEAR = uiAddress; EEDR = 255; /* Write logical one to EEMPE and enable erase only*/ EECR = (1<<EEMPE) + (1<<EEPM0);...
Page 23 ATmega256/128/64RFR2 C Code Example (Atomic Operation) void EEPROM_atomic_write(unsigned int uiAddress, unsigned char ucData) /* Wait for completion of previous write */ while(EECR & (1<<EEPE)) /* Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE);...
Page 24 The programming time can be reduced if an entire 8 byte EEPROM page is programmed instead of single bytes. In this case the data has to be loaded into the page buffer first. The page buffer will auto-erase after a write or erase operation. It is also erased after a system reset.
Page 25 ATmega256/128/64RFR2 while(EECR & (1<<EEPE)); // wait finish of previous erase/write EEAR = uiAddress; // set up address EEDR = 255; // data for erase do { EECR = (1<<EEMPE) + (3<<EEPM0); // enable buffer load only EECR |= (1<<EEPE); // start EEPROM loading while(EECR &...
Page 26: Eeprom Register Description
8.3.2 Preventing EEPROM Corruption During periods of low DEVDD, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.
Page 27 ATmega256/128/64RFR2 8.4.3 EEDR – EEPROM Data Register $20 ($40) EEDR7:0 EEDR Read/Write Initial Value For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.
Page 28: I/O Memory
The EEPROM Programming Enable Signal EEPE is the write strobe to the EEPROM. It triggers either the programming or the page buffer loading. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM.
Page 29: General Purpose I/O Registers
ATmega256/128/64RFR2 must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega256/128/64RFR2 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 –...
Page 30: Other Port Registers
The three General Purpose I/O Registers can be used for storing any information. • Bit 7:0 – GPIOR27:20 - General Purpose I/O Register 2 Value 8.7 Other Port Registers The inherited control registers of missing ports located in the I/O space are kept in the ATmega256/128/64RFR2.
Page 31 ATmega256/128/64RFR2 8.7.4 PORTC – Port C Data Register $08 ($28) PORTC7:0 PORTC Read/Write Initial Value The PORTC register can be used as a General Purpose I/O Register for storing any information. • Bit 7:0 – PORTC7:0 - Port C Data Register Value 8.7.5 DDRC –...
Page 32: Low-Power 2.4 Ghz Transceiver
9 Low-Power 2.4 GHz Transceiver 9.1 Features • High performance RF-CMOS 2.4 GHz radio transceiver targeted for IEEE 802.15.4™, ZigBee™, IPv6 / 6LoWPAN, RF4CE, SP100, WirelessHART™ and ISM applications • Outstanding link budget (103.5 dB): Receiver sensitivity -100 dBm Programmable output power from -17 dBm up to +3.5 dBm •...
Page 33: General Circuit Description
ATmega256/128/64RFR2 The ATmega256/128/64RFR2 features a low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4, 6LoWPAN, RF4CE and high data rate 2.4 GHz ISM band applications. The radio transceiver is a true peripheral block of the AVR microcontroller. All RF-critical components except the antenna, crystal de-coupling capacitors integrated...
Page 34: Transceiver To Microcontroller Interface
The received RF signal at pins RFN and RFP is differentially fed through the low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (RX ADC) and generates a digital RSSI signal.
Page 35 ATmega256/128/64RFR2 That means if the controller runs with about 16MHz or faster, at least three wait cycles are generated, but if the controller runs with about 4MHz, no wait cycles are inserted. A register access is only possible, if the transceiver clock is available. Otherwise it returns 0x00 regardless of the current register content.
Page 36 Atmel standalone transceiver devices (two chip solution). The register (TRXRST) can be used to reset the transceiver without resetting the controller. After the reset bit was set, it is cleared immediately. A second configuration bit (SLPTR) is used to control frame transmission or sleep and wakeup of the transceiver.
Page 37 ATmega256/128/64RFR2 Table 9-2. Interrupt Description in Basic Operating Mode IRQ Vector IRQ Name Description Section Number/ Priority TRX24_AWAKE Indicates radio transceiver reached TRX_OFF "TRX_OFF – Clock State" on page 40 state RESET, or SLEEP states TRX24_TX_END Indicates the completion of a frame "Frame Transmit Procedure"...
Page 38: Operating Modes
9.3.4 TX Start Interrupt When the TRX24 starts a frame transmission a TRX24_TX_START interrupt is issued when the preamble starts. Table 9-3. Interrupt Description for TX_START interrupt IRQ Vector IRQ Name Description enable Number/ Priority TRX24_TX_START Indicates the start of a preamble transmission. set bit TX_START in register IRQ_MASK1 When enabled, the TX_START interrupt is issued in both basic operating modes and extended operating modes.
Page 39 ATmega256/128/64RFR2 Figure 9-3. Basic Operating Mode State Diagram (for timing refer to Table 9-4 on page S L E E P ( S le e p S ta te ) X O S C = O F F ( fro m a ll s ta te s ) T R X R S T = 1 T R X _ O F F F O R C E _ T R X _ O F F...
Page 40 active processes, and forces an immediate transition to TRX_OFF. In contrast a TRX_OFF command is stored until an active state (receiving or transmitting) has been finished. After that the transition to TRX_OFF is performed. For a fast transition from receive or active transmit states to PLL_ON state the command FORCE_PLL_ON is provided.
Page 41 ATmega256/128/64RFR2 9.4.1.2.4 RX_ON and BUSY_RX – RX Listen and Receive State In RX_ON state the receiver blocks and the PLL frequency synthesizer are enabled. The receive mode is internally separated into the RX_ON and BUSY_RX states. There is no difference between these states with respect to the analog radio transceiver circuitry, which are always turned on.
Page 42 A reset forces the radio transceiver into the TRX_OFF state. A reset is initiated by a ATmega256/128/64RFR2 main reset (see "Resetting the AVR" on page 209) or a radio transceiver reset (see "Transceiver Pin Register TRXPR" on page 35). During radio transceiver reset the TRXPR register is not cleared and therefore the application software has to set the SLPTR bit to “0”.
Page 43 ATmega256/128/64RFR2 Figure 9-14. Timing of TRX24_RX_START, TRX24_XAH_AMI, TRX24_TX_END and TRX24_RX_END Interrupts in Basic Operating Mode - 1 6 1 2 8 1 6 0 1 9 2 1 9 2 + ( 9 + m ) * 3 2 T i m e [ µ s ] T R X _ S T A T E P L L _ O N B U S Y _ T X...
Page 44 During this wake-up procedure the calibration of the filter-tuning network (FTN) is performed. Entering TRX_OFF state is signaled by the TRX24_AWAKE interrupt, if enabled. 9.4.1.4.2 PLL_ON and RX_ON States The transition from TRX_OFF to PLL_ON and RX_ON mode is shown in Figure 9-16 below.
Page 45 ATmega256/128/64RFR2 = 16 µs after initiating the transmission, the radio transceiver changes into TR10 BUSY_TX state and the internally generated SHR is transmitted. After that the PSDU data are transmitted from the Frame Buffer. After completing the frame transmission, indicated by the TRX24_TX_END interrupt, the PLL settles back to the receive frequency within t = 32 µs in state PLL_ON.
Page 46 9.4.1.4.5 State Transition Timing Summary The transition numbers correspond to Table 9-4 below. See measurement setup in "Basic Application Schematic" on page 540. Table 9-4. Radio Transceiver State Transition Timing Symbol Transition Time [µs], (typ) Comments Depends on crystal oscillator setup (CL = 10 pf) SLEEP TRX_OFF TRX_OFF state indicated by TRX24_AWAKE interrupt...
Page 47 ATmega256/128/64RFR2 Symbol Block Time [µs], (typ) Time [µs], (max) Comments PLL, TX Maximum PLL settling time TX TR24 RSSI update period in receive states, refer to "Reading RSSI, update RSSI" on page 74 TR25 ED measurement period, refer to "Measurement Description"...
Page 48 frame pending subfield in the received acknowledgement frame the transaction status is set according to Table 9-19 on page 64. The state diagram including the Extended Operating Mode states is shown in Figure 9- below. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode.
Page 49 ATmega256/128/64RFR2 9.4.2.1 State Control The Extended Operating Mode states RX_AACK and TX_ARET are controlled via the bits TRX_CMD of register TRX_STATE, which receives the state transition commands. The states are entered from TRX_OFF or PLL_ON state as illustrated in Figure 9-19 on page 48.
Page 50 Handling of Pending Data Indicator Characterize as PAN coordinator Handling of Slotted Acknowledgement • Additional Frame Filtering Properties (register XAH_CTRL_1, CSMA_SEED_1) Promiscuous Mode Enable or disable automatic ACK generation Handling of reserved frame types The addresses for the address match algorithm are to be stored in the appropriate address registers.
Page 51 ATmega256/128/64RFR2 Generally, at nodes, configured as a normal device or PAN coordinator, a frame is not indicated if the frame filter does not match and the FCS is invalid. Otherwise, the TRX_24_RX_END interrupt is issued after the completion of the frame reception. The microcontroller can then read the frame.
Page 52 Figure 9-20. Flow Diagram of RX_AACK TRX_STATE = RX_AACK_ON SHR detected TRX_STATE = BUSY_RX_AACK Generate TRX24_RX_START interrupt Scanning MHR Promiscuous Mode Reserved Frames Frame Filtering Note 1: Fram e Filtering, Prom iscuous Mode and (see Note 1) Frame reception Reserved Fram es: - A radio transceiver in Prom iscuous Generate TRX24_XAH_AMI M ode, or configured to receive Reserved...
Page 53 ATmega256/128/64RFR2 9.4.2.3.1 Description of RX_AACK Configuration Bits Overview The following table summarizes all register bits which affect the behavior of a RX_AACK transaction. For address filtering it is further required to setup address registers to match to the expected address. Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior to switching to RX_AACK mode.
Page 54 9.4.2.3.2 Configuration of IEEE Scenarios Normal Device Table 9-7 below shows a typical RX_AACK configuration of an IEEE 802.15.4 device operated as a normal device rather than a PAN coordinator or router. Table 9-7. Configuration of IEEE 802.15.4 Devices Register Name Register Bits Description SHORT_ADDR_0/1...
Page 55 ATmega256/128/64RFR2 Table 9-8. Configuration of a PAN Coordinator Register Name Register Bits Description SHORT_ADDR_0/1 Set node addresses PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 RX_SAFE_MODE 0: disable frame protection 1: enable frame protection SLOTTED_OPERATION 0: if transceiver works in unslotted mode 1: if transceiver works in slotted mode AACK_I_AM_COORD 1: device is PAN coordinator AACK_SET_PD...
Page 56 Register Name Register Bits Description AACK_FVN_MODE Controls the ACK behavior, depends on FCF frame version number 0x00 : acknowledges only frames with version number 0, i.e. according to IEEE 802.15.4-2003 frames 0x01 : acknowledges only frames with version number 0 or 1, i.e. frames according to IEEE 802.15.4-2006 0x10 : acknowledges only frames with version number 0 or 1 or 2...
Page 57 ATmega256/128/64RFR2 Reception of Reserved Frames Frames with reserved frame types (see section Table 9-19 on page 69) can also be handled in RX_AACK mode. This might be required when implementing proprietary, non-standard compliant protocols. It is an extension of the address filtering in RX_AACK mode.
Page 58 If AACK_FLT_RES_FT = 1 any frame with a reserved frame type is filtered by the address filter similar to a data frame as described in the standard. Consequently, a TRX24_AMI interrupt is generated upon address match. A TRX24_RX_END interrupt is only generated if the address matched and the frame was not corrupted.
Page 59 ATmega256/128/64RFR2 2. At least one address field must be configured. Address match, indicated by the TRX24_AMI interrupt is further controlled by the content of subfields of the frame control field of a received frame according to the following rule: If (Destination Addressing Mode = 0 OR 1) AND (Source Addressing Mode = 0) no TRX24_AMI interrupt is generated, refer to Figure 9-27 on page 69.
Page 60 Figure 9-11. Example Timing of an RX_AACK Transaction for Slotted Operation 51 2 7 04 1 026 tim e [µ s] F ram e T ype D ata Fram e (Length = 10, A C K = 1) A C K F ram e S F D T R X_ ST AT E R X _A A C K _O N...
Page 61 ATmega256/128/64RFR2 configured by a short address and pan ID. The IEEE 64 bit address is the same for every filter block. There are some separate configuration bits for every filter block (see Table 9-13 below). Table 9-13. Additional register set for Multiple Address Filter Register Name Description {MAFSA0H,MAFSA0L}...
Page 62 Interrupt Name Description TRX24_AMI3 address match interrupt from address filter #3, enabled bit AMI3 in register IRQ_MASK1 is set Note: If bit AMI_EN is set in register IRQ_MASK, interrupt TRX24_XAH_AMI occures if any of the four filter detects an address match. It is not allowed to configure two enabled address filter to the same short address and PAN.
Page 63 ATmega256/128/64RFR2 9.4.2.6 TX_ARET_ON – Transmit with Automatic Retry and CSMA-CA Retry Figure 9-13. Flow Diagram of TX_ARET T R X _ S T A T E = T X _ A R E T _ O N fra m e _ rctr = 0 S ta rt T X T R X _ S T A T E = B U S Y _ T X _ A R E T T R A C _ S T A T U S = IN V A L ID...
Page 64 Overview The implemented TX_ARET algorithm is shown in Figure 9-13 on page 63. In TX_ARET mode, the radio transceiver first executes the CSMA-CA algorithm, as defined by IEEE 802.15.4–2006, section 7.5.1.4, initiated by a transmit start event. If the channel is IDLE a frame is transmitted from the Frame Buffer. If the acknowledgement frame is requested the radio transceiver additionally checks for an ACK reply.
Page 65 ATmega256/128/64RFR2 Value Name Description NO_ACK No acknowledgement frames were received during all retry attempts INVALID Entering TX_ARET mode sets TRAC_STATUS = 7 Note that if no ACK is expected (according to the content of the received frame in the Frame Buffer), the radio transceiver issues a TRX24_TX_END interrupt directly after the frame transmission has been completed.
Page 66 Table 9-16. Interrupt Handling in Extended Operating Mode Mode Interrupt Description RX_AACK TRX24_RX_START Indicates a PHR reception TRX24_AMI Issued at address match TRX24_RX_END Signals completion of RX_AACK transaction if successful A received frame must pass the address filter; The FCS is valid TX_ARET TRX24_TX_END Signals completion of TX_ARET transaction...
Page 67: Functional Description
ATmega256/128/64RFR2 Register Name Description IEEE_ADDR_7 …. IEEE_ADDR_0 Address filter configuration PAN_ID_1 Short address, PAN-ID and IEEE address PAN_ID_0 SHORT_ADDR_1 SHORT_ADDR_0 XAH_CTRL_0 TX_ARET control, retries value control CSMA_SEED_0 CSMA-CA seed value CSMA_SEED_1 CSMA-CA seed value, RX_AACK control CSMA_BE CSMA-CA back-off exponent control 9.5 Functional Description 9.5.1 Introduction –...
Page 68 On receive the PHR is returned as the first octet during Frame Buffer read access, the most significant bit always set to 0. For IEEE 802.15.4 compliant operation bit 8 has to be masked by software. The reception of a valid PHR is signaled by a TRX24_RX_START interrupt.
Page 69 ATmega256/128/64RFR2 9.5.1.2.2 Frame Control Field (FCF) The FCF consists of 16 bits, and occupies the first two octets of either the MPDU or the PSDU, respectively. Figure 9-27. IEEE 802.15.4-2006 Frame Control Field (FCF) Bit [2:0]: describe the frame type. Table 9-19 below summarizes frame types defined by IEEE 802.15.4, section 7.2.1.1.1.
Page 70 Bit 6: the “Intra-PAN” subfield indicates that in a frame, where both, the destination and source addresses are present, the PAN-ID of the source address filed is omitted. In RX_AACK mode this bit is evaluated by the address filter logic of the radio transceiver. Bit [11:10]: the “Destination Addressing Mode”...
Page 71 ATmega256/128/64RFR2 9.5.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006 All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003 with two exceptions: a coordinator realignment command frame with the “Channel Page” field present (see IEEE 802.15.4- 2006 7.3.8) frame...
Page 72 subfield b3 is set to one (see section "Frame Compatibility between IEEE 802.15.4- 2003 and IEEE 802.15.4-2006" on page 71). For details of its structure see IEEE 802.15.4-2006, 7.6.2 Auxiliary security header. 9.5.1.2.7 MAC Service Data Unit (MSDU) This is the actual MAC payload. It is usually structured according to the individual frame type.
Page 73 ATmega256/128/64RFR2 Example: Consider a 5 octet ACK frame. The MHR field consists of 0100 0000 0000 0000 0101 0110. The leftmost bit (b ) is transmitted first in time. The FCS is in this case 0010 0111 1001 1110. The leftmost bit (r ) is transmitted first in time.
Page 74 received signal strength is evaluated. The RSSI provides the basis for an ED measurement. See section "Energy Detection (ED)" below for details. 9.5.3.2 Reading RSSI In Basic Operating Mode the RSSI value is valid in any receive state, and is updated every t = 2 µs to register PHY_RSSI.
Page 75 ATmega256/128/64RFR2 For High Data Rate Modes the automated ED measurement duration is reduced to 32 µs as described in "High Data Rate Modes" on page 93. The measurement period in these modes is still 128 µs for manually initiated ED measurements as long as the receiver is in RX_ON state.
Page 76 = -90 + ED [dBm] Figure 9-19. Mapping between values in PHY_ED_LEVEL and Received Input Power Measured Ideal -100 Register PHY_ED_LEVEL Value 9.5.4.4 Interrupt Handling The TRX24_CCA_ED_DONE interrupt is issued at the end of a manually initiated ED measurement. Note that an ED request should only be initiated in one of the receive states. Otherwise the radio transceiver generates a TRX24_CCA_ED_DONE interrupt but no ED measurement was performed.
Page 77 ATmega256/128/64RFR2 CCA Mode Description 0, 3 Carrier sense with energy above threshold. CCA shall report a busy medium using a logical combination of Detection of a signal with the modulation and spreading characteristics of this standard and Energy above the ED threshold. Where the logical operator may be configured as either OR (mode 0) or AND (mode 3).
Page 78 9.5.5.5 Measurement Time The response time for a manually initiated CCA measurement depends on the receiver state. In RX_ON state the CCA measurement is done over eight symbol periods and the result is accessible 140 µs after the request (see section "Configuration and CCA Request"...
Page 79 ATmega256/128/64RFR2 can be associated with an expected packet error rate. The PER is the ratio of erroneous received frames to the total number of received frames. A PER of zero indicates no frame error whereas at a PER of one no frame was received correctly. The radio transceiver uses correlation results of multiple symbols within a frame to determine the LQI value.
Page 80: Module Description
Note that the received signal power as indicated by the received signal strength indication (RSSI) value or energy detection (ED) value of the radio transceiver do not characterize the signal quality and the ability to decode a signal. As an example, a received signal with an input power of about 6 dB above the receiver sensitivity likely results in a LQI value close to 255 for radio channels with very low signal distortions.
Page 81 ATmega256/128/64RFR2 converter (RX ADC) and generates a digital RSSI signal. The ADC output signal is sampled and processed further by the digital base band receiver (RX BBP). The RX BBP performs additional signal filtering and signal synchronization. The frequency offset of each frame is calculated by the synchronization unit and is used during the remaining receive process to correct the offset.
Page 82 9.6.2 Transmitter (TX) 9.6.2.1 Overview The transmitter consists of a digital base band processor (TX BBP) and an analog front end as shown in the following figure. Figure 9-22. Transmitter Block Diagram $0140 Ext. R F front-end and Control R egisters D IG3/4 Output Power C ontrol $017F...
Page 83 ATmega256/128/64RFR2 Figure 9-23. TX Power Ramping When using en external RF front-end (refer to "RX/TX Indicator" on page 97) it may be required to adjust the startup time of the external PA relative to the internal building blocks to optimize the overall PSD. This can be achieved by PARCR register in the bits PALTU/PALTD.
Page 84 • Bit PRTRX24 in register "PRR1 – Power Reduction Register 1" on page 198 is not set; By default there is no protection of the Frame Buffer against overwriting. If a frame is received during a Frame Buffer read access of a previously received frame, the stored data might be overwritten.
Page 85 ATmega256/128/64RFR2 preamble and the SFD field. The variable frame section contains the PHR and the PSDU including the FCS (see "Overview" on page 72). The Frame Buffer content differs depending on the direction of the communication (receive or transmit). To access the data follow the procedures described in "Radio Transceiver Usage"...
Page 86 9.6.4.2 Configuration The Battery Monitor can be configured using the BATMON register. Register subfield BATMON_VTH sets the threshold voltage. It is configurable with a resolution of 75 mV in the upper voltage range (BATMON_HR = 1) and with a resolution of 50 mV in the lower voltage range (BATMON_HR = 0).
Page 87 ATmega256/128/64RFR2 oscillator should be selected carefully and the related board layout should be done with caution as described in section "Application Circuits" on page 540. The register XOSC_CTRL provides access to the control signals of the oscillator. Two operating modes are supported. It is recommended to use the integrated oscillator setup as described in Figure 9-26 below.
Page 88 necessary for a robust oscillation during stable operation. This also keeps the drive level of the crystal low. Crystals with a higher load capacitance are generally less sensitive to parasitic pulling effects caused by variations of external components or board and circuit parasitics. On the other hand a larger crystal load capacitance results in a longer start-up time and a higher steady state current consumption.
Page 89 ATmega256/128/64RFR2 The PLL frequency is changed to the transmit frequency within t = 16 µs after TR23 starting the transmit procedure and before starting the transmission. After the transmission the PLL settles back to the receive frequency within t = 32 µs. This TR24 frequency step does not generate a TRX24_PLL_LOCK or TRX24_PLL_UNLOCK interrupt within these time spans.
Page 90: Radio Transceiver Usage
Additionally, the PLL supports all frequencies from 2322 MHz to 2527 MHz with 500 kHz frequency spacing. The frequency is selected by CC_BAND (see "CC_CTRL_1 – Channel Control Register 1" on page 136) and CC_NUMBER (see "CC_CTRL_0 – Channel Control Register 0" on page 136).
Page 91 ATmega256/128/64RFR2 enabled. The frame reception is completed when issuing the TRX24_RX_END interrupt. Different Frame Buffer read access scenarios are recommended for: • Non-time critical applications: read access starts after the TRX24_RX_END interrupt; • Time-critical applications: read access starts after the TRX24_RX_START interrupt; The controller must ensure to read valid Frame Buffer contents.
Page 92: Radio Transceiver Extended Feature Set
Figure 9-29. Transaction between radio transceiver and microcontroller during transmit Write frame data (Frame Buffer access) Write TRX_CMD = TX_START, or write SLPTR (Register access) IRQ issued (TX_END) Alternatively a frame transmission can be started first, followed by the Frame Buffer write access (PSDU data) as shown in Figure 9-30 below.
Page 93 ATmega256/128/64RFR2 Note, if the PLL is not locked or unlocks in receive states or either antenna diversity or RPC mode is enabled, the RND_VALUE is zero. 9.8.2 High Data Rate Modes The main features of the High Data Rate Modes are: •...
Page 94 Figure 9-31. High Data Rate Frame Structure 1472 2752 time [µs] 250 kb/s PSDU: 80 octets 500 kb/s PSDU: 80 octets 1000 kb/s PSDU: 80 octets 2000 kb/s PSDU: 80 octets The effective data rate is smaller than the selected data rate due to the overhead caused by the SHR, the PHR and the FCS.
Page 95 ATmega256/128/64RFR2 9.8.2.5 High Data Rate Mode Options Receiver Sensitivity Control The different data rates between PPDU header (SHR and PHR) and PHY payload (PSDU) cause a different sensitivity between header and payload. This can be adjusted by defining sensitivity threshold levels of the receiver. The receiver does not receive frames with an RSSI level below the defined sensitivity threshold level (register bits RX_PDT_LEVEL >...
Page 96 Antenna Diversity uses two antennas to switch to the most reliable RF signal path. This is done by the radio transceiver during RX_ON and RX_AACK_ON state without interaction of the application software. Both antennas should be carefully separated from each other to ensure highly independent receive signals. Antenna Diversity can be used in Basic and Extended Operating Modes and can also be combined with other features and operating modes like High Data Rate Mode and RX/TX Indication.
Page 97 ATmega256/128/64RFR2 An application software defined selection of a certain antenna can be done by disabling the automatic Antenna Diversity algorithm (ANT_DIV_EN = 0) and selecting one antenna using register bit ANT_CTRL. If the radio transceiver is not in a receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN and to set the port pins DIG1 and DIG2 to output low via the I/O port control register (DDG1 = 1, PORTG1 = 0, DDF2 = 1, PORTF2 = 0).
Page 98 9.8.4.2 External RF-Front End Control The setup time of the external power amplifier (PA) relative to the internal building blocks should be adjusted when using an external RF front-end including a power amplifier to optimize the overall power spectral density (PSD) mask. Figure 9-35.
Page 99 ATmega256/128/64RFR2 The register SFD_VALUE contains the one octet start-of-frame delimiter (SFD) to synchronize to a received frame. It is not recommended to set the low-order 4 bits to 0 due to the way the SHR is formed. 9.8.7 Dynamic Frame Buffer Protection The ATmega256/128/64RFR2 continues the reception of incoming frames as long as it is in any receive state.
Page 100 Register Name Description AES_CTRL AES control register AES_KEY Access to 16 Byte key buffer AES_STATE Access to 16 Byte data buffer 9.8.8.2 Security Module Preparation The use of the security module requires a configuration of the security engine before starting a security operation. The following steps are required: Table 9-29.
Page 101 ATmega256/128/64RFR2 The operation takes 24 µs and the completed encryption/ decryption is indicated by the AES_READY IRQ and the AES_DONE bit. The internal byte counter of the key and data buffer is cleared and the resulting data can be read out. For additional information about the key and data buffer please refer to section "AES_KEY –...
Page 102 Figure 9-36. ECB Mode - Encryption Plaintext Plaintext Encryption Encryption Block Cipher Block Cipher Encryption Encryption Ciphertext Ciphertext Figure 9-37. ECB Mode - Decryption Ciphertext Ciphertext Decryption Block Cipher Decryption Block Cipher Decryption Decryption Plaintext Plaintext Due to the nature of AES algorithm the initial key to be used when decrypting is not the same as the one used for encryption.
Page 103 ATmega256/128/64RFR2 Figure 9-38. CBC Mode - Encryption Plaintext Initialization Vector (IV) Plaintext Encryption Encryption Block Cipher Block Cipher Encryption Encryption Ciphertext Ciphertext mode mode After preparing the AES key and defining the AES operation direction register bit AES_DIR, the data has to be provided to the AES engine and the CBC operation can be started.
Page 104 If AES_IM is not set, the processing status can be polled by software (AES_STATUS register), but no Interrupt occurs. 9.8.9 Receiver Override The RX Override feature improves the network throughput under busy conditions. When an incoming received frame is overlayed by a later starting stronger signal, the overlayed signal would surely destroy the received frame.
Page 105 ATmega256/128/64RFR2 Applicable to states: RX_ON, RX_AACK_ON and TX_ARET_ON SRT reduces the average power consumption during RX listening periods. In typical environment situations SRT reduces the average current consumption of the transceiver in the RX_ON state by up to 50%. The configuration of SRT is done with the RX_RPC_CTRL bits of register TRX_RPC.
Page 106 2. If the PAN address matches (but not the short destination address), the radio transceiver enters power saving mode for the remaining frame. If acknowledgement is also requested, power saving continues through the acknowledgement period. . Notes: 1. PAM is applicable to short acknowledgement times and reserved frame types as set by the bits AACK_ACK_TIME and AACK_FLTR_RES_FT of register XAH_CTRL_1, respectively (see "XAH_CTRL_1 –...
Page 107: Continuous Transmission Test Mode
ATmega256/128/64RFR2 9.9 Continuous Transmission Test Mode 9.9.1 Overview The 2.4GHz transceiver offers a Continuous Transmission Test Mode to support final application / production tests as well as certification tests. In this test mode the radio transceiver transmits continuously a previously transferred frame (PRBS mode) or a continuous wave signal (CW mode).
Page 108: Abbreviations
Step Action Register Value Description Register Access PHY_TX_PWR 0x00 Set TX output power, e.g. to P Register Access TRX_STATUS 0x08 Verify TRX_OFF state Register Access TST_CTRL_DIGI 0x0F Enable Continuous Transmission Test Mode – step # 1 Register Access TRX_CTRL_2 0x03 Enable High Data Rate Mode, 2 Mb/s Register Access...
Page 109 ATmega256/128/64RFR2 Automated gain control Advanced encryption standard ARET Automatic retransmission AVREG Voltage regulator for analog building blocks AWGN Additive White Gaussian Noise BATMON Battery monitor Base band processor Band pass filter Cipher block chaining Cyclic redundancy check Clear channel assessment CSMA-CA Carrier sense multiple access/Collision avoidance Continuous wave...
Page 110: Reference Documents
O-QPSK Offset - quadrature phase shift keying Power amplifier Personal area network Printed circuit board Packet error rate PHY header Physical layer Phase locked loop Power-on reset Poly-phase filter PRBS Pseudo random bit sequence PSDU PHY service data unit Power spectral mask Quad flat no-lead package Radio frequency RSSI...
Page 111: Register Description
ATmega256/128/64RFR2 ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Human Body Model (HBM). ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Charged Device Model (CDM). NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 9.12 Register Description...
Page 112 • Bit 1:0 – Res1:0 - Reserved Bit These bits are reserved for future use. The result of a read access is undefined. The register bits must always be written with the reset value. 9.12.2 AES_STATUS – AES Status Register NA ($13D) AES_ER Res5...
Page 113 ATmega256/128/64RFR2 The AES key register accesses a 128 Bit internal buffer that holds the Encryption or Decryption Key. The AES_KEY buffer is a 16 Byte buffer. The buffer is accessed by reading or writing 16 fold to the same address location (AES_KEY). A read access to registers AES_KEY returns the last round key of the preceding security operation.
Page 114 Table 9-36 TST_STATUS Register Bits Register Bits Value Description TST_STATUS Test mode is disabled. Test mode is active. • Bit 4:0 – TRX_STATUS4:0 - Transceiver Main Status The register bits TRX_STATUS signal the current radio transceiver status. Do not try to initiate further state...
Page 115 ATmega256/128/64RFR2 TRAC_STATUS is valid 2us after the respective procedure is finished by TX_END or RX_END IRQ). Details of the algorithm and a description of the status information are given in the RX_AACK_ON and TX_ARET_ON sections of the data-sheet. Even though the reset value for register bits TRAC_STATUS is 0, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when it is started.
Page 116 9.12.7 TRX_CTRL_0 – Tranceiver Control Register 0 NA ($143) Res7 PMU_EN PMU_START PMU_IF_INV TRX_CTRL_0 Read/Write Initial Value NA ($143) Res3 Res2 Res1 Res0 TRX_CTRL_0 Read/Write Initial Value The TRX_CTRL_0 register is a multi purpose register to control various operating modes and settings of the radio transceiver. •...
Page 117 ATmega256/128/64RFR2 is high. It is recommended to set PA_EXT_EN=1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external RF switches or other building blocks especially during SLEEP state. • Bit 6 – IRQ_2_EXT_EN - Connect Frame Start IRQ to TC1 When this bit is set to one the capture input of Timer/Counter 1 is connected to the RX frame start signal and pin DIG2 becomes an output, driving the RX frame start signal.
Page 118 Register Bits Value Description -6.5 dBm -8.5 dBm -11.5 dBm -16.5 dBm 9.12.10 PARCR – Power Amplifier Ramp up/down Control Register NA ($138) PALTD2 PALTD1 PALTD0 PALTU2 PALTU1 PALTU0 PARDFI PARUFI PARCR Read/Write Initial Value This Register controls the power up and power down behavior of the Power Amplifier. •...
Page 119 ATmega256/128/64RFR2 If this bit is clear, the PLL frequency is -500kHz (relative to carrier) while PA is ramping up and +500kHz otherwise. 9.12.11 PHY_RSSI – Receiver Signal Strength Indicator Register NA ($146) RX_CRC_VALID RND_VALUE1 RND_VALUE0 RSSI4 PHY_RSSI Read/Write Initial Value NA ($146) RSSI3 RSSI2...
Page 120 9.12.12 PHY_ED_LEVEL – Transceiver Energy Detection Level Register NA ($147) ED_LEVEL7 ED_LEVEL6 ED_LEVEL5 ED_LEVEL4 PHY_ED_LEVEL Read/Write Initial Value NA ($147) ED_LEVEL3 ED_LEVEL2 ED_LEVEL1 ED_LEVEL0 PHY_ED_LEVEL Read/Write Initial Value This register contains the result of an Energy Detection measurement. • Bit 7:0 – ED_LEVEL7:0 - Energy Detection Level The minimum ED value (ED_LEVEL = 0) indicates a receiver power less than or equal to RSSI_BASE_VAL.
Page 121 ATmega256/128/64RFR2 CCA_REQUEST. The register bit is automatically cleared after requesting a CCA measurement with CCA_REQUEST=1. • Bit 6:5 – CCA_MODE1:0 - Select CCA Measurement Mode The CCA mode can be selected using these register bits. Note that IEEE 802.15.4- 2006 CCA Mode 3 defines the logical combination of CCA Mode 1 and 2 with the logical operators AND or OR.
Page 122 NA ($149) CCA_CS_THRES1 CCA_CS_THRES0 CCA_THRES Read/Write Initial Value NA ($149) CCA_ED_THRES3 CCA_ED_THRES2 CCA_THRES Read/Write Initial Value NA ($149) CCA_ED_THRES1 CCA_ED_THRES0 CCA_THRES Read/Write Initial Value This register sets the threshold level for the Energy Detection (ED) of the Clear Channel Assessment (CCA). •...
Page 123 ATmega256/128/64RFR2 Register Bits Value Description SDM mode 2 selected (Mash 1-1), DCU turned on SDM mode 2 with random ACCU2 • Bit 5 – ACR_MODE - Adjacent Channel Rejection Mode This bit is reserved for internal use. It turns on or off the ACR module. For high rate modes the ACR module will be always disabled.
Page 124 9.12.17 TRX_CTRL_2 – Transceiver Control Register 2 NA ($14C) RX_SAFE_MODE Res4 Res3 Res2 TRX_CTRL_2 Read/Write Initial Value NA ($14C) Res1 Res0 OQPSK_DATA_RATE1 OQPSK_DATA_RATE0 TRX_CTRL_2 Read/Write Initial Value This register controls the data rate setting of the radio transceiver. • Bit 7 – RX_SAFE_MODE - RX Safe Mode If this bit is set, the next received frame will be protected and not overwritten by following frames.
Page 125 ATmega256/128/64RFR2 Table 9-52 ANT_SEL Register Bits Register Bits Value Description ANT_SEL Antenna 0 Antenna 1 • Bit 6:4 – Res2:0 - Reserved • Bit 3 – ANT_DIV_EN - Enable Antenna Diversity If this register bit is set the Antenna Diversity algorithm is enabled. On reception of a frame the algorithm selects an antenna autonomously during SHR search.
Page 126 Register Bits Value Description Antenna Diversity 9.12.19 IRQ_MASK – Transceiver Interrupt Enable Register NA ($14E) AWAKE_EN TX_END_EN AMI_EN CCA_ED_DONE_EN IRQ_MASK Read/Write Initial Value NA ($14E) RX_END_EN RX_START_EN PLL_UNLOCK_EN PLL_LOCK_EN IRQ_MASK Read/Write Initial Value This register is used to enable or disable individual interrupts of the radio transceiver. An interrupt is enabled if the corresponding bit is set to 1.
Page 127 ATmega256/128/64RFR2 This register is used to enable or disable additional interrupts of the radio transceiver. An interrupt is enabled if the corresponding bit is set to 1. All interrupts are disabled after the power up sequence or reset. If an interrupt is enabled it is recommended to read the interrupt status register IRQ_STATUS first to clear the history.
Page 128 This register contains the status of additional pending interrupt requests. An interrupt is pending if the associated bit has a value of one. Such a pending interrupts can be manually cleared by writing a 1 to that register bit. Interrupts are automatically cleared when the corresponding interrupt service routine is being executed.
Page 129 ATmega256/128/64RFR2 Table 9-58 AVREG_TRIM Register Bits Register Bits Value Description AVREG_TRIM1:0 1.80V 1.75V 1.84V 1.88V • Bit 3 – DVREG_EXT - Use External DVDD Regulator This bit may be set in the Register, but is deactivated in the design. The DVREG_EXT functionality to deactivate the digital voltage regulator is no implemented anymore Table 9-59 DVREG_EXT Register Bits Register Bits...
Page 130 This register configures the battery monitor to observe the supply voltage at EVDD. The status of the EVDD supply voltage is accessible by reading bit BATMON_OK with respect to the actual BATMON settings. Furthermore the Battery Monitor Interrupt can be controlled with the bits BAT_LOW and BAT_LOW_EN similar to the function of the IRQ_STATUS and IRQ_MASK register for other radio transceiver interrupts.
Page 131 ATmega256/128/64RFR2 Register Bits Value Description 3.600V / 2.40V (BATMON_HR=1/0) 3.675V / 2.45V (BATMON_HR=1/0) 9.12.25 XOSC_CTRL – Crystal Oscillator Control Register NA ($152) XTAL_MODE3 XTAL_MODE2 XTAL_MODE1 XTAL_MODE0 XOSC_CTRL Read/Write Initial Value NA ($152) XTAL_TRIM3 XTAL_TRIM2 XTAL_TRIM1 XTAL_TRIM0 XOSC_CTRL Read/Write Initial Value This register controls the operation of the 16MHz crystal oscillator.
Page 132 NA ($155) RXO_CFG1 RXO_CFG0 RX_SYN Read/Write Initial Value NA ($155) RX_PDT_LEVEL3 RX_PDT_LEVEL2 RX_SYN Read/Write Initial Value NA ($155) RX_PDT_LEVEL1 RX_PDT_LEVEL0 RX_SYN Read/Write Initial Value This register controls the sensitivity threshold of the receiver. • Bit 7 – RX_PDT_DIS - Prevent Frame Reception RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive modes.
Page 133 ATmega256/128/64RFR2 9.12.27 XAH_CTRL_1 – Transceiver Acknowledgment Frame Control Register 1 NA ($157) Res1 Res0 AACK_FLTR_RES_FT AACK_UPLD_RES_FT XAH_CTRL_1 Read/Write Initial Value NA ($157) AACK_ACK_TIME AACK_PROM_MODE XAH_CTRL_1 Read/Write Initial Value This register is a multi-purpose control register for various RX_AACK settings. • Bit 7:6 – Res1:0 - Reserved Bit This bit is reserved for future use.
Page 134 Register Bits Value Description 2 symbols acknowledgment time • Bit 1 – AACK_PROM_MODE - Enable Promiscuous Mode This register bit enables the promiscuous mode within the RX_AACK mode; refer to IEEE 802.15.4-2006 chapter 7.5.6.5. If this bit is set, every incoming frame with a valid PHR finishes with a RX_END interrupt even if the third level filter rules do not match or the FCS is not valid.
Page 135 ATmega256/128/64RFR2 NA ($15A) PLL_CF3 PLL_CF2 PLL_CF Read/Write Initial Value NA ($15A) PLL_CF1 PLL_CF0 PLL_CF Read/Write Initial Value This register controls the operation of the center frequency calibration loop. Consecutive read/write commands to this register must include a wait time of at least 500ns between each access.
Page 136 9.12.31 CC_CTRL_0 – Channel Control Register 0 NA ($153) CC_NUMBER7 CC_NUMBER6 CC_NUMBER5 CC_NUMBER4 CC_CTRL_0 Read/Write Initial Value NA ($153) CC_NUMBER3 CC_NUMBER2 CC_NUMBER1 CC_NUMBER0 CC_CTRL_0 Read/Write Initial Value This register controls the frequency of the transceiver PLL. CC_CTRL_0 and CC_CTRL_1 form a 16 bit register. Changed CC_CTRL_1 bits are updated only when writing to CC_CTRL_0.
Page 137 ATmega256/128/64RFR2 The register bits RX_RPC_CTRL[1:0] are used for timing calculation within smart receiving mode. Table 9-69 RX_RPC_CTRL Register Bits Register Bits Value Description RX_RPC_CTRL1:0 Activates minimum power saving behaviour for smart receiving mode Reserved Reserved Activates maximum power saving behaviour for smart receiving mode •...
Page 138 Table 9-70 PART_NUM Register Bits Register Bits Value Description PART_NUM7:0 0x94 RFR2 family 9.12.35 VERSION_NUM – Device Identification Register (Version Number) NA ($15D) VERSION_NUM7:0 VERSION_NUM Read/Write Initial Value This register contains the version number of the device. The device identification overwrites the Reset value.
Page 139 Table 9-72 MAN_ID_ Register Bits Register Bits Value Description MAN_ID_17:10 0x00 Atmel JEDEC manufacturer ID, bits [15:8] of 32 bit manufacturer ID: 00 00 00 1F 9.12.38 SHORT_ADDR_0 – Transceiver MAC Short Address Register (Low Byte) NA ($160) SHORT_ADDR_07:00 SHORT_ADDR_0...
Page 140 9.12.41 PAN_ID_1 – Transceiver Personal Area Network ID Register (High Byte) NA ($163) PAN_ID_17:10 PAN_ID_1 Read/Write Initial Value This register contains the upper 8 bits of the MAC PAN ID for Frame Filter address recognition. • Bit 7:0 – PAN_ID_17:10 - MAC Personal Area Network ID These bits contain the bits [15:8] of the MAC PAN ID.
Page 141 ATmega256/128/64RFR2 • Bit 7:0 – IEEE_ADDR_27:20 - MAC IEEE Address These bits map to the bits [23:16] of the 64 bit MAC IEEE address. 9.12.45 IEEE_ADDR_3 – Transceiver MAC IEEE Address Register 3 NA ($167) IEEE_ADDR_37:30 IEEE_ADDR_3 Read/Write Initial Value This register contains the bits [31:24] of the MAC IEEE address for Frame Filter address recognition.
Page 142 9.12.48 IEEE_ADDR_6 – Transceiver MAC IEEE Address Register 6 NA ($16A) IEEE_ADDR_67:60 IEEE_ADDR_6 Read/Write Initial Value This register contains the bits [55:48] of the MAC IEEE address for Frame Filter address recognition. • Bit 7:0 – IEEE_ADDR_67:60 - MAC IEEE Address These bits map to the bits [55:48] of the 64 bit MAC IEEE address.
Page 143 ATmega256/128/64RFR2 • Bit 7:4 – MAX_FRAME_RETRIES3:0 - Maximum Number of Frame Re- transmission Attempts The setting of MAX_FRAME_RETRIES in TX_ARET mode specifies the number of attempts to retransmit a frame when it was not acknowledged by the recipient. The transaction gets canceled if the number of attempts exceeds MAX_FRAME_RETRIES. Table 9-73 MAX_FRAME_RETRIES Register Bits Register Bits Value...
Page 144 9.12.51 CSMA_SEED_0 – Transceiver CSMA-CA Random Number Generator Seed Register NA ($16D) CSMA_SEED_07:00 CSMA_SEED_0 Read/Write Initial Value This register contains the lower 8 bits of the CSMA_SEED. The upper 3 bits are part of register CSMA_SEED_1. CSMA_SEED is the seed for the random number generation that determines the length of the back-off period in the CSMA-CA algorithm.
Page 145 ATmega256/128/64RFR2 Table 9-76 AACK_FVN_MODE Register Bits Register Bits Value Description AACK_FVN_MODE1:0 Acknowledge frames with version number 0 Acknowledge frames with version number 0 or 1 Acknowledge frames with version number 0 or 1 or 2 Acknowledge frames independent of frame version number •...
Page 146 Table 9-77 MAX_BE Register Bits Register Bits Value Description MAX_BE3:0 This value is not valid for the maximum back-off exponent. This value is not valid for the maximum back-off exponent. Minimum, IEEE compliant value for the maximum back-off exponent. Maximum, IEEE compliant value for the maximum back-off exponent.
Page 147 ATmega256/128/64RFR2 • Bit 1 – MAF1EN - Multiple Address Filter 1 Enable This bit enables the Multiple Address Filter 1. If the bit is set and the corresponding Short Address and PAN ID Register is configured, an address match is indicated in the IRQ_STATUS1 register and an interrupt occurs if the interrupt enable flag is set in the IRQ_MASK register.
Page 148 subfield of the acknowledgment frame if the ACK is the answer to a data request MAC command frame. • Bit 4 – AACK_2_I_AM_COORD - Enable PAN Coordinator mode for address filter 2. This register bit has to be set if the node is a PAN coordinator for address filter 2. It is used for frame filtering in RX_AACK.
Page 149 ATmega256/128/64RFR2 9.12.57 MAFPA0L – Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte) NA ($110) MAFPA0L7:0 MAFPA0L Read/Write Initial Value This register contains the lower 8 bits of the MAC PAN ID for Frame Filter 0 address recognition.
Page 150 This register contains the upper 8 bits of the MAC PAN ID for Frame Filter 2 address recognition. • Bit 7:0 – MAFPA2H7:0 - MAC Personal Area Network ID high Byte for Frame Filter 2 These bits contain the bits [15:8] of the MAC PAN ID for Frame Filter 2. 9.12.61 MAFPA2L –...
Page 151 ATmega256/128/64RFR2 These bits contain the bits [7:0] of the MAC PAN ID for Frame Filter 3. 9.12.64 MAFSA0H – Transceiver MAC Short Address Register for Frame Filter 0 (High Byte) NA ($10F) MAFSA0H7:0 MAFSA0H Read/Write Initial Value This register contains the upper 8 bits of the MAC short address for Frame Filter 0 address recognition.
Page 152 This register contains the lower 8 bits of the MAC short address for Frame Filter 1 address recognition. • Bit 7:0 – MAFSA1L7:0 - MAC Short Address low Byte for Frame Filter 1 These bits contain the bits [7:0] of the MAC short address for Frame Filter 1. 9.12.68 MAFSA2H –...
Page 153 ATmega256/128/64RFR2 9.12.71 MAFSA3L – Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte) NA ($11A) MAFSA3L7:0 MAFSA3L Read/Write Initial Value This register contains the lower 8 bits of the MAC short address for Frame Filter 3 address recognition. •...
Page 154 • Bit 4 – TST_CTRL_DIG_4 - Switch Receiver Input Data This bit is reserved for internal use. It is used to switch the input source from the receiver. A value of 0 selects the default RX ADC path. A value of 1 selects the DIG1 pin as a receive data source.
Page 155 ATmega256/128/64RFR2 This bit is reserved for future use. The result of a read access is undefined. The register bit must always be written with the reset value. • Bit 5 – AGC_HOLD_SEL - Enable AGC Hold Function A value of 1 will disable the AGC hold function of the base-band processor. Normal operation of the AGC is achieved with a value of 0 (reset value) of this bit.
Page 156 • Bit 4 – TX_RX_SEL - Select Transmit/Receive Control Signal A value of 0 (reset value) selects the state-machine to control the sigma-delta modulator. A value of 1 selects this register as the control input. • Bit 3:0 – Resx3:0 - Reserved 9.12.76 TRXFBST –...
Page 157: Mac Symbol Counter
ATmega256/128/64RFR2 10 MAC Symbol Counter Figure 10-1. Symbol Counter Overview clock prescaler configuration 320µs register clock backoff slot select counter 32Bit Symbol Counter compare unit 1 interrupt generation Beacon compare timestamp timestamp unit 2 compare unit 3 10.1 Main Features The MAC symbol counter provides symbol timing information for IEEE 802.15.4 wireless networks.
Page 158: Bit Register Access (Atomic Read/Write)
clock source change is indicated in the bit SCCKSEL of Register "SCCR0 – Symbol Counter Control Register 0" on page 171 . The bit SCCKSEL can not be written if the radio transceiver is in SLEEP mode. After wake up, the counter switches back to the clock source which was selected before going to sleep mode.
Page 159: Symbol Counter Beacon Timestamp Register (32 Bit, Scbtsr)
ATmega256/128/64RFR2 length > 0) has been detected, but it is not checked if the received frame is valid (CRC check). Timestamping must be enabled in the control register (Bit SCTSE of Register SCCR0). A read access to SCTSRLL requires a maximum of three AVR clocks. Reading the upper three bytes of the timestamp requires two CPU clock cycles for each byte.
Page 160: Backoff Slot Counter
All Interrupts can be used to wakeup the controller from any sleep state. 10.9 Backoff Slot Counter The backoff slot counter can be used to provide accurate MAC protocol timing. The counter is sourced by the transceiver clock and works only if the transceiver clock is running.
Page 161: Register Description
ATmega256/128/64RFR2 The Symbol Counter together with the three compare units provide support for waking up the device at the right time to receive the beacon for superframe synchronization and at certain times within the superframe. A typical superframe timing scenario using the symbol counter relative compare mode is shown in Figure 10-3 below.
Page 162 The Register describes the source timestamp register used for the relative compare mode. The time stamp source can be selected separately for each compare unit. Possible sources for the relative compare are the Transmit Timestamp, the Receive Timestamp or the Beacon Timestamp (default). •...
Page 163 ATmega256/128/64RFR2 Register Bits Value Description Compare Unit 1 Relative Compare Source = Received Frame Timestamp Register 10.11.2 SCCNTHH – Symbol Counter Register HH-Byte NA ($E4) SCCNTHH7:0 SCCNTHH Read/Write Initial Value This register contains the most significant byte of the 32 bit Symbol Counter. •...
Page 164 10.11.6 SCTSRHH – Symbol Counter Frame Timestamp Register HH-Byte NA ($EC) SCTSRHH7:0 SCTSRHH Read/Write Initial Value This register contains the most significant byte of the 32 bit frame (SFD) timestamp register • Bit 7:0 – SCTSRHH7:0 - Symbol Counter Frame Timestamp Register HH-Byte 10.11.7 SCTSRHL –...
Page 165 ATmega256/128/64RFR2 10.11.10 SCTSTRHH – Symbol Counter Transmit Frame Timestamp Register HH-Byte NA ($FC) SCTSTRHH7:0 SCTSTRHH Read/Write Initial Value This register contains the most significant byte of the 32 bit Transmit Frame Timestamp Register. The Transmit Frame Timestamp Register is updated one symbol before the beginning of the frame transmission (preamble transmission).
Page 166 This register contains the least significant byte of the 32 bit Transmit Frame Timestamp Register. • Bit 7:0 – SCTSTRLL7:0 - Symbol Counter Transmit Frame Timestamp Register LL-Byte 10.11.14 SCRSTRHH – Symbol Counter Received Frame Timestamp Register HH-Byte NA ($DA) SCRSTRHH7:0 SCRSTRHH Read/Write...
Page 167 ATmega256/128/64RFR2 10.11.17 SCRSTRLL – Symbol Counter Received Frame Timestamp Register LL-Byte NA ($D7) SCRSTRLL7:0 SCRSTRLL Read/Write Initial Value This register contains the least significant byte of the 32 bit Received Frame Timestamp Register. • Bit 7:0 – SCRSTRLL7:0 - Symbol Counter Received Frame Timestamp Register LL-Byte 10.11.18 SCBTSRHH –...
Page 168 This register contains the second least significant byte of the 32 bit Beacon Timestamp Register. • Bit 7:0 – SCBTSRLH7:0 - Symbol Counter Beacon Timestamp Register LH- Byte 10.11.21 SCBTSRLL – Symbol Counter Beacon Timestamp Register LL-Byte NA ($E5) SCBTSRLL7:0 SCBTSRLL Read/Write Initial Value...
Page 169 ATmega256/128/64RFR2 This register contains the second least significant byte of the 32 bit compare value for the first compare unit • Bit 7:0 – SCOCR1LH7:0 - Symbol Counter Output Compare Register 1 LH-Byte 10.11.25 SCOCR1LL – Symbol Counter Output Compare Register 1 LL-Byte NA ($F5) SCOCR1LL7:0 SCOCR1LL...
Page 170 This register contains the second least significant byte of the 32 bit compare value for the second compare unit • Bit 7:0 – SCOCR2LH7:0 - Symbol Counter Output Compare Register 2 LH-Byte 10.11.29 SCOCR2LL – Symbol Counter Output Compare Register 2 LL-Byte NA ($F1) SCOCR2LL7:0 SCOCR2LL...
Page 171 ATmega256/128/64RFR2 This register contains the second least significant byte of the 32 bit compare value for the third compare unit • Bit 7:0 – SCOCR3LH7:0 - Symbol Counter Output Compare Register 3 LH-Byte 10.11.33 SCOCR3LL – Symbol Counter Output Compare Register 3 LL-Byte NA ($ED) SCOCR3LL7:0 SCOCR3LL...
Page 172 source, regardless of the selected clock. After wakeup, it switches back to the previosly selected clock source. • Bit 3 – SCTSE - Symbol Counter Automatic Timestamping enable This bit enables automatic SFD and Beacon Timestamping. If the bit is zero, no automatic timestamp capturing is possible.
Page 173 ATmega256/128/64RFR2 The 3 Bit value controls the symbol counter clock prescaler. The input clock to the prescaler is the 16MHz transceiver clock. The different prescaler values are defined in the table below. The default prescaler setting is 62.5kHz. If the transceiver clock is selected, the counter continues on the RTC time base during sleep mode, regardless of the SCCKDIV setting.
Page 174 The Interrupt Status Register indicates pending interrupt requests. If the corresponding interrupt mask bit is set, an interrupt service routine is called and the status bit is cleared automatically. It is also possible to clear the status bit by writing "1" to the selected bit.
Page 175 ATmega256/128/64RFR2 • Bit 0 – IRQMCP1 - Symbol Counter Compare Match 1 IRQ enable This bit enables the SCNT_CMP1 interrupt. 8393C-MCU Wireless-09/14...
Page 176: System Clock And Clock Options
11 System Clock and Clock Options This section describes the clock options for the AVR microcontroller. 11.1 Overview Figure 11-1 below presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in chapter "Power Management and Sleep Modes"...
Page 177: Clock Sources
ATmega256/128/64RFR2 11.2.2 I/O Clock – clk The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.
Page 178: Calibrated Internal Rc Oscillator
To ensure sufficient startup time, the device issues an internal reset with a time-out delay (t ) after the device reset is released by all other reset sources. Section TOUT "Power-on Reset" on page 210 describes the start conditions for the internal reset. The delay (t ) is timed from the Watchdog Oscillator and the number of cycles in the TOUT...
Page 179: 128 Khz Internal Oscillator
ATmega256/128/64RFR2 When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre- programmed calibration value, see the section "Calibration Byte" on page 507.
Page 180: Transceiver Crystal Oscillator
Figure 11-2. External Clock Drive Configuration external clock CLKI When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 11-8 below. Table 11-7. External Clock Frequency Nominal Frequency CKSEL3:0 0 – 16 MHz 0000 Table 11-8.
Page 181: Clock Output Buffer
ATmega256/128/64RFR2 Table 11-10. Start-up Times for the Transceiver Oscillator Clock Selection Power Conditions Start-up Time from Additional Delay CKSEL0 SUT1:0 Power-down and from Reset Power-save fast rising power 258 CK 14CK + 4.1 ms slowly rising power 258 CK 14CK + 65 ms BOD enabled 1K CK 14CK + 0 ms...
Page 182: Register Description
The prescaler is implemented as a ripple counter running at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable. The exact time it takes to switch from one clock division to another cannot be exactly predicted.
Page 183 ATmega256/128/64RFR2 Register Bits Value Description 0x7f End value of low frequency range calibration 0x80 Start value of high frequency range calibration 0xff Calibration value for highest oscillator frequency 11.11.2 CLKPR – Clock Prescale Register NA ($61) CLKPCE Res2 Res1 Res0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR Read/Write...
Page 184 Register Bits Value Description Division factor 256 / RC-Oscillator 512 Reserved Reserved Reserved Reserved Reserved Reserved Division factor 1 only permitted for RC- Oscillator. Flash and EEPROM programming is not allowed. ATmega256/128/64RFR2 8393C-MCU Wireless-09/14...
Page 185: Power Management And Sleep Modes
ATmega256/128/64RFR2 12 Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR microcontroller and the RF transceiver provide various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
Page 186: Avr Microcontroller Sleep Modes
C Code Example #include <avr/sleep.h> int main(void) … TRXPR = 1 << SLPTR; // sent transceiver to sleep set_sleep_mode(SLEEP_MODE_PWR_DOWN); // select power down mode sleep_enable(); sleep_cpu(); // go to deep sleep sleep_disable(); // executed after wake-up … Notes: 1. See also section "About Code Examples"...
Page 187 ATmega256/128/64RFR2 To enter any of the sleep modes, the SE bit in in the SMCR register (see "SMCR – Sleep Mode Control Register" on page 196) must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode will be activated by the SLEEP instruction.
Page 188: Extended Standby Mode
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to section "External Interrupts" on page 250 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective.
Page 189: Minimizing Power Consumption
ATmega256/128/64RFR2 transceiver. The SRAM is shut down by a DRT switch and the radio transceiver is in reset state if its respective power reduction bit is set. Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption.
Page 190 12.4.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk ) and the ADC clock (clk ) are stopped, the input buffers of the device will be disabled.
Page 191: Supply Voltage And Leakage Control
ATmega256/128/64RFR2 12.5 Supply Voltage and Leakage Control For battery applications using DEEP_SLEEP periods, the leakage current defines the system life time. Due to the typical strong temperature dependency of the leakage current, major contributors to the leakage budget are turned off: •...
Page 192 Figure 12-2 shows the chained startup procedure after power up. The Figure 12-3 shows the startup from DEEP_SLEEP. A module is only switched on if it is not deselected by power reduction register (PRR1 or PRR2). This is possible for SRAM blocks and radio transceiver power switch.
Page 193 ATmega256/128/64RFR2 AVR State Radio Transceiver State Powerchain (2,3) off (SLEEP or power reduction) DEEP SLEEP Notes: 1. Idle 2. Power Down 3. Power Save 4. ADC Noise Reduction Mode 5. Standby 6. Extended Standby 7. If the OCDEN fuse is programmed, the Power-chain is always on 12.5.2 SRAM with Data Retention It is necessary to prevent any data loss of the SRAM when setting the CPU in one of the DEEP_SLEEP modes.
Page 194 • Configurable to use an external voltage regulator; internal voltage regulators supply stabilized voltage ATmega256/128/64RFR2. The AVREG provides the regulated 1.8V supply voltage for the analog section and the DVREG supplies the 1.8V supply voltage for the digital section. The DVREG is enabled during startup and is switched off if the power-chain is disabled.
Page 195 ATmega256/128/64RFR2 Because the calibration setting is fixed, temperature and load current variations during the following DEEP_SLEEP period are not regulated out. Thus the output voltage may drift away from the target value. However the design guarantees that for allowed operating conditions the output voltage will stay within valid limits. After every wake-up a new calibration cycle is initiated.
Page 196: Register Description
After the completion of the power-up process the calibration will start automatically if bit LLENCAL in the control register LLCR is 1 (default). The completion of a calibration cycle is indicated by the bit LLDONE in that same register. After the first cycle the calibration will continue to run until either the device goes into a sleep mode (“power down”...
Page 197 ATmega256/128/64RFR2 Table 12-104 SM Register Bits Register Bits Value Description SM2:0 0x00 Idle 0x01 ADC Noise Reduction (If Available) 0x02 Power Down 0x03 Power Save 0x04 Reserved 0x05 Reserved 0x06 Standby 0x07 Extended Standby • Bit 0 – SE - Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.
Page 198 Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation. • Bit 1 – PRUSART0 - Power Reduction USART Writing a logic one to this bit shuts down the USART0 by stopping the clock to the module.
Page 199 ATmega256/128/64RFR2 12.6.4 PRR2 – Power Reduction Register 2 NA ($63) Res3 Res2 Res1 Res0 PRRAM3 PRRAM2 PRRAM1 PRRAM0 PRR2 Read/Write Initial Value The Power Reduction Register PRR2 allows to individually disable all four SRAM blocks. Setting any PRRAM3:0 bit to one will completely switch off (disconnect from the power supply) the corresponding SRAM block.
Page 200 • Bit 1 – SLPTR - Multi-purpose Transceiver Control Bit The bit SLPTR is a multi-functional bit to control transceiver state transitions. Dependent on the radio transceiver state, a rising edge of bit SLPTR causes the following state transitions: TRX_OFF => SLEEP (level sensitive), PLL_ON => BUSY_TX.
Page 201 ATmega256/128/64RFR2 Table 12-105 DRTMP Register Bits Register Bits Value Description DRTMP1:0 500 mV 425 mV 360 mV < 5 mV • Bit 1:0 – DRTMN1:0 - Negative Data Retention Voltage Setting The bits DRTMN1:0 define the reduction of the negative supply voltage during data retention (DRT) mode.
Page 202 power supply) and all its data are lost. The typical voltage reduction levels are shown in the following table. Table 12-107 DRTMP Register Bits Register Bits Value Description DRTMP1:0 500 mV 425 mV 360 mV < 5 mV • Bit 1:0 – DRTMN1:0 - Negative Data Retention Voltage Setting The bits DRTMN1:0 define the reduction of the negative supply voltage during data retention (DRT) mode.
Page 203 ATmega256/128/64RFR2 • Bit 4 – ENDRT - Enable SRAM Data Retention During "Deep-Sleep" each SRAM block will either be switched off or provides data retention of its memory content. This bit must set to one if data retention mode should be used.
Page 204 This bit indicates the status of the SRAM power-switch. A logical one indicates that the SRAM supply voltage is fully available and the memory may be accessed normally. • Bit 4 – ENDRT - Enable SRAM Data Retention During "Deep-Sleep" each SRAM block will either be switched off or provides data retention of its memory content.
Page 205 ATmega256/128/64RFR2 • Bit 7:6 – Res1:0 - Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. • Bit 5 – LLDONE - Calibration Done This bit indicates the last state of the calibration algorithm. The data register contents is updated with new calibration data after the bit changed to 1.
Page 206 • Bit 4:0 – LLDRH4:0 - High-Byte Data Register Bits Value of the high-byte calibration result Table 12-113 LLDRH Register Bits Register Bits Value Description LLDRH4:0 0x00 Calibration limit for fast process corner/high output voltage 0x10 Calibration limit for slow process corner/low output voltage 12.6.12 LLDRL –...
Page 207 ATmega256/128/64RFR2 Table 12-115 PFDRV Register Bits Register Bits Value Description PFDRV1:0 2 mA 4 mA 6 mA 8 mA • Bit 5:4 – PEDRV1:0 - Driver Strength Port E Table 12-116 PEDRV Register Bits Register Bits Value Description PEDRV1:0 2 mA 4 mA 6 mA 8 mA...
Page 208 Table 12-119 PGDRV Register Bits Register Bits Value Description PGDRV1:0 2 mA 4 mA 6 mA 8 mA ATmega256/128/64RFR2 8393C-MCU Wireless-09/14...
Page 209: System Control And Reset
ATmega256/128/64RFR2 13 System Control and Reset 13.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP –...
Page 210 Figure 13-1. Reset Logic DATA BUS MCU Status Register (MCUSR) EVDD Brown-out Reset Circuit BODLEVEL [2..0] DEVDD Power-on Reset Circuit Pull-up Resistor SPIKE RSTN Reset Circuit FILTER JTAG Reset Watchdog Register Timer Watchdog Oscillator Delay Counters Clock Generator TIMEOUT CKSEL[3:0] SUT[1:0] 13.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by a dynamic, on-chip detection circuit.
Page 211 ATmega256/128/64RFR2 Figure 13-3. MCU Start-up, RSTN Extended Externally RSTN TOUT TIME-OUT INTERNAL RESET 13.2.2 External Reset An External Reset is generated by a low level on the RSTN pin. Reset pulses longer than the minimum pulse width (see "System and Reset Characteristics" on page 556) will generate a reset, even if the clock is not running.
Page 212: Internal Voltage Reference
Figure 13-5. Brown-out Reset During Operation EVDD BOT+ BOT- RSTN TOUT TIME-OUT INTERNAL RESET 13.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t .
Page 213: Watchdog Timer
ATmega256/128/64RFR2 13.4 Watchdog Timer 13.4.1 Features • Clocked from separate On-chip Oscillator • 3 Operating modes - Interrupt - System Reset - Interrupt and System Reset • Selectable Time-out period from 16ms to 8s • Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode Figure 13-7.
Page 214 program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows: 1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.
Page 215 ATmega256/128/64RFR2 Note: 1. The example code assumes that the part specific header file is included. If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets.
Page 216: Register Description
(1,2) Assembly Code Example, Interrupt Mode WDT_Interrupt_Mode: ; Turn off global interrupt ; Reset Watchdog Timer ; Start timed sequence, use WDCE and WDE bits r16, (1<<WDCE) | (1<<WDE) WDTCSR, r16 ; --Got four cycles to set the new values from here – ;...
Page 217 ATmega256/128/64RFR2 cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. Note, after power on the bit EXTRF has to be ignored. • Bit 7:5 – Res2:0 - Reserved • Bit 4 – JTRF - JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
Page 218 Table 13-1. Watchdog Timer Configuration WDTON WDIE Mode Action on Time-out Stopped None Interrupt Mode Interrupt System Reset Mode Reset Interrupt and System Interrupt, then go to Reset Mode System Reset Mode System Reset Mode Reset Note: 1. WDTON Fuse set to “0“ means programmed and “1” means un-programmed. •...
Page 219: O-Ports
ATmega256/128/64RFR2 14 I/O-Ports 14.1 Introduction All ATmega256/128/64RFR2 ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions.
Page 220: Ports As General Digital I/O
14.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 14-2 below shows a functional description of one I/O-port pin, here generically called Pxn. Figure 14-2. General Digital I/O DPDS0/DPDS1 DPDS0/DPDS1: drive strength register Note: 1.
Page 221: Pin Configurations
ATmega256/128/64RFR2 14.2.3 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 14.2.4 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur.
Page 222: Atmega256/128/64Rfr2
Figure 14-3. Synchronization when reading an external applied pin value Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH”...
Page 223: Atmega256/128/64Rfr2
ATmega256/128/64RFR2 Assembly Code Example … ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16 out DDRB,r17 ; Insert nop for synchronization ; Read port pins in r16,PINB … C Code Example unsigned char i;...
Page 224: Alternate Port Functions
described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset-, Active- and Idle-mode). The simplest method to ensure a defined level of an unused pin is to enable the internal pull-up.
Page 225 ATmega256/128/64RFR2 Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. , SLEEP, and PUD are common to all ports. All other signals are unique for each pin. The following table summarizes the function of the overriding signals. The pin and port indexes from Figure 14-5 on page 224 are not shown in the succeeding tables.
Page 226 Table 14-3. Port B Pins Alternate Functions Port Pin Alternate Functions OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/Counter0, Output Compare and PWM Output C for Timer/Counter1 or Pin Change Interrupt 7) OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change Interrupt 6) OC1A/PCINT5 (Output Compare and PWM Output A for Timer/Counter1 or Pin Change Interrupt 5)
Page 227 ATmega256/128/64RFR2 PCINT4, Pin Change Interrupt source 4: The PB4 pin can serve as an external interrupt source. • MISO/PDO/PCINT3 – Port B, Bit 3 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3.
Page 228 Signal PB7/OC0A/OC1C PB6/OC1B PB5/OC1A PB4/OC2A Name PUOV DDOE DDOV PVOE OC0/OC1C OC1B ENABLE OC1A ENABLE OC2A ENABLE ENABLE PVOV OC0/OC1C OC1B OC1A OC2A DIEOE PCINT7•PCIE0 PCINT6•PCIE0 PCINT5•PCIE0 PCINT4•PCIE0 DIEOV PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT PCINT4 INPUT – – – –...
Page 229 ATmega256/128/64RFR2 • T1 – Port D, Bit 6 T1, this is Timer/Counter1 counter source. • XCK1 – Port D, Bit 5 XCK1, USART1 External clock: The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1 operates in Synchronous mode.
Page 230: Pe1:Txd0
Signal PD7/T0 PD6/T1 PD5/XCK1 PD4/ICP1 Name DDOV PVOE XCK1 OUTPUT ENABLE PVOV XCK1 OUTPUT DIEOE DIEOV T0 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT – – – – Table 14-8. Overriding Signals for Alternate Functions PD3:PD0 Signal PD3/INT3/TXD1 PD2/INT2/RXD1 PD1/INT1/SDA PD0/INT0/SCL Name PUOE...
Page 231: Pe0:Rxd0:Pcint8
ATmega256/128/64RFR2 Port Alternate Function RXD0/PCINT8 (USART0 Receive Pin or Pin Change Interrupt8) • INT7/ICP3/CLKO – Port E, Bit 7 INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. ICP3, Input Capture Pin 3: The PE7 pin can act as an input capture pin for Timer/Counter3.
Page 232 RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.
Page 233 ATmega256/128/64RFR2 Table 14-12. Port F Pins Alternate Functions Port Pin Alternate Function ADC7/TDI (ADC input channel 7 or JTAG Test Data Input) ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select) ADC4/TCK (ADC input channel 4 or JTAG Test Clock) ADC3/DIG4 (ADC input channel 3 or Radio Transceiver RX/TX Indicator Output)
Page 234 Table 14-13. Overriding Signals for Alternate Functions PF7:PF4 Signal PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK Name PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV DDOE JTAGEN JTAGEN JTAGEN JTAGEN DDOV SHIFT_IR+SHIFT_DR PVOE JTAGEN PVOV DIEOE JTAGEN JTAGEN JTAGEN JTAGEN DIEOV – – – – TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5...
Page 235 ATmega256/128/64RFR2 TOSC2, Timer Oscillator pin 1: Setting the AS2 bit to one and the EXCLKAMR bit to zero in ASSR, enables asynchronous clocking of Timer/Counter2 by a Crystal Oscillator. The pin PG4 is disconnected from the port, and becomes the input of the inverting Oscillator amplifier.
Page 236: Register Description
Table 14-17. Overriding Signals for Alternate Functions PG1:PG0 Signal PG1/DIG1 PG0/DIG3 Name PUOE PUOV DDOE ANT_EXT_SW_EN PA_EXT_EN DDOV ANT_EXT_SW_EN PA_EXT_EN PVOE ANT_EXT_SW_EN PA_EXT_EN PVOV DIG1 DIG3 DIEOE DIEOV – – – – 14.4 Register Description For a detailed description of register MCUCR see chapter "MCUCR –...
Page 237 ATmega256/128/64RFR2 Table 14-18 PFDRV Register Bits Register Bits Value Description PFDRV1:0 2 mA 4 mA 6 mA 8 mA • Bit 5:4 – PEDRV1:0 - Driver Strength Port E Table 14-19 PEDRV Register Bits Register Bits Value Description PEDRV1:0 2 mA 4 mA 6 mA 8 mA...
Page 238 Table 14-22 PGDRV Register Bits Register Bits Value Description PGDRV1:0 2 mA 4 mA 6 mA 8 mA 14.4.4 PORTB – Port B Data Register $05 ($25) PORTB7:0 PORTB Read/Write Initial Value If PORTBn is written logic one when the PORTB pin n is configured as an input pin, the pull-up resistor is activated.
Page 239 ATmega256/128/64RFR2 14.4.7 PORTD – Port D Data Register $0B ($2B) PORTD7:0 PORTD Read/Write Initial Value If PORTDn is written logic one when the PORTD pin n is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTDn has to be written logic zero or the pin has to be configured as an output pin.
Page 240 If PORTEn is written logic one when the PORTE pin n is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTEn has to be written logic zero or the pin has to be configured as an output pin. If PORTEn is written logic one when the pin is configured as an output pin, the port pin is driven high (one).
Page 241 ATmega256/128/64RFR2 14.4.14 DDRF – Port F Data Direction Register $10 ($30) DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF Read/Write Initial Value The DDFn bit in the DDRF Register selects the direction of the PORTF pin n. If DDFn is written logic one, PFn is configured as an output pin.
Page 242 14.4.17 DDRG – Port G Data Direction Register $13 ($33) Res1 Res0 DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 DDRG Read/Write Initial Value The DDGn bit in the DDRG Register selects the direction of the PORTG pin n. If DDGn is written logic one, PGn is configured as an output pin. If DDGn is written logic zero, PGn is configured as an input pin.
Page 243: Interrupts
ATmega256/128/64RFR2 15 Interrupts This section describes the specifics of the interrupt handling as performed in ATmega256/128/64RFR2. For a general explanation of the AVR interrupt handling, refer to "Reset and Interrupt Handling" on page 15.1 Interrupt Vectors in ATmega256/128/64RFR2 Table 15-1. Reset and Interrupt Vectors Vector Program Address...
Page 244 Vector Program Address Source Interrupt Definition $003A ADC Conversion Complete $003C EE_READY EEPROM Ready $003E TIMER3_CAPT Timer/Counter3 Capture Event $0040 TIMER3_COMPA Timer/Counter3 Compare Match A $0042 TIMER3_COMPB Timer/Counter3 Compare Match B $0044 TIMER3_COMPC Timer/Counter3 Compare Match C $0046 TIMER3_OVF Timer/Counter3 Overflow $0048 USART1_RX USART1 Rx Complete...
Page 245: Reset And Interrupt Vector Placement
ATmega256/128/64RFR2 Vector Program Address Source Interrupt Definition $0082 SCNT_CMP1 Symbol Counter Compare Match 1 $0084 SCNT_CMP 2 Symbol Counter Compare Match 2 $0086 SCNT_CMP 3 Symbol Counter Compare Match 3 $0088 SCNT_OVFL Symbol Counter Overflow $008A SCNT_BACKOFF Symbol Counter Backoff Slot Counter $008C AES_READY AES Encryption Ready...
Page 246 0x0008 INT3 ;IRQ3 Handler 0x000A INT4 ;IRQ4 Handler 0x000C INT5 ;IRQ5 Handler 0x000E INT6 ;IRQ6 Handler 0x0010 INT7 ;IRQ7 Handler 0x0012 PCINT0 ;PCINT0 Handler 0x0014 PCINT1 ;PCINT1 Handler 0x0016 PCINT2 ;PCINT2 Handler 0X0018 ;Watchdog Timeout Handler 0x001A TIM2_COMPA ;Timer2 CompareA Handler 0x001C TIM2_COMPB ;Timer2 CompareB Handler...
Page 247 ATmega256/128/64RFR2 0x007C TRX24_XAH_AMI ;Transceiver Addr. Match Handler 0x007E TRX24_TX_END ;Transceiver Transmit End Handler 0x0080 TRX24_AWAKE ;Transceiver Wake Up Handler 0x0082 SCNT_CMP1 ;Symbol Counter Compare Match 1 0x0084 SCNT_CMP2 ;Symbol Counter Compare Match 2 0x0086 SCNT_CMP3 ;Symbol Counter Compare Match 3 0x0088 SCNT_OVFL ;Symbol Counter Overflow Handler...
Page 248: Moving Interrupts Between Application And Boot Section
When the BOOTRST Fuse is programmed, the Boot section size set to 8KBytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code Comments________________________...
Page 249: Register Description
ATmega256/128/64RFR2 15.4 Register Description 15.4.1 MCUCR – MCU Control Register $35 ($55) Res1 Res0 Res1 Res0 IVSEL IVCE MCUCR Read/Write Initial Value The MCU Control Register contains control bits for general Microcontroller Unit functions. • Bit 7 – JTD - JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed.
Page 250: External Interrupts
16 External Interrupts The External Interrupts are triggered by the INT7:0 pin or any of the PCINT8:0 pins. Observe that if enabled, the interrupts will trigger even if the INT7:0 or PCINT8:0 pins are configured as outputs. This feature provides a way of generating a software interrupt.
Page 251: Register Description
ATmega256/128/64RFR2 16.2 Register Description 16.2.1 EICRA – External Interrupt Control Register A NA ($69) ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA Read/Write Initial Value The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set.
Page 252 Table 16-148 ISC1 Register Bits Register Bits Value Description ISC11:10 0x00 The low level of INTn generates an interrupt request. 0x01 Any edge of INTn generates asynchronously an interrupt request. 0x02 The falling edge of INTn generates asynchronously an interrupt request. 0x03 The rising edge of INTn generates asynchronously an interrupt request.
Page 253 ATmega256/128/64RFR2 Register Bits Value Description request. 0x01 Any edge of INTn generates asynchronously an interrupt request. 0x02 The falling edge of INTn generates asynchronously an interrupt request. 0x03 The rising edge of INTn generates asynchronously an interrupt request. • Bit 5:4 – ISC61:60 - External Interrupt 6 Sense Control Bit Table 16-151 ISC6 Register Bits Register Bits Value...
Page 254 16.2.3 EIMSK – External Interrupt Mask Register $1D ($3D) INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 EIMSK Read/Write Initial Value When an INT7:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers EICRA and EICRB define whether the External Interrupt is activated on rising or falling edge or level sensed.
Page 255 ATmega256/128/64RFR2 16.2.5 PCICR – Pin Change Interrupt Control Register NA ($68) Res4 Res3 Res2 Res1 Res0 PCIE2 PCIE1 PCIE0 PCICR Read/Write Initial Value • Bit 7:3 – Res4:0 - Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content.
Page 256 • Bit 1 – PCIF1 - Pin Change Interrupt Flag 1 When a logic change on any PCINT15:8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
Page 257 ATmega256/128/64RFR2 • Bit 7:1 – PCINT15:9 - Pin Change Enable Mask Bits 15:9 of the PCMSK1 register have no function in this device. The I/O ports associated to PCINT15:9 are not implemented. • Bit 0 – PCINT8 - Pin Change Enable Mask 8 If this bit is set to one the pin change interrupt on the corresponding I/O pin is enabled.
Page 258: 17 8-Bit Timer/Counter0 With Pwm
17 8-bit Timer/Counter0 with PWM 17.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period •...
Page 259: Timer/Counter Clock Sources
ATmega256/128/64RFR2 17.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit registers. Interrupt request signals (abbreviated to Int.Req. in the figure) are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
Page 260: Output Compare Unit
Figure 17-2. Counter Unit Block Diagram TOVn (Int.Req.) DATA BUS Clock Select count Edge Detector clear TCNTn Control Logic direction ( From Prescaler ) bottom Signal description (internal signals): count Increment or decrement TCNT0 by 1; direction Select between increment and decrement; clear Clear TCNT0 (set all bits to zero);...
Page 261 ATmega256/128/64RFR2 Figure 17-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn (8-bit Comparator ) OCFnx (Int.Req.) bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled.
Page 262: Compare Match Output Unit
Be aware that the COM0x1:0 bits are not double buffered together with the compare value. A Change of the COM0x1:0 bits will take effect immediately. 17.6 Compare Match Output Unit The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match.
Page 263 ATmega256/128/64RFR2 A state change of the COM0x1:0 bits will have effect at the first Compare Match after the bits are written. For non-PWM modes the action can be forced to have immediate effect by using the FOC0x strobe bits. The following table shows the COM0x1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-PWM).
Page 264: Modes Of Operation
17.7 Modes of Operation The mode of operation i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence while the Waveform Generation mode bits do.
Page 265 ATmega256/128/64RFR2 for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 17-5. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A.
Page 266 PWM mode well suited for power regulation, rectification and DAC applications. The high frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value.
Page 267 ATmega256/128/64RFR2 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency with 50% duty cycle waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1).
Page 268: Timer/Counter Timing Diagrams
In phase correct PWM mode, the compare unit allows generating PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to 3. Setting the COM0A0 bits to 1 allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set.
Page 269 ATmega256/128/64RFR2 Figure 17-9 shows the same timing data, but with the prescaler enabled. Figure 17-9. Timer/Counter Timing Diagram with Prescaler (f clkI/O (clk TCNTn MAX - 1 BOTTOM BOTTOM + 1 TOVn Figure 17-10 shows the setting of OCF0B and OCF0A in all modes except CTC and PWM mode, where OCR0A is TOP.
Page 270: Register Description
17.9 Register Description 17.9.1 GTCCR – General Timer/Counter Control Register $23 ($43) Res4 Res3 Res2 Res1 Res0 PSRASY PSRSYNC GTCCR Read/Write Initial Value • Bit 7 – TSM - Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted.
Page 271 ATmega256/128/64RFR2 Table 17-6 COM0A Register Bits Register Bits Value Description COM0A1:0 Normal port operation, OC0A disconnected Toggle OC0A on Compare Match Clear OC0A on Compare Match Set OC0A on Compare Match • Bit 5:4 – COM0B1:0 - Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior.
Page 272 17.9.3 TCCR0B – Timer/Counter0 Control Register B $25 ($45) FOC0A FOC0B Res1 Res0 WGM02 CS02 CS01 CS00 TCCR0B Read/Write Initial Value • Bit 7 – FOC0A - Force Output Compare A The FOC0A bit is only active when the WGM02:0 bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0B is written in a PWM operation mode.
Page 273 ATmega256/128/64RFR2 Register Bits Value Description 0x04 clkIO/256 (from prescaler) 0x05 clkIO/1024 (from prescaler) 0x06 External clock source on T0 pin, clock on falling edge 0x07 External clock source on T0 pin, clock on rising edge 17.9.4 TCNT0 – Timer/Counter0 Register $26 ($46) TCNT0_7 TCNT0_6...
Page 274 17.9.6 OCR0B – Timer/Counter0 Output Compare Register B $28 ($48) OCR0B_7 OCR0B_6 OCR0B_5 OCR0B_4 OCR0B Read/Write Initial Value $28 ($48) OCR0B_3 OCR0B_2 OCR0B_1 OCR0B_0 OCR0B Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0).
Page 275 ATmega256/128/64RFR2 17.9.8 TIFR0 – Timer/Counter0 Interrupt Flag Register $15 ($35) Res4 Res3 Res2 Res1 Res0 OCF0B OCF0A TOV0 TIFR0 Read/Write Initial Value • Bit 7:3 – Res4:0 - Reserved This bit is reserved for future use. A read access always will return zero. A write access does not modify the content.
Page 276: 16-Bit Timer/Counter (Timer/Counter 1, 3, 4, And 5)
18 16-bit Timer/Counter (Timer/Counter 1, 3, 4, and 5) 18.1 Features • True 16-bit Design (i.e., allows 16-bit PWM) • Three independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceller •...
Page 277 ATmega256/128/64RFR2 Figure 18-1. 16-bit Timer/Counter Block Diagram Count TOVn (Int.Req.) Clear Control Logic Clock Select Direction Edge Detector BOTTOM ( From Prescaler ) Timer/Counter TCNTn OCnA (Int.Req.) Waveform OCnA Generation OCRnA OCnB Fixed (Int.Req.) Values Waveform OCnB Generation OCRnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge...
Page 278 Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C). See section "Output Compare Units" on page 284 for details. The compare match event will also set the Compare Match Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request.
Page 279 ATmega256/128/64RFR2 Assembly Code Examples ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNTnH,r17 out TCNTnL,r16 ; Read TCNTn into r17:r16 in r16,TCNTnL in r17,TCNTnH C Code Examples unsigned int i; /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn;...
Page 280 C Code Examples unsigned int TIM16_ReadTCNTn( void ) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg;...
Page 281 ATmega256/128/64RFR2 C Code Examples void TIM16_WriteTCNTn( unsigned int i ) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Set TCNTn to i */ TCNTn = i; /* Restore global interrupt flag */ SREG = sreg;...
Page 282 Clear Clear TCNTn (set all bits to zero); Timer/Counter clock; Signalize that TCNTn has reached maximum value; BOTTOM Signalize that TCNTn has reached minimum value (zero); The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) contains the upper eight bits of the counter and Counter Low (TCNTnL) contains the lower eight bits.
Page 283 ATmega256/128/64RFR2 Figure 18-3. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) ICRn (16-bit Register) TCNTn (16-bit Counter) WRITE ACO* ACIC* ICNC ICES Analog Comparator Noise Edge ICFn (Int.Req.) Canceler Detector ICPn Note: 1.
Page 284 clock cycles. Note that the input of the noise canceller and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICRn to define TOP. An input capture can be software-triggered by controlling the port of the ICPn pin. 18.6.2 Noise Canceller The noise canceller improves noise immunity by using a simple digital filtering scheme.
Page 285 ATmega256/128/64RFR2 Figure 18-4 shows a block diagram of the Output Compare unit. The small “n” in the register and bit names indicates the device number (n = Timer/Counter n), and the “x” indicates Output Compare unit A, B or C. The elements of the block diagram not direct parts of the Output Compare unit are gray shaded.
Page 286 18.7.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare match had occurred (the COMn1:0 bits settings define whether the OCnx pin is set, cleared or toggled).
Page 287 ATmega256/128/64RFR2 Figure 18-5. Compare Match Output Unit, Schematic COMnx1 Waveform COMnx0 Generator FOCnx OCnx OCnx PORT 18.8.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC and PWM modes. A setting of COMnx1:0 = 0 tells the Waveform Generator in all modes that no action on the OCnx Register is to be performed on the next compare match.
Page 288 Table 18-3. Compare Output Mode, Fast PWM COMnA1 COMnA0 COMnB1 COMnB0 COMnC1 COMnC0 Description Normal port operation, OCnA/OCnB/OCnC disconnected. WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C disconnected.
Page 289 ATmega256/128/64RFR2 Table 18-5. Waveform Generation Mode Bit Description Timer/Counter WGMn2 WGMn1 WGMn0) Update of TOVn Flag Mode WGMn3 (CTCn) (PWMn1) (PWMn0) Mode of Operation OCRnx at Set on Normal 0xFFFF Immediate PWM, Phase Correct, 8-bit 0x00FF BOTTOM PWM, Phase Correct, 9-bit 0x01FF BOTTOM PWM, Phase Correct, 10-bit...
Page 290 cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency.
Page 291 ATmega256/128/64RFR2 OCnx is set at BOTTOM. In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase-correct and phase and frequency correct PWM modes that use dual-slope operation.
Page 292 The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low value while the counter is running with no or a low prescaler value, there is a risk that the newly written ICRn value is lower than the current value of TCNTn.
Page 293 ATmega256/128/64RFR2 up-counting, and set on the compare match while down-counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has a lower maximum operation frequency than single slope operation. However these modes are preferred for motor control applications due to the symmetric feature of the dual-slope PWM modes.
Page 294 TCNTn and the OCRnx. Note that when working with fixed TOP values, the unused bits are masked to zero when any of the OCRnx Registers are written. As the third period shown in Figure 18-8 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an asymmetrical output.
Page 295 ATmega256/128/64RFR2 The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2 bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16 bit (ICRn or OCRnA set to MAX). The PWM resolution R in bits can be calculated with the following equation: PFCPWM...
Page 296 The definition of TOP with the ICRn Register works well when using fixed TOP values. Combined with ICRn the OCRnA Register is available for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by modifying the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature.
Page 297 ATmega256/128/64RFR2 Figure 18-11 shows the same timing data, but with the prescaler enabled. Figure 18-11. Timer/Counter Timing Diagram, Setting of OCFnx with Prescaler (f clkI/O (clk TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 18-12 shows the count sequence close to TOP in various modes.
Page 298 Figure 18-13 shows the same timing data, but with the prescaler enabled. Figure 18-13. Timer/Counter Timing Diagram with Prescaler (f clkI/O (clk TCNTn TOP - 1 BOTTOM BOTTOM + 1 (CTC and FPWM) TCNTn TOP - 1 TOP - 1 TOP - 2 (PC and PFC PWM) TOVn...
Page 299 ATmega256/128/64RFR2 The COM1B1:0 bits control the output compare behavior of pin OC1B. If one or both of the COM1B1:0 bits are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However note that the Data Direction Register (DDR) bit corresponding to the OC1B pin must be set in order to enable the output driver.
Page 300 Register Bits Value Description PWM, phase correct, 9-bit PWM, phase correct, 10-bit CTC, TOP = OCRnA Fast PWM, 8-bit Fast PWM, 9-bit Fast PWM, 10-bit PWM, Phase and frequency correct, TOP = ICRn PWM, Phase and frequency correct, TOP = OCRnA PWM, Phase correct, TOP = ICRn PWM, Phase correct, TOP = OCRnA...
Page 301 ATmega256/128/64RFR2 Combined with the WGM11:10 bits, found in the TCCR1A Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes.
Page 302 18.11.3 TCCR1C – Timer/Counter1 Control Register C NA ($82) FOC1A FOC1B FOC1C Res4 Res3 Res2 Res1 Res0 TCCR1C Read/Write Initial Value • Bit 7 – FOC1A - Force Output Compare for Channel A The FOC1A bit is only active when the WGM13:0 bits specify a non-PWM mode. When writing a logical one to the FOC1A bit, an immediate compare match is forced on the waveform generation unit.
Page 303 ATmega256/128/64RFR2 16-bit registers. See section "Accessing 16-bit Registers" for details. Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers. Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units.
Page 304 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1A pin. The Output Compare Registers are 16-bit in size.
Page 305 ATmega256/128/64RFR2 18.11.10 OCR1CH – Timer/Counter1 Output Compare Register C High Byte NA ($8D) OCR1CH7:0 OCR1CH Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC1C pin.
Page 306 18.11.13 ICR1L – Timer/Counter1 Input Capture Register Low Byte NA ($86) ICR1L7:0 ICR1L Read/Write Initial Value The Input Capture Register is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin or on the Analog Comparator output. The Input Capture Register can be used for defining the counter TOP value.
Page 307 ATmega256/128/64RFR2 The corresponding Interrupt Vector is executed when the OCF1A Flag, located in TIFR1, is set. • Bit 0 – TOIE1 - Timer/Counter1 Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow interrupt is enabled.
Page 308 overflows. TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed. Alternatively, TOV1 can be cleared by writing a logic one to its bit location. 18.11.16 TCCR3A – Timer/Counter3 Control Register A NA ($90) COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 TCCR3A Read/Write Initial Value...
Page 309 ATmega256/128/64RFR2 Register Bits Value Description (set output to high level). • Bit 3:2 – COM3C1:0 - Compare Output Mode for Channel C The COM3C1:0 bits control the output compare behavior of pin OC3C. If one or both of the COM3C1:0 bits are written to one, the OC3C output overrides the normal port functionality of the I/O pin it is connected to.
Page 310 Register Bits Value Description Fast PWM, TOP = ICRn Fast PWM, TOP = OCRnA 18.11.17 TCCR3B – Timer/Counter3 Control Register B NA ($91) ICNC3 ICES3 WGM33 WGM32 CS32 CS31 CS30 TCCR3B Read/Write Initial Value • Bit 7 – ICNC3 - Input Capture 3 Noise Canceller Setting this bit (to one) activates the Input Capture Noise Canceler.
Page 311 ATmega256/128/64RFR2 Register Bits Value Description Fast PWM, 10-bit PWM, Phase and frequency correct, TOP = ICRn PWM, Phase and frequency correct, TOP = OCRnA PWM, Phase correct, TOP = ICRn PWM, Phase correct, TOP = OCRnA CTC, TOP = OCRnA Reserved Fast PWM, TOP = ICRn Fast PWM, TOP = OCRnA...
Page 312 • Bit 6 – FOC3B - Force Output Compare for Channel B The FOC3B bit is only active when the WGM33:0 bits specify a non-PWM mode. When writing a logical one to the FOC3B bit, an immediate compare match is forced on the waveform generation unit.
Page 313 ATmega256/128/64RFR2 The two Timer/Counter I/O locations (TCNT3H and TCNT3L, combined TCNT3) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP).
Page 314 18.11.23 OCR3BH – Timer/Counter3 Output Compare Register B High Byte NA ($9B) OCR3BH7:0 OCR3BH Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC3B pin.
Page 315 ATmega256/128/64RFR2 18.11.26 OCR3CL – Timer/Counter3 Output Compare Register C Low Byte NA ($9C) OCR3CL7:0 OCR3CL Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC3C pin.
Page 316 18.11.29 TIMSK3 – Timer/Counter3 Interrupt Mask Register NA ($71) Res1 Res0 ICIE3 OCIE3C OCIE3B OCIE3A TOIE3 TIMSK3 Read/Write Initial Value • Bit 7:6 – Res1:0 - Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content.
Page 317 ATmega256/128/64RFR2 This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. • Bit 5 – ICF3 - Timer/Counter3 Input Capture Flag This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register (ICR3) is set by the WGM33:0 to be used as the TOP value, the ICF3 Flag is set when the counter reaches the TOP value.
Page 318 COM4A1:0 bit functionality when the WGM43:0 bits are set to a normal or a CTC mode (non-PWM). For the other functionality refer to section "Modes of Operation". Table 18-18 COM4A Register Bits Register Bits Value Description COM4A1:0 Normal operation Reserved Reserved Reserved •...
Page 319 ATmega256/128/64RFR2 Register Bits Value Description Fast PWM, 8-bit Fast PWM, 9-bit Fast PWM, 10-bit PWM, Phase and frequency correct, TOP = ICRn PWM, Phase and frequency correct, TOP = OCRnA PWM, Phase correct, TOP = ICRn PWM, Phase correct, TOP = OCRnA CTC, TOP = OCRnA Reserved Fast PWM, TOP = ICRn...
Page 320 Register Bits Value Description CTC, TOP = OCRnA Fast PWM, 8-bit Fast PWM, 9-bit Fast PWM, 10-bit PWM, Phase and frequency correct, TOP = ICRn PWM, Phase and frequency correct, TOP = OCRnA PWM, Phase correct, TOP = ICRn PWM, Phase correct, TOP = OCRnA CTC, TOP = OCRnA Reserved Fast PWM, TOP = ICRn...
Page 321 ATmega256/128/64RFR2 Compare Match (CTC) mode using OCR4A as TOP. The FOC4A bits are always read as zero. • Bit 6 – FOC4B - Force Output Compare for Channel B The FOC4B bit is only active when the WGM43:0 bits specify a non-PWM mode. When writing a logical one to the FOC4B bit, an immediate compare match is forced.
Page 322 The two Timer/Counter I/O locations (TCNT4H and TCNT4L, combined TCNT4) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP).
Page 323 ATmega256/128/64RFR2 18.11.38 OCR4BH – Timer/Counter4 Output Compare Register B High Byte NA ($AB) OCR4BH7:0 OCR4BH Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT4). A match can be used to generate an Output Compare interrupt.
Page 324 18.11.41 OCR4CL – Timer/Counter4 Output Compare Register C Low Byte NA ($AC) OCR4CL7:0 OCR4CL Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT4). A match can be used to generate an Output Compare interrupt.
Page 325 ATmega256/128/64RFR2 18.11.44 TIMSK4 – Timer/Counter4 Interrupt Mask Register NA ($72) Res1 Res0 ICIE4 OCIE4C OCIE4B OCIE4A TOIE4 TIMSK4 Read/Write Initial Value • Bit 7:6 – Res1:0 - Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content.
Page 326 • Bit 5 – ICF4 - Timer/Counter4 Input Capture Flag The Timer/Counter4 has only limited functionality. It does not have an Input Capture pin. Therefore this bit has no useful meaning. • Bit 4 – Res - Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content.
Page 327 ATmega256/128/64RFR2 Register Bits Value Description Reserved Reserved Reserved • Bit 5:4 – COM5B1:0 - Compare Output Mode for Channel B The Timer/Counter5 has only limited functionality. Therefore the COM5B1:0 bits do not control the output compare behavior of any pin. The following table shows the COM5B1:0 bit functionality when the WGM53:0 bits are set to a normal or a CTC mode (non-PWM).
Page 328 Register Bits Value Description PWM, Phase and frequency correct, TOP = ICRn PWM, Phase and frequency correct, TOP = OCRnA PWM, Phase correct, TOP = ICRn PWM, Phase correct, TOP = OCRnA CTC, TOP = OCRnA Reserved Fast PWM, TOP = ICRn Fast PWM, TOP = OCRnA 18.11.47 TCCR5B –...
Page 329 ATmega256/128/64RFR2 Register Bits Value Description Fast PWM, 10-bit PWM, Phase and frequency correct, TOP = ICRn PWM, Phase and frequency correct, TOP = OCRnA PWM, Phase correct, TOP = ICRn PWM, Phase correct, TOP = OCRnA CTC, TOP = OCRnA Reserved Fast PWM, TOP = ICRn Fast PWM, TOP = OCRnA...
Page 330 The FOC5B bit is only active when the WGM53:0 bits specify a non-PWM mode. When writing a logical one to the FOC5B bit, an immediate compare match is forced. Due to the limited functionality of the Timer/Counter5 the match has no direct impact on any output pin.
Page 331 ATmega256/128/64RFR2 counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers.
Page 332 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT5). A match can be used to generate an Output Compare interrupt. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP).
Page 333 ATmega256/128/64RFR2 18.11.56 OCR5CL – Timer/Counter5 Output Compare Register C Low Byte NA ($12C) OCR5CL7:0 OCR5CL Read/Write Initial Value The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT5). A match can be used to generate an Output Compare interrupt.
Page 334 18.11.59 TIMSK5 – Timer/Counter5 Interrupt Mask Register NA ($73) Res1 Res0 ICIE5 OCIE5C OCIE5B OCIE5A TOIE5 TIMSK5 Read/Write Initial Value • Bit 7:6 – Res1:0 - Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content.
Page 335 ATmega256/128/64RFR2 • Bit 5 – ICF5 - Timer/Counter5 Input Capture Flag The Timer/Counter5 has only limited functionality. It does not have an Input Capture pin. Therefore this bit has no useful meaning. • Bit 4 – Res - Reserved Bit This bit is reserved for future use.
Page 336 19 Timer/Counter 0, 1, 3, 4, and 5 Prescaler Timer/Counter 0, 1, 3, 4, and 5 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1, 3, 4, or 5. 19.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Page 337 ATmega256/128/64RFR2 Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle. Otherwise there is a risk of generating a false Timer/Counter clock pulse. Each half period of the applied, external clock must be longer than one system clock cycle to ensure correct sampling.
Page 338 This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. • Bit 1 – PSRASY - Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware.
Page 339 ATmega256/128/64RFR2 20 Output Compare Modulator (OCM1C0A) 20.1 Overview The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see "Timer/Counter 0, 1, 3, 4, and 5 Prescaler"...
Page 340 When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. 20.3 Timing Example Figure 20-3 below illustrates the modulator in action.
Page 341 ATmega256/128/64RFR2 21 8-bit Timer/Counter2 with PWM and Asynchronous Operation 21.1 Features Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: • Single channel counter • Clear timer on compare match (auto reload) • Glitch-free, phase-correct pulse-width modulator (PWM) •...
Page 342 register or bit defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value and so on. Figure 21-1. 8-bit Timer/Counter Block Diagram The definitions in Table Table 21-1 below are also used extensively throughout the section.
Page 343 ATmega256/128/64RFR2 "Asynchronous Operation of Timer/Counter2" on page 352. For details on clock sources and prescaler, see section "Timer/Counter Prescaler" on page 355. 21.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 21-2 below shows a block diagram of the counter and its surrounding environment.
Page 344 not (inverted or non-inverted PWM). For non-PWM modes the COM2x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (see chapter "Compare Match Output Unit" on page 349). For detailed timing information refer to chapter "Timer/Counter Timing Diagrams"...
Page 345 ATmega256/128/64RFR2 Figure 21-3. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn (COMnx1:0 = 1) (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
Page 346 Figure 21-4. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period The PWM frequency for the output can be calculated by the following equation: clkI OCnxPWM ⋅...
Page 347 ATmega256/128/64RFR2 includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. Figure 21-5. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2)
Page 348 • OCR2A changes its value from MAX, like in Figure 21-5 on page 347. When the OCR2A value is MAX the OCn pin value is the same as the result of a down- counting compare match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match.
Page 349 ATmega256/128/64RFR2 The OCR2x Register access may seem complex, but this is not the case. When the double buffering is enabled, the CPU has access to the OCR2x Buffer Register, and if double buffering is disabled the CPU will access the OCR2x directly. 21.6.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2x) bit.
Page 350 Figure 21-7. Compare Match Output Unit, Schematic COMnx1 Waveform COMnx0 Generator FOCn OCnx OCnx PORT 21.7.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2x1:0 bits differently in normal, CTC, and PWM modes. Setting the COM2x1:0 = 0 for all modes tells the Waveform Generator that no action on the OC2x Register is to be performed on the next compare match.
Page 351 ATmega256/128/64RFR2 COM2x1 COM2x0 Description Clear OC2x on Compare Match, set OC2x at BOTTOM, (non- inverting mode). Set OC2x on Compare Match, clear OC2x at BOTTOM, (inverting mode). Note: 1. A special case occurs when OCR2x equals TOP and COM2x1 is set. In this case, the Compare Match is ignored, but the set or clear is done at BOTTOM.
Page 352 Figure 21-9 below shows the same timing data, but with the prescaler enabled. Figure 21-9. Timer/Counter Timing Diagram, with Prescaler (f clkI/O (clk TCNTn MAX - 1 BOTTOM BOTTOM + 1 TOVn Figure 21-10 below shows the setting of OCF2A in all modes except CTC mode. Figure 21-10.
Page 353 ATmega256/128/64RFR2 • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source is: 1. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2. 2.
Page 354 C Code Example (Fragment) … do { // main loop … TRXPR = 1 << SLPTR; // disable transceiver set_sleep_mode(SLEEP_MODE_PWR_SAVE); TCNT2 = 0; // reset counter // check if busy before sleeping {} while(ASSR & (1<<TCN2UB)); sleep_enable(); sleep_cpu(); // go to deep-sleep (power- save) sleep_disable();...
Page 355 ATmega256/128/64RFR2 causing the setting of the Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. • If the CPU wakes up from asynchronous timer and goes back to sleep again, it may wakeup multiple times or the IRQ is called multiple times.
Page 356 Table 21-6. Asynchronous clock selection for Timer/Counter2 and Symbol-Counter Timer/Counter2 32 kHz crystal Osc. PG2, PG3, PG4 EXCLK EXCLKAMR clock source (TOSC1/TOSC2) as GPIOs clkI/O PG2, PG3, PG4 not defined not defined not defined 32 kHz crystal Osc TOSC1 (PG4) PG2, PG3 clkI/O PG2, PG3, PG4...
Page 357 ATmega256/128/64RFR2 • Bit 7:3 – Res4:0 - Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content. • Bit 2 – OCF2B - Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B Output Compare Register2.
Page 358 Register Bits Value Description Set OC2A on Compare Match • Bit 5:4 – COM2B1:0 - Compare Match Output B Mode These bits control the Output Compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output overrides the normal port functionality of the I/O pin it is connected to.
Page 359 ATmega256/128/64RFR2 The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is written in PWM mode operation. When writing a logical one to the FOC2A bit, an immediate Compare Match is forced on the Waveform Generation unit.
Page 360 The Timer/Counter Register gives direct access, both for read and write operations, to the 8-bit counter unit of the Timer/Counter2. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.
Page 361 ATmega256/128/64RFR2 The bit EXCLKAMR extends the available clock sources for Timer/Counter2. If this bit is written to one, and asynchronous clock is selected (bit AS2 set), AMR functionality is enabled and Timer/Counter2 is clocked by pin AMR. • Bit 6 – EXCLK - Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal.
Page 362 • Bit 7 – TSM - Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode the value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during the configuration.
Page 363 ATmega256/128/64RFR2 22 SPI- Serial Peripheral Interface 22.1 Features The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega256/128/64RFR2 and peripheral devices or between several AVR devices. The ATmega256/128/64RFR2 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer •...
Page 364 Figure 22-1. SPI Block Diagram DIVIDER /2/4/8/16/32/64/128 Note: 1. Refer to Figure 1-1 on page 2 Table 14-3 on page 226 for SPI pin placement. Figure 22-2. SPI Master-slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direction.
Page 365 ATmega256/128/64RFR2 control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles High period: longer than 2 CPU clock cycles When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 21-1.
Page 366 C Code Example void SPI_MasterInit(void) /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); void SPI_MasterTransmit(char cData) /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR &...
Page 367 ATmega256/128/64RFR2 C Code Example void SPI_SlaveInit(void) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); char SPI_SlaveReceive(void) /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR;...
Page 368 22.3.3 Data Mode There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 22-3 below Figure 22-4 below. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize.
Page 369 ATmega256/128/64RFR2 22.4 Register Description 22.4.1 SPCR – SPI Control Register $2C ($4C) SPIE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR Read/Write Initial Value • Bit 7 – SPIE - SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global Interrupt Enable bit in SREG is set.s •...
Page 370 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table. Table 22-5 SPR Register Bits Register Bits Value Description...
Page 371 ATmega256/128/64RFR2 The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read. •...
Page 372 23 USART 23.1 Features • Full duplex operation (independent serial receive and transmit registers) • Asynchronous or synchronous operation • Master or slave clocked synchronous operation • High resolution baud rate generator • Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits •...
Page 373 ATmega256/128/64RFR2 Figure 23-1. USART Block Diagram Clock Generator UBRR[H:L] BAUD RATE GENERATOR SYNC LOGIC CONTROL Transmitter UDR (Transmit) CONTROL PARITY GENERATOR TRANSMIT SHIFT REGISTER CONTROL Receiver CLOCK RECOVERY CONTROL DATA RECEIVE SHIFT REGISTER RECOVERY CONTROL PARITY UDR (Receive) CHECKER UCSRA UCSRB UCSRC Note:...
Page 374 Figure 22-2 on page 364 shows a block diagram of the clock generation logic. Figure 23-2. Clock Generation Logic, Block Diagram UBRR fosc UBRR+1 Prescaling Down-Counter txclk DDR_XCK Sync Edge Register Detector xcki UMSEL xcko DDR_XCK UCPOL rxclk Signal description: txclk Transmitter clock (internal signal).
Page 375 ATmega256/128/64RFR2 Operating Mode Equation for Calculating Equation for Calculating Baud Rate UBRR Value Synchronous Master Mode BAUD UBRRn − UBRRn BAUD Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps). Baud rate (in bits per second, bps) BAUD System oscillator clock frequency UBRRn...
Page 376 Figure 23-3. Synchronous Mode XCKn Timing UCPOL = 1 RxD / TxD Sample UCPOL = 0 RxD / TxD Sample The UCPOLn bit UCRSC selects which XCKn clock edge is used for data sampling and which is used for data change. As Figure 22-3 on page 368 shows, when UCPOLn is zero the data will be changed at rising XCKn edge and sampled at falling XCKn edge.
Page 377 ATmega256/128/64RFR2 The USART Character Size (UCSZn2:0) bits select the number of data bits in the frame. The USART Parity Mode (UPMn1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBSn) bit.
Page 378 C Code Example #define FOSC 8000000// Clock Speed #define BAUD 9600 #define (MYUBRR FOSC/16/BAUD-1) void main( void ) {... USART_Init ( MYUBRR ); ...} // main void USART_Init( unsigned int ubrr){ /* Set baud rate */ UBRRnH = (unsigned char)(ubrr>>8); UBRRnL = (unsigned char) ubrr;...
Page 379 ATmega256/128/64RFR2 Assembly Code Example USART_Transmit: ; Wait for empty transmit buffer sbis UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDRn,r16 C Code Example void USART_Transmit( unsigned char data ) /* Wait for empty transmit buffer */ while ( !( UCSRnA &...
Page 380 (1)(2) C Code Example void USART_Transmit( unsigned int data ) /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn))) ); /* Copy 9th bit to TXB8 */ UCSRnB &= ~(1<<TXB8); if ( data & 0x0100 ) UCSRnB |= (1<<TXB8);...
Page 381 ATmega256/128/64RFR2 23.6.4 Parity Generator The parity generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent. 23.6.5 Disabling the Transmitter The disabling of the transmitter (setting the TXEN to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the transmit shift register...
Page 382 C Code Example unsigned char USART_Receive( void ) /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn)) ); /* Get and return received data from buffer */ return UDRn; Note: 1. See "About Code Examples" on page 7 23.7.2 Receiving Frames with 9 Data Bits If 9 bit characters are used (UCSZn2:0=7) the 9 bit must be read from the RXB8n bit in...
Page 383 ATmega256/128/64RFR2 C Code Example unsigned int USART_Receive( void ) unsigned char status, resh, resl; /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn)) ); /* Get status and 9th bit, then data */ /* from buffer */ status = UCSRnA;...
Page 384 read (as one), and the FEn flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn flag is not affected by the setting of the USBSn bit in UCSRnC since the receiver ignores all, except for the first, stop bits.
Page 385 ATmega256/128/64RFR2 C Code Example void USART_Flush( void ) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; Note: 1. See "About Code Examples" on page 7 23.8 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception.
Page 386 shows the sampling of the data bits and the parity bit. Each of the samples is given a number that is equal to the state of the recovery unit. Figure 23-6. Sampling of Data and Parity Bit BIT n Sample (U2X = 0) Sample (U2X = 1)
Page 387 ATmega256/128/64RFR2 The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. slow fast − ⋅ Sum of character size and parity size (D = 5 to 10 bit) Samples per bit. S = 16 for normal speed mode and S = 8 for double speed mode.
Page 388 division of the system frequency to get the baud rate wanted. In this case an UBRR value that gives an acceptable low error can be used if possible. 23.9 Multi-processor Communication Mode Setting the Multi-processor Communication Mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USART receiver.
Page 389 ATmega256/128/64RFR2 Do not use read-modify-write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn flag and this might accidentally be cleared when using SBI or CBI instructions. 23.10 Register Description 23.10.1 UDR0 –...
Page 390 • Bit 5 – UDRE0 - USART Data Register Empty The UDRE0 Flag indicates if the transmit buffer (UDR0) is ready to receive new data. If UDRE0 is one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag can generate a Data Register Empty interrupt (see description of the UDRIE0 bit).
Page 391 ATmega256/128/64RFR2 Writing this bit to one enables interrupt on the UDRE0 Flag. A Data Register Empty interrupt will be generated only if the UDRIE0 bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDRE0 bit in UCSR0A is set. •...
Page 392 compare it to the UPM0 setting. If a mismatch is detected, the UPE0 Flag in UCSR0A will be set. Table 23-5 UPM0 Register Bits Register Bits Value Description UPM1:0 0x00 Disabled 0x01 Reserved 0x02 Enabled, Even Parity 0x03 Enabled, Odd Parity •...
Page 393 ATmega256/128/64RFR2 23.10.5 UBRR0H – USART0 Baud Rate Register High Byte NA ($C5) Res3 Res2 Res1 Res0 UBRR11 UBRR10 UBRR9 UBRR8 UBRR0H Read/Write Initial Value UBRR0 is a 12-bit register which contains the USART baud rate. The UBRR0H contains the four most significant bits, and the UBRR0L contains the eight least significant bits of the USART baud rate.
Page 394 Receive Data Buffer Register (RXB). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE1 Flag in the UCSR1A Register is set. Data written to UDR1 when the UDRE1 Flag is not set, will be ignored by the USART Transmitter.
Page 395 ATmega256/128/64RFR2 This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPM11 = 1). This bit is valid until the receive buffer (UDR1) is read. Always set this bit to zero when writing to UCSR1A. •...
Page 396 The UCSZ12 bits combined with the UCSZ11:0 bit in UCSR1C sets the number of data bits (Character Size) in the frame that the Receiver and Transmitter use. • Bit 1 – RXB81 - Receive Data Bit 8 RXB81 is the 9th data bit of the received character when operating with serial frames with nine data bits.
Page 397 ATmega256/128/64RFR2 Table 23-11 USBS1 Register Bits Register Bits Value Description USBS1 0x00 1-bit 0x01 2-bit • Bit 2:1 – UCSZ11:10 - Character Size The UCSZ11:0 bits combined with the UCSZ12 bit in UCSR1B sets the number of data bits (Character Size) in the frame that the Receiver and Transmitter use. Table 23-12 UCSZ1 Register Bits Register Bits Value...
Page 398 • Bit 3:0 – UBRR11:8 - USART Baud Rate Register These bits represent bits [11:8] of the Baud Rate Register. Sample values for commonly used clock frequencies can be found in section "Examples of Baud Rate Setting". 23.10.12 UBRR1L – USART1 Baud Rate Register Low Byte NA ($CC) UBRR7 UBRR6...
Page 399 ATmega256/128/64RFR2 = 1.8432 MHz = 2.0000 MHz = 3.6864 MHz Baud U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 Rate UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error (bps)
Page 400 Table 23-16. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued) = 11.0592 MHz = 14.7456 MHz = 16.0000 MHz Baud U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 Rate UBRR Error...
Page 401 ATmega256/128/64RFR2 24 USART in SPI Mode The Universal Synchronous and Asynchronous Serial Receiver and Transmitter (USART) can be set to a master SPI compliant mode of operation. The Master SPI Mode (MSPIM) has the following features: • Full duplex, three-wire synchronous data transfer •...
Page 402 24.2.1 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. For USART MSPIM mode of operation only internal clock generation (i.e. master operation) is supported. The Data Direction Register for the XCKn pin (DDR_XCKn) must therefore be set to one (i.e.
Page 403 ATmega256/128/64RFR2 UCPOLn UCPHAn SPI Mode Leading Edge Trailing Edge Setup (Falling) Sample (Rising) 24.4 Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: •...
Page 404 Assembly Code Example USART_Init: clr r18 out UBRRnH,r18 out UBRRnL,r18 ; Setting the XCKn port pin as output, enables master mode. sbi XCKn_DDR, XCKn ; Set MSPI mode of operation and SPI data mode 0. ldi r18, (1<<UMSELn1)|(1<<UMSELn0)|(0<<UCPHAn)|(0<<UCPOLn) out UCSRnC,r18 ;...
Page 405 ATmega256/128/64RFR2 UDRn is moved from the transmit buffer to the shift register when the shift register is ready to send a new frame. Note: To keep the input buffer in sync with the number of data bytes transmitted, the UDRn register must be read once for each byte transmitted. The input buffer operation is identical to normal USART mode, i.e.
Page 406 24.5.1 Transmitter and Receiver Flags and Interrupts The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and are always read as zero. 24.5.2 Disabling the Transmitter or Receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation.
Page 407 ATmega256/128/64RFR2 • Bit 5 – UDRE0 - USART Data Register Empty The UDRE0 Flag indicates if the transmit buffer (UDR0) is ready to receive new data. If UDRE0 is one, the buffer is empty, and therefore ready to be written. The UDRE0 Flag can generate a Data Register Empty interrupt (see description of the UDRIE0 bit).
Page 408 When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the data word is transmitted first. Refer to section "Frame Formats" for details. • Bit 1 – UCPHA0 - Clock Phase The UCPHA0 bit setting determines if data is sampled on the leading (first) or tailing (last) edge of XCK0.
Page 409 ATmega256/128/64RFR2 • Bit 6 – TXCIE1 - TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC1 Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE1 bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXC1 bit in UCSR1A is set.
Page 410 25 2-wire Serial Interface 25.1 Features • Simple yet powerful and flexible communication interface, only two bus lines needed • Both master and slave operation supported • Device can operate as transmitter or receiver • 7-bit address space allows up to 128 different slave addresses •...
Page 411 ATmega256/128/64RFR2 The Power Reduction TWI bit, PRTWI bit in "PRR0 – Power Reduction Register0" on page 197 must be written to zero to enable the 2-wire Serial Interface. Electrical 25.2.2 Interconnection As depicted in Figure 25-1 on page 410, both bus lines are connected to the positive supply voltage through pull-up resistors.
Page 412 Figure 25-3. START, REPEATED START and STOP conditions START STOP START REPEATED START STOP 25.3.3 Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed.
Page 413 ATmega256/128/64RFR2 pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signaled. When the Receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the Transmitter by sending a NACK after the final byte.
Page 414 • An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to Slave mode to check whether it is being addressed by the winning master.
Page 415 ATmega256/128/64RFR2 must contain the same number of data packets, otherwise the result of the arbitration is undefined. Figure 25-8. Arbitration Between Two Masters START Master A Loses Arbitration, SDA SDA from Master A SDA from Master B SDA Line Synchronized SCL Line 25.5 Overview of the TWI Module The TWI module is comprised of several sub-modules, as shown in...
Page 416 25.5.1 SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section.
Page 417 ATmega256/128/64RFR2 compare addresses even if the AVR MCU is in sleep mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0) occurs during TWI Power- down address match and wakes up the CPU, the TWI aborts operation and return to it’s idle state.
Page 418 Figure 25-10. Interfacing the Application to the TWI in a Typical Transmission 3. Check TWSR to see if START was 5. Check TWSR to see if SLA+W was 1. Application 7. Check TWSR to see if data was sent sent. Application loads SLA+W into sent and ACK received.
Page 419 ATmega256/128/64RFR2 clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent.
Page 420 Assembly Code Example C Example Comments wait2: while (!(TWCR & (1<<TWINT))); Wait for TWINT Flag set. This indicates that the SLA+W has been in r16,TWCR transmitted, and ACK/NACK has sbrs r16,TWINT been received. rjmp wait2 in r16,TWSR if ((TWSR & 0xF8) != MT_SLA_ACK) Check value of TWI Status Register.
Page 421 ATmega256/128/64RFR2 details of the following serial transfer are given in Table 25-3 on page 423 to Table 25-6 page 431. Note that the prescaler bits are masked to zero in these tables. 25.7.1 Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver (see Figure 25-11 below).
Page 422 TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR: TWCR TWINT...
Page 423 ATmega256/128/64RFR2 Table 25-3. Status codes for Master Transmitter Mode Status Code Status of the 2-wire Application Software Response (TWSR) Serial Bus and 2-wire To TWCR Prescaler Serial Interface Next Action Taken by TWI TWINT TWEA Bits are 0 Hardware To/from TWDR Hardware 0x08 A START condition has...
Page 424 Figure 25-13. Data Transfer in Master Receiver Mode DEVDD Device 1 Device 2 ..Device 3 Device n MASTER SLAVE RECEIVER TRANSMITTER A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN –...
Page 425 ATmega256/128/64RFR2 START enables the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Table 25-4. Status codes for Master Receiver Mode Status Code Status of the 2-wire Application Software Response (TWSR) Serial Bus and 2-wire To TWCR Prescaler...
Page 426 Figure 25-14. Formats and States in the Master Receiver Mode Successful DATA DATA reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave Other master Other master A or A address or data byte continues...
Page 427 ATmega256/128/64RFR2 The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR TWINT TWEA...
Page 428 0x78 Arbitration lost in No TWDR action or Data byte will be received and NOT SLA+R/W as Master; ACK will be returned General call address has No TWDR action Data byte will be received and ACK been received; ACK has will be returned been returned 0x80...
Page 429 ATmega256/128/64RFR2 0xA0 A STOP condition or No action Switched to the not addressed Slave repeated START mode; no recognition of own SLA or condition has been received while still Switched to the not addressed Slave addressed as Slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”...
Page 430 Figure 25-17. Data Transfer in Slave Transmitter Mode DEVDD Device 1 Device 2 Device 3 ..Device n SLAVE MASTER TRANSMITTER RECEIVER To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1...
Page 431 ATmega256/128/64RFR2 will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared (by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions.
Page 432 Figure 25-18. Formats and States in the Slave Transmitter Mode Reception of the own DATA DATA P or S slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. All 1’s P or S Switched to not addressed slave (TWEA = ’0’)
Page 433 ATmega256/128/64RFR2 3. The reading must be performed. 4. The transfer must be finished. Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the Slave, implying the use of the MR mode.
Page 434 will lose the arbitration. Losing masters will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. • Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits.
Page 435 ATmega256/128/64RFR2 25.9.2 TWCR – TWI Control Register NA ($BC) TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE TWCR Read/Write Initial Value The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are put into the TWDR.
Page 436 pins enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated regardless of any ongoing operation. • Bit 1 – Res - Reserved Bit This bit is reserved for future use. A read access always will return zero. A write access does not modify the content.
Page 437 ATmega256/128/64RFR2 Register Bits Value Description returned. 0x58 Data byte has been received; NOT ACK has been returned. 0x60 Own SLA+W has been received; ACK has been returned. 0x68 Arbitration lost in SLA+R/W as Master; own SLA+W has been received; ACK has been returned.
Page 438 Register Bits Value Description 0x01 0x02 0x03 25.9.4 TWDR – TWI Data Register NA ($BB) TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR Read/Write Initial Value In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received.
Page 439 ATmega256/128/64RFR2 25.9.6 TWAMR – TWI (Slave) Address Mask Register NA ($BD) TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 TWAMR Read/Write Initial Value • Bit 7:1 – TWAM6:0 - TWI Address Mask The TWAMR can be loaded with a 7-bit Slave Address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bit in the TWI Address Register (TWAR).
Page 440 26 AC – Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function.
Page 441 ATmega256/128/64RFR2 ACME ADEN MUX5 MUX2:0 Analog Comparator Negative Input ADC5 ADC6 ADC7 26.2 Register Description 26.2.1 ACSR – Analog Comparator Control And Status Register $30 ($50) ACBG ACIE ACIC ACIS1 ACIS0 ACSR Read/Write Initial Value • Bit 7 – ACD - Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off.
Page 442 • Bit 1:0 – ACIS1:0 - Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in the following table. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register.
Page 443 ATmega256/128/64RFR2 8393C-MCU Wireless-09/14...
Page 444 27 ADC – Analog to Digital Converter 27.1 Features • 10-bit Resolution • Differential Non-Linearity is less than ± 0.5 LSB • 2 LSB Integral Non-Linearity • 3 - 240 µs Conversion Time • Up to 330 kSPS (Up to 570 kSPS with 8-bit Resolution) •...
Page 445 ATmega256/128/64RFR2 The Power Reduction ADC bit, PRADC (see "PRR0 – Power Reduction Register0" on page 197) must be disabled by writing a logical zero to enable the ADC. Figure 27-1. Analog to Digital Converter Block Schematic 27.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approximation.
Page 446 changes in the course of the successive approximation process (load current steps). The internal voltage reference (except AVDD) must not be decoupled by an external capacitor. Adding unnecessary external capacitance at the AREF pin will cause instable operation of the internal reference voltage buffer and will not improve noise immunity. The analog input channel is selected by writing to the MUX bits in ADMUX and ADCSRB.
Page 447 ATmega256/128/64RFR2 possible to change the analog input channel until the AVDDOK bit changes to logic one or, if the AVDDOK bit is one, until the ADSC bit is set. 27.4 Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
Page 448 27.5 Pre-scaling and Conversion Timing 27.5.1 Prescaler By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 4 MHz. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be as high as 8 MHz to get a higher sample rate. For differential input channels the ADC clock speed is restricted to a maximum of 2 MHz.
Page 449 ATmega256/128/64RFR2 Table 27-1. Start-Up Time, Single Ended Channels Parameter Duration in ADC Clock Cycles ADC Start-Up Time t 4(ADSUT+1), minimum 20 µs ADSU Table 27-2. Start-Up Time, Differential Channels Parameter Duration in ADC Clock Cycles ADC Start-Up Time t 4(ADSUT+1), minimum 20 µs ADSU Gain Amplifier Initialization Time t 2(ADTHT+3)
Page 450 ended and differential channels. A summary is given in Table 27-3 below. All conversions take 11 ADC clock cycles. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated at the earliest after the following tracking phase.
Page 451 ATmega256/128/64RFR2 Figure 27-7. ADC Timing Diagram, Auto Triggered Conversion C o n ve rsio n T ra c kin g C o n v e rs io n A D C C lo c k A D E N T rig g e r S o u rc e A D A T E A D IF A D C H...
Page 452 After the channel or reference voltage selection is updated a settling time is required for the ADC and the gain amplifier or the reference voltage to stabilize. When changing the channel selection while the ADC is enabled the required settling phase is automatically inserted by the ADC interface, see section "ADC Input Channels"...
Page 453 ATmega256/128/64RFR2 Figure 27-10. ADC Timing Diagram, Changing MUXn during a Conversion C on version A D C S ettling A D C C lo ck M U X 5:0 O ld C hann el N ew C hanne l M U X 5:0 O ld C han nel N ew C ha nnel in te rn a l...
Page 454 If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. An external reference voltage must be supplied with a very low impedance R (see "ADC Characteristics"...
Page 455 ATmega256/128/64RFR2 depend on how much time is needed to charge the S/H capacitor, which can vary widely. The user is recommended to only use low impedance sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. The required tracking time (input sampling switch closed) t to settle to within 1 LSB DTRCK...
Page 456 27.7.4 Differential Amplifier Limitations The programmable gain, differential amplifier (PGA) converts a differential input voltage to a single-ended output voltage that is further processed with the 10 bit ADC. The performance of the PGA is determined by the physical properties of its operational amplifier: •...
Page 457 ATmega256/128/64RFR2 Figure 27-13. Gain Error Gain Output Code Error Ideal ADC Actual ADC Input Voltage • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code.
Page 458 Figure 27-15. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB 0x000 Input Voltage • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. It is always ±0.5 LSB.
Page 459 ATmega256/128/64RFR2 Figure 27-16. Differential Measurement Range Output code 0x1FF 0x000 /GAIN Differential Input /GAIN 0x3FF voltage (Volts) 0x200 Table 27-7. Correlation Between Input Voltage and Output Codes Read Code Corresponding Decimal Value ADCn / GAIN 0x1FF ADCm + 0.999 V / GAIN 0x1FF ADCm...
Page 460 27.9 Internal Temperature Measurement The on-chip temperature can be measured using a special setup of the A/D converter inputs. The integrated temperature sensor provides a linear, medium-accurate voltage proportional to the absolute temperature (in Kelvin). This voltage is first amplified with the programmable gain amplifier and then processed with the A/D converter.
Page 461 ATmega256/128/64RFR2 run_cmd, (1<<ADEN)+(1<<ADSC)+(4<<ADPS0) run_conversion: ADCSRA, run_cmd wait_adsc: r17, ADCSRA sbrc r17, ADSC ; flag cleared at conversion complete rjmp wait_adsc r18, ADCL ; measured temperature in ADCL and ADCH r19, ADCH … The above Assembly code example enables the temperature measurement step by step.
Page 462: Dvss
connected to a differential input channel with a gain of 10. The voltage offset error of the differential signal processing can be corrected to the first order by using an appropriate similar channel (e.g. MUX4:0=01000, MUX5=0, see Table 27-12 on page 465).
Page 463: Devdd
ATmega256/128/64RFR2 The A/D conversion result will always be a positive number for both V DRTBBP . The SRAM supply voltage is easily calculated according to the following DRTBBN equation (see chapter "SRAM with Data Retention" on page 193): − SRAM DRTBBP DRTBBN The conversion result is coded as described in...
Page 464 27.12 Register Description 27.12.1 ADMUX – ADC Multiplexer Selection Register NA ($7C) REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX Read/Write Initial Value • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in the following table. Changes of these bits will take effect until a conversion start is requested by setting ADSC.
Page 465 ATmega256/128/64RFR2 • Bit 6 – ACME: Analog Comparator Multiplexer Enable This bit is used for the Analog Comparator only. See "ADCSRB – ADC Control and Status Register B" on page 442 for details. • Bit 5 – REFOK: Reference Voltage OK The status of the internal generated reference voltage can be monitored through this bit.
Page 466 Single Ended Positive Differential Negative Differential MUX5:0 Input Input Input Gain 010100 ADC4 ADC1 010101 ADC5 ADC1 010110 ADC6 ADC1 010111 ADC7 ADC1 011000 ADC0 ADC2 011001 ADC1 ADC2 011010 ADC2 ADC2 011011 ADC3 ADC2 011100 ADC4 ADC2 011101 ADC5 ADC2 011110 1.2V (V...
Page 467 ATmega256/128/64RFR2 Single Ended Positive Differential Negative Differential MUX5:0 Input Input Input Gain 111101 SRAM Back-bias Voltage V DRTBBN 111110 Reserved 111111 Reserved Note: 1. EVDD measurement is not available in ATmega128RFA1. • Bits 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an A/D conversion.
Page 468 • Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB.
Page 469 ATmega256/128/64RFR2 • Bits 5:0 – ADSUT5:0: ADC Start-up Time These bits define the number of ADC clock cycles for the start-up time of the analog blocks. For a complete description of this bit, see "Pre-scaling and Conversion Timing" on page 448.
Page 470 • Bits 7:0 – ADC7D:ADC0D: Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set.
Page 471 ATmega256/128/64RFR2 Register Bits Value Description Setting for highest voltage Setting for lowest voltage • Bit 2:0 – BGCAL2:0 - Coarse Calibration Bits These bits allow the calibration of the AREF voltage with a resolution of 10mV. Table 27-16 BGCAL Register Bits Register Bits Value Description...
Page 472 "Programming via the JTAG Interface" on page 525, respectively. The on-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Figure 28-1 on page 473 shows a block diagram of the JTAG interface and the on-chip debug system.
Page 473 ATmega256/128/64RFR2 Figure 28-1. Block Diagram I/O PORT 0 DEVICE BOUNDARY BOUNDARY SCAN CHAIN JTAG PROGRAMMING INTERFACE CONTROLLER AVR CPU INTERNAL FLASH Address SCAN MEMORY Data INSTRUCTION CHAIN Instruction REGISTER REGISTER BREAKPOINT UNIT FLOW CONTROL BYPASS UNIT REGISTER DIGITAL ANALOG PERIPHERAL Analog inputs PERIPHERAL UNITS...
Page 474 Figure 28-2. TAP Controller State Diagram Test-Logic-Reset Run-Test/Idle Select-DR Scan Select-IR Scan Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR 28.4 TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or on-chip debug system.
Page 475 ATmega256/128/64RFR2 selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.
Page 476 Breakpoints, alternatively combined as a mask (range) breakpoint. 28.7 On-chip Debug Specific JTAG Instructions The on-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Instruction operation codes are listed for reference. 28.7.1 PRIVATE0; 0x8 Private JTAG instruction for accessing on-chip debug system;...
Page 477 ATmega256/128/64RFR2 The JTAG programming capability supports: • Flash programming and verifying. • EEPROM programming and verifying. • Fuse programming and verifying. • Lock bit programming and verifying. The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase.
Page 478 29 IEEE 1149.1 (JTAG) Boundary-scan 29.1 Features • JTAG (IEEE std. 1149.1 compliant) Interface • Boundary-scan Capabilities According to the JTAG Standard • Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections • Supports the Optional IDCODE Instruction •...
Page 479 Table 31-6 on page 507. 29.3.2.3 Manufacturer ID The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed in Table 31-6 on page 507. 29.3.3 Reset Register The Reset Register is a test Data Register used to reset the part. Since the AVR tri- states Port Pins when reset, the Reset Register can also replace the function of the unimplemented optional JTAG instruction HIGHZ.
Page 480 Figure 29-2. Reset Register From Other Internal and External Reset Sources From Internal reset ClockDR · AVR_RESET 29.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections.
Page 481 ATmega256/128/64RFR2 The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input. 29.4.3 SAMPLE_PRELOAD; 0x2 Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation.
Page 482 When no alternate port function is present, the Input Data - ID - corresponds to the PINxn Register value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data Direction - DD Register, and the Pull-up Enable - PUExn –...
Page 483: Clki
ATmega256/128/64RFR2 Figure 29-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn DDxn RESET OCxn ODxn PORTxn IDxn RESET SLEEP SYNCHRONIZER PINxn PUD: PULLUP DISABLE WDx: WRITE DDRx PUExn: PULLUP ENABLE for pin Pxn RDx: READ DDRx OCxn: OUTPUT CONTROL for pin Pxn WRx: WRITE PORTx...
Page 484 29.5.3 Scanning the RSTON Pin For the low-active reset output pin RSTON a boundary-scan cell as shown in Figure 29-6 below is inserted. Figure 29-6. Boundary-scan Cell for Output Pins without Pull-up Function 29.6 Boundary-scan Related Register in I/O Memory For detailed register description see chapter "MCUCR –...
Page 485 ATmega256/128/64RFR2 The MCU Status Register provides information on which reset source caused an MCU reset. • Bit 4 – JTRF - JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET.
Page 486 Table 29-1. ATmega256/128/64RFR2 Boundary-Scan Order Number Signal Name Module Number Signal Name Module PF1.Control CLKI.Data Clock Input (Input Only) PF1.Data PD7.Control Port F PF0.Control PD7.Data PF0.Data PD6.Control PE7.Control PD6.Data PE7.Data PD5.Control PE6.Control PD5.Data PE6.Data PD4.Control PE5.Control PD4.Data Port D PE5.Data PD3.Control PE4.Control PD3.Data...
Page 487 ATmega256/128/64RFR2 30 Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program.
Page 488 30.3 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader software update is dependent on the address that is being programmed. In addition to the two sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While-Write (NRWW) section.
Page 489 ATmega256/128/64RFR2 programming is completed, the RWWSB must be cleared by software before reading code located in the RWW section. See "SPMCSR – Store Program Memory Control Register" on page 501 for details on how to clear RWWSB. 30.3.2 NRWW – No Read-While-Write Section The code located in the NRWW section can be read when the Boot Loader software is updating a page in the RWW section.
Page 490 30.4 Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection.
Page 491 ATmega256/128/64RFR2 Since the Flash is organized in pages (see "Table 31-7" on page 507), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages.
Page 492 and Page Write operation is addressing the same page. For an assembly code example "Simple Assembly Code Example for a Boot Loader" on page 496. 30.6.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
Page 493 ATmega256/128/64RFR2 30.6.6 Prevent Reading the RWW Section During Self-Programming During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW section is busy.
Page 494 the next page. Refer to (see "Table 31-5" on page 506) for a detailed description and mapping of the Fuse Low byte. FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 Similarly, load 0x0003 in the Z-pointer for reading the Fuse High byte. When an (E)LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below.
Page 495 ATmega256/128/64RFR2 Assembly Code Example SPMCSR, r16 ; write SPMCSR r4, Z+ SPMCSR, r16 ; write SPMCSR r5, Z+ Table 30-3. Signature Row Addressing Signature Byte Z-Pointer Address Device Signature Byte 1 0x0000 Device Signature Byte 2 0x0002 Device Signature Byte 3 0x0004 RC Oscillator Calibration Byte 0x0001...
Page 496 30.6.12 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 30-4 below shows the typical programming time for Flash accesses from the CPU. Table 30-4. SPM Programming Time Symbol Min Programming Time Max Programming Time Flash write (Page Write, and write 3.7 ms...
Page 497 ATmega256/128/64RFR2 Assembly Code Example subi ZL, low(PAGESIZEB) ;restore pointer sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcrval, (1<<PGWRT) | (1<<SPMEN) call Do_spm ; re-enable the RWW section ldi spmcrval, (1<<RWWSRE) | (1<<SPMEN) call Do_spm ; read back and check, optional ldi looplo, low(PAGESIZEB) ;init loop variable ldi loophi, high(PAGESIZEB)
Page 498 Assembly Code Example ; SPM timed sequence out SPMCSR, spmcrval ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 Notes: 1. See "About Code Examples" on page 30.6.14 Boot Loader Parameters for 64 kByte of Flash Memory Table 30-5 below through Table 30-7 on...
Page 499 ATmega256/128/64RFR2 Table 30-7. Boot Size Configuration with 64 kByte of Flash Memory 0x0000 – 0x7E00 – 0x7DFF 0x7E00 words 0x7DFF 0x7FFF 1024 0x0000 – 0x7C00 – 0x7BFF 0x7C00 words 0x7BFF 0x7FFF 2048 0x0000 – 0x7800 – 0x77FF 0x7800 words 0x77FF 0x7FFF 4096 0x0000 –...
Page 500 Corresponding Variable Value Z-value Description Program Counter word address: Word PCWORD PC[6:0] Z7:Z1 select, for filling temporary buffer (must be zero during Page Write operation) Notes: 1. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction. 2.
Page 501 ATmega256/128/64RFR2 Corresponding Variable Value Z-value Description Bit in Z-pointer that is mapped to PCMSB. ZPCMSB Z17:Z16 Because Z0 is not used, the ZPCMSB equals PCMSB + 1. Bit in Z-pointer that is mapped to PCMSB. ZPAGEMSB Because Z0 is not used; the ZPAGEMSB equals PAGEMSB + 1.
Page 502 • Bit 7 – SPMIE - SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCR register is cleared.
Page 503 ATmega256/128/64RFR2 instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z pointer. The LSB of the Z pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles.
Page 504 31 Memory Programming 31.1 Program And Data Memory Lock Bits The ATmega256/128/64RFR2 provides six Lock bits which can be left un-programmed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 31-2 below. The Lock bits can only be erased to “1” with the Chip Erase command. Table 31-1.
Page 505 ATmega256/128/64RFR2 Memory Lock Bits Protection Type BLB1 Mode BL12 BL11 No restrictions for SPM or (E)LPM accessing the Boot Loader section. SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and (E)LPM executing from the Application section is not allowed to read from the Boot Loader section.
Page 506 Fuse High Byte Bit No Description Default Value EESAVE EEPROM memory is preserved 1 (un-programmed, through the Chip Erase EEPROM not preserved) BOOTSZ1 Select Boot Size (see Table 30- 0 (programmed) 10 on page 500 for details) BOOTSZ0 Select Boot Size (see Table 30- 0 (programmed) 10 on page...
Page 507 ATmega256/128/64RFR2 31.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. For the ATmega256/128/64RFR2...
Page 508 31.7 Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, Fuse bits ATmega256/128/64RFR2. 31.7.1 Signal Names In this section, some pins of the ATmega256/128/64RFR2 are referenced by signal names describing their functionality during parallel programming;...
Page 509 ATmega256/128/64RFR2 Signal Name in Programming Mode Pin Name Function Byte Select 2. Bi-directional Data bus (Output when OE ¯ ¯ ¯ is DATA PB7-0 low). Table 31-10. BS2 and BS1 Encoding Flash / EEPROM Flash Data Fuse Reading Fuse Address Loading / Reading Programming and Lock Bits...
Page 510 Table 31-14. Command Byte Bit Encoding (EEPROM Erase, User Signature Data) Command Byte Command Executed 1000 0010 Chip Erase EEPROM only 1000 0011 Erase EEPROM Page 0001 0010 Write User Signature Page 1000 0100 Erase User Signature Page 0000 1000 Read User Signature Page "User Signature Data"...
Page 511 ATmega256/128/64RFR2 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give CLKI a positive pulse. This loads the command. 5. Give WR a negative pulse.
Page 512 that if less than eight bits are required to address words in the page (page size < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. G. Load Address High byte (Address bits15:8) 1.
Page 513 ATmega256/128/64RFR2 Figure 31-5. Addressing the Flash which is Organized in Pages PCMSB PAGEMSB PROGRAM PCPAGE PCWORD COUNTER PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]: PAGE INSTRUCTION WORD PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 31-7 on page 507.
Page 514 K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS2, BS1 to “00”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 31- 7 below...
Page 515 ATmega256/128/64RFR2 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. 31.8.9 Programming the Fuse High Bits The algorithm for programming the Fuse High bits is as follows (refer to "Programming...
Page 516 31.8.12 Reading the Fuse and Lock Bits The algorithm for reading the Fuse and Lock bits is as follows (refer to "Programming the Flash" on page 511 for details on Command and Data loading): 1. A: Load Command “0000 0100”. 2.
Page 517 ATmega256/128/64RFR2 31.8.15 Chip Erase of EEPROM only This special Chip Erase command will erase only the EEPROM memory. The Flash, Lock and Fuse bits are not changed. The EEPROM must be erased before it can be reprogrammed. Note: 1. The EEPROM memory is also preserved during this special Chip Erase if the EESAVE Fuse is programmed.
Page 518 2. B. Load Address Low byte (Address bits 7:0). 3. C. Load Data Low Byte (0x00 - 0xFF). 4. D. Load Data High Byte (0x00 - 0xFF). 5. E. Latch Data (give PAGEL a positive pulse). F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
Page 519 ATmega256/128/64RFR2 1. A: Load Command “0000 1000”. 2. G: Load Address High Byte. 2. B: Load Address Low Byte. 3. Set OE to “0” and BS to “0”. The Signature word low byte can now be read at DATA. 4. Set OE to “1”.
Page 520 Figure 31-12. Parallel programming reading sequence (within the same page) with timing requirements LOAD ADDRESS READ DATA READ DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE) XLOL CLKI BVDV OLDV OHDZ DATA (High Byte) ADDR1 (Low Byte) DATA ADDR0 (Low Byte) DATA (Low Byte)
Page 521 ATmega256/128/64RFR2 Notes: 1. t is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock WLRH bits commands. 2. t is valid for the Chip Erase command. WLRH_CE 31.9 Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using a serial programming bus while RSTN is pulled to DVSS.
Page 522 Low: > 2 CPU clock cycles for f < 12 MHz, 3 CPU clock cycles for f >= 12 MHz; High: > 2 CPU clock cycles for f < 12 MHz, 3 CPU clock cycles for f >= 12 MHz; 31.9.2 Serial Programming Algorithm When writing serial data to the ATmega256/128/64RFR2, data is clocked on the rising edge of SCK.
Page 523 ATmega256/128/64RFR2 8. Power-off sequence (if needed): Set RESET to “1”. Turn DEVDD power off. Table 31-17. Minimum Wait Delay before writing the next Fuse/Flash/EEPROM location Symbol Minimum Wait Delay 4.5 ms WD_FUSE 4.5 ms WD_FLASH 13 ms WD_EEPROM 18.5 ms WD_CHIPERASE 31.9.3 Serial Programming Instruction Set Table 31-18 below...
Page 524 4. To ensure future compatibility, unused Fuses and Lock bits should be un-programmed (‘1’). 5. Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes and Page size. 6. See http://www.atmel.com/avr for Application Notes regarding programming and programmers. If the LSB in RDY/BSY ¯...
Page 525 ATmega256/128/64RFR2 31.10 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed.
Page 526 Figure 31-16. State Machine Sequence for Changing the Instruction Word Test-Logic-Reset Select-DR Scan Select-IR Scan Run-Test/Idle Capture-DR Capture-IR Shift-DR Shift-IR Exit1-DR Exit1-IR Pause-DR Pause-IR Exit2-DR Exit2-IR Update-DR Update-IR 31.10.2 AVR_RESET (0xC) The AVR specific public JTAG instruction is used for setting the AVR device in the Reset mode or taking the device out from the Reset mode.
Page 527 ATmega256/128/64RFR2 • Update-DR: The programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid. 31.10.4 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction is used for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register.
Page 528 • Programming Enable Register • Programming Command Register • Flash Data Byte Register 31.10.8 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low.
Page 529 ATmega256/128/64RFR2 Figure 31-18. Programming Command Register Flash EEPROM Fuses Lock Bits Table 31-19. JTAG Programming Instruction (set a = address high bits, b = address low bits, c = address extended bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care) Instruction TDI Sequence TDO Sequence...
Page 530 Instruction TDI Sequence TDO Sequence Notes 3c. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx 3d. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 0110010_00000000 xxxxxxx_xxxxxxxx 3e. Read Data Low and High Byte 0110110_00000000 xxxxxxx_oooooooo Low byte 0110111_00000000 xxxxxxx_oooooooo High byte 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b.
Page 531 ATmega256/128/64RFR2 Instruction TDI Sequence TDO Sequence Notes 7b. Load Data Byte 0010011_11iiiiii xxxxxxx_xxxxxxxx (4)(9) 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 7c. Write Lock Bits 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx 8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx 0111010_00000000...
Page 532 Notes: 1. This command sequence is not required if the seven MSB’s are correctly set by the previous command sequence (which is normally the case). 2. Repeat until o = “1”. 3. Set bits to “0” to program the corresponding Fuse, “1” to un-program the Fuse. 4.
Page 533 ATmega256/128/64RFR2 31.10.11 Flash Data Byte Register The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer before executing Page Write, or to read out/verify the content of the Flash. A state machine sets up the control signals to the Flash and senses the strobe signals from the Flash, thus only the data words need to be shifted in/out.
Page 534 31.10.12 Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 31-19 on page 529. 31.10.13 Entering Programming Mode 7. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 8. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Programming Enable Register.
Page 535 ATmega256/128/64RFR2 Data Byte Register into the Flash page location and to auto-increment the Program Counter before each new word. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2h. 8. Poll for Flash write complete using programming instruction 2i, or wait for t (refer WLRH Table 31-15 on page...
Page 536 31.10.19 Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM.
Page 537 ATmega256/128/64RFR2 5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 31.10.24 Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3.
Page 538 31.10.27 Programming User Signature Data Three Flash pages are dedicated for user signature data (see "User Signature Data" on page 507 for details). Before programming the user signature pages a Page Erase must be performed, see section "Erasing User Signature Data" below.
Page 539 ATmega256/128/64RFR2 7. Poll for Flash write complete using programming instruction 2i, or wait for t (refer WLRH Table 31-15 on page 520). 8. Repeat steps 4 to 7 until all user signature data have been erased. 31.10.29 Reading User Signature Data The algorithm for reading User Signature Data is similar to read from Flash.
Page 540 32 Application Circuits 32.1 Basic Application Schematic A basic application schematic of the ATmega256/128/64RFR2 with a single-ended RF connector is shown in Figure 32-1 below and the associated Bill of Material in Table 32- 1 on page 541. The 50Ω single-ended RF input is transformed to the 100Ω differential RF port impedance using Balun B1.
Page 541 ATmega256/128/64RFR2 Capacitors should be placed as close as possible to the pins and should have a low- resistance and low-inductance connection to ground to achieve the best performance. The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the 16MHz crystal oscillator for the 2.4GHz transceiver.
Page 542 • RX/TX Indicator using alternate pin function DIG3/4 at Port G and F An extended feature set application schematic illustrating the use of the ATmega256/128/64RFR2 Extended Feature Set, is shown in Figure 32-2 below. Figure 32-2. Extended Feature Application schematic XTAL DVSS ANT0...
Page 543 ATmega256/128/64RFR2 33 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x1FF) TRXFBEND TRXFBEND7 TRXFBEND6 TRXFBEND5 TRXFBEND4 TRXFBEND3 TRXFBEND2 TRXFBEND1 TRXFBEND0 (0x180) TRXFBST TRXFBST7 TRXFBST6 TRXFBST5 TRXFBST4 TRXFBST3 TRXFBST2 TRXFBST1 TRXFBST0...
Page 544 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x145) PHY_TX_PWR Res3 Res2 Res1 Res0 TX_PWR3 TX_PWR2 TX_PWR1 TX_PWR0 (0x144) TRX_CTRL_1 PA_EXT_EN IRQ_2_EXT_EN TX_AUTO_CRC_ON PLL_TX_FLT Res3 Res2 Res1 Res0 (0x143) TRX_CTRL_0 Res7 PMU_EN...
Page 545 ATmega256/128/64RFR2 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xF6) SCOCR1LH SCOCR1LH7 SCOCR1LH6 SCOCR1LH5 SCOCR1LH4 SCOCR1LH3 SCOCR1LH2 SCOCR1LH1 SCOCR1LH0 (0xF5) SCOCR1LL SCOCR1LL7 SCOCR1LL6 SCOCR1LL5 SCOCR1LL4 SCOCR1LL3 SCOCR1LL2 SCOCR1LL1 SCOCR1LL0 (0xF4) SCOCR2HH SCOCR2HH7...
Page 546 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xB2) TCNT2 TCNT27 TCNT26 TCNT25 TCNT24 TCNT23 TCNT22 TCNT21 TCNT20 (0xB1) TCCR2B FOC2A FOC2B Res1 Res0 WGM22 CS22 CS21 CS20 (0xB0) TCCR2A COM2A1 COM2A0...
Page 547 ATmega256/128/64RFR2 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x6F) TIMSK1 Res1 Res0 ICIE1 OCIE1C OCIE1B OCIE1A TOIE1 (0x6E) TIMSK0 Res4 Res3 Res2 Res1 Res0 OCIE0B OCIE0A TOIE0 (0x6D) PCMSK2 PCINT23 PCINT22...
Page 548 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 0x0B (0x2B) PORTD...
Page 549 ATmega256/128/64RFR2 Mnemonics Operands Description Operation Flags #Clocks Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V Increment Rd ← Rd + 1 Z,N,V Decrement Rd ← Rd − 1 Z,N,V Test for Zero or Minus Rd ←...
Page 550 Mnemonics Operands Description Operation Flags #Clocks BRSH Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2 BRLO Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2 BRMI...
Page 551 ATmega256/128/64RFR2 Mnemonics Operands Description Operation Flags #Clocks Set Signed Test Flag S ← 1 Clear Signed Test Flag S ← 0 Set Twos Complement Overflow V ← 1 Clear Twos Complement Overflow V ← 0 Set T in SREG T ← 1 Clear T in SREG T ←...
Page 552 Mnemonics Operands Description Operation Flags #Clocks ELPM Extended Load Program Memory R0 ← (RAMPZ:Z) None ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None ELPM Rd, Z+ Extended Load Program Memory Rd ← (RAMPZ:Z), None RAMPZ:Z ← RAMPZ:Z+1 Store Program Memory (Z) ←...
Page 553 ATmega256/128/64RFR2 35 Electrical Characteristics 35.1 Absolute Maximum Ratings Note that stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied.
Page 554 35.3 Digital Pin Characteristics Test Conditions: T = -40°C to 125°C, V =1.8V to 3.6V (unless otherwise stated) Symbol Parameter Condition Units High level input voltage Except pin RSTN 0.7 V Low level input voltage Except pin RSTN 0.3 V High level input voltage Pin RSTN 0.9 V...
Page 555 ATmega256/128/64RFR2 35.5 Power Supply Currents (RF transceiver in SLEEP mode) Test Conditions: T = 25°C, V =3.0V (unless otherwise stated) Symbol Parameter Condition / AVR mode Units Power Supply Current Standby mode 0.31 SUPPLY (PRR0=0xFF, PRR1=0x3F, Idle 1MHz 0.45 16MHz RC Oscillator selected) Idle 8MHz Idle 16MHz Active 1MHz...
Page 556 Load capacitance as specified by the 12.5 LOAD32 crystal manufacturer Shunt capacitance SHUNT32 Internal parasitic capacitance PAR32 Equivalent series resistance Crystal @ 32.768 kHz kΩ 35.6.3 External Clock Drive (pin CLKI) Figure 35-1 External Clock Drive Waveforms Table 35-3. External Clock Drive Symbol Parameter Min.
Page 557 ATmega256/128/64RFR2 Table 35-5. Reset, Brown-out and Internal Voltage Characteristics Symbol Parameter Condition Units RSTN Pin Threshold Voltage 0.1V 0.9V Minimum pulse width on RSTN Pin Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset Bandgap reference voltage = 3.0V, T = 25°...
Page 558 Symbol Parameter Condition Min. Typ. Max. Units Max. load current during ramp-up Current limitation is applied to ramp-up only. RAMPMAX 35.8.3 Low-Leakage Voltage Regulator (1,2) Table 35-28. Timing Characteristics of the Low-Leakage Voltage Regulator Symbol Parameter Condition Min. Typ. Max. Units Calibration time After power-on or wake-up from DEEP_SLEEP...
Page 559: Characterized
ATmega256/128/64RFR2 35.9 2-wire Serial Interface Characteristics Table 35-11 below describes the requirements for devices connected to the 2-wire Serial Bus. The ATmega256/128/64RFR2 2-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 35-2 on page 560.
Page 560 5. This requirement applies to all the ATmega256/128/64RFR2 2-wire Serial Interface operation. Other devices connected to the 2-wire Serial Bus need only obey the general f requirement. 6. The actual low period generated by the ATmega256/128/64RFR2 2-wire Serial interface is (1/f –...
Page 561 ATmega256/128/64RFR2 Figure 35-3. SPI timing Requirements (Master Mode) (CPOL = 0) (CPOL = 1) MISO (Data Input) MOSI (Data Output) Figure 35-4. SPI timing Requirements (Slave Mode) (CPOL = 0) (CPOL = 1) MOSI (Data Input) MISO (Data Output) 35.11 ADC Characteristics Table 35-13.
Page 562 (1)(2) Table 35-14. ADC Characteristics, Single Ended Channels Symbol Parameter Condition Units Single Ended Conversion f ≤ 4 MHz Bits RES4M CLKADC Resolution Single Ended Conversion f = 8 MHz Bits RES8M CLKADC Single Ended Conversion ABS500k = 1.6V = 500kHz CLKADC Absolute accuracy (Including Single Ended Conversion...
Page 563: Characterized
ATmega256/128/64RFR2 Symbol Parameter Condition Units Gain = 1x Offset Error OFFSET,D1 = 1.6V = 2MHz CLKADC Conversion Time Free Running Conversion µs CONV,D Clock Frequency Single Ended Conversion CLKADC Reference Voltage AVDD Input Common Mode Voltage EVDD Input Differential Voltage Input pin voltage ≥...
Page 564 Symbol Parameter Condition Min. Typ. Max. Units AES core cycle time µs Interrupt event latency Relative to the event on the RF pins to be µs indicated (e.g. TRX24_RX_END interrupt) Battery monitor latency µs BATMON 35.14.2 General RF Specifications Test Conditions (unless otherwise stated): = 3.0V, f = 2.45 GHz, T = 25°C, Measurement setup see...
Page 565 ATmega256/128/64RFR2 Symbol Parameter Condition Min. Typ. Max. Units Harmonics HARM harmonic harmonic Spurious Emissions Complies with SPUR 30 – ≤ 1000 MHz EN 300 328/440, >1 – 12.75 GHz FCC-CFR-47 part 15, 1.8 – 1.9 GHz ARIB STD-66, RSS-210 5.15 – 5.3 GHz 35.14.4 Receiver Characteristics Test Conditions (unless otherwise stated): = 3.0V, f...
Page 566 Symbol Parameter Condition Min. Typ. Max. Units RSSI resolution RSSI sensitivity Defined as RSSI_BASE_VAL Minimum RSSI value ≤ RSSI_BASE_VAL Maximum RSSI value > RSSI_BASE_VAL + 81 dB Note: 1. Offset equals ±120 ppm 35.14.5 Current Consumption Specifications Test Conditions (unless otherwise stated): = 3.0V, f = 2.45 GHz, T = 25°C, Measurement setup see...
Page 567 ATmega256/128/64RFR2 Symbol Parameter Condition Min. Typ. Max. Units 16MHz XTAL oscillator off-time Minimum sleep time of the transceiver XTALOFF 36 Typical Characteristics 36.1 Supply Current vs. Clock Speed with Transceiver in SLEEP 36.1.1 Clock source 16MHz RC Oscillator Figure 36-5. Active Supply Current vs. Frequency (V = 3.0V, PRR0/1 = 0xFF/0x3F) 125°C 85°C...
Page 568 Figure 36-6. Active Supply Current vs. V =1MHz, PRR0/1 = 0xFF/0x3F) 125° C 85° C 25° C -40° C EVDD [V] Figure 36-7. Active Supply Current vs. V = 16MHz, PRR0/1 = 0x00/0x00) 125°C 85°C 25°C -40° C EVDD [V] ATmega256/128/64RFR2 8393C-MCU Wireless-09/14...
Page 569 ATmega256/128/64RFR2 Figure 36-8. Idle Supply Current vs. V = 1MHz; PRR0/1 = 0xFF/0x3F) 125° C 85° C 25° C -40° C EVDD [V] Figure 36-9. Idle Supply Current vs. V = 8MHz, PRR0/1 = 0xFF/0x3F) 125° C 85° C 25° C -40°...
Page 570 36.1.2 External clock source on pin CLKI Figure 36-10. Active Supply Current vs. Frequency (V = 3.0V, PRR0/1 = 0x00/0x00) 125° C 85° C 25° C -40° C 10.0 12.0 14.0 16.0 Frequency [MHz] CLK [MHz] Figure 36-11. Active Supply Current vs. Frequency (V = 3.0V, PRR0/1 = 0xFF/0x3F) 125°...
Page 571 ATmega256/128/64RFR2 Figure 36-12. Idle Supply Current vs. Frequency (V = 3.0V, PRR0/1 set and reset) 125° C no PRR 85° C no PRR 25° C no PRR -40° C no PRR 125° C PRR set 85° C PRR set 25° C PRR set -40°...
Page 572 Figure 36-14. TRXOFF state supply current vs V 125° C 85° C 25° C -40° C EVDD [V] Figure 36-15. RX_ON state supply current vs. V 125° C 85° C 25° C -40° C EVDD [V] ATmega256/128/64RFR2 8393C-MCU Wireless-09/14...
Page 573 ATmega256/128/64RFR2 Figure 36-16. RX_ON State Supply Current vs. V , RPC Enabled 125° C 85° C 27° C -40° C EVDD [V] Figure 36-17. RX_ON State Supply Current, RPC Enabled, RX_PDT_LEVEL = 15 125° C 85° C 27° C -40° C EVDD [V] 8393C-MCU Wireless-09/14...
Page 574 Figure 36-18. TX Active state supply current vs. V (maximum TX output power) 125°C 85°C 25°C -40° C EVDD [V] 36.4 RF Measurements For all RF power measurement results the calibration level is the differential RF input of the device. It enables an easy calculation for the different RF front-ends with external power amplifier and/or RF switches (diversity, RX/TX).
Page 575 ATmega256/128/64RFR2 36.4.2 Transmit Power Figure 36-20. TX maximum output power -40 °C 25 ° C 85 ° C 125 ° C Supply Voltage [V] Figure 36-21. TX output power vs. TX_PWR in register PHY_TX_PWR -40 ° C 25 ° C 85 °...
Page 576 36.5 BOD Threshold Figure 36-22. Brown-out Threshold vs. Temperature (Rising Supply Voltage) BOD_LEVEL=2.4 BOD_LEVEL=2.3 BOD_LEVEL=2.2 BOD_LEVEL=2.1 BOD_LEVEL=2.0 BOD_LEVEL=1.9 BOD_LEVEL=1.8 -40.0 -20.0 20.0 40.0 60.0 80.0 100.0 120.0 Temperature [°C] Figure 36-23. Brown-out Threshold vs. Temperature (Falling Supply Voltage) BOD_LEVEL=2.4 BOD_LEVEL=2.3 BOD_LEVEL=2.2 BOD_LEVEL=2.1 BOD_LEVEL=2.0...
Page 577 ATmega256/128/64RFR2 36.6 Pin Driver Strength Figure 36-24. I/O Pin Output Voltage vs. Source Current (V = 3.0V, DPDS0=0) 0.45 125°C 25° C 85° C -40 ° C 0.35 0.25 0.15 0.05 IOH [mA] Figure 36-25. I/O Pin Output Voltage vs. Source Current (25° C, DPDS0=0) EVDD=1.8 EVDD=2.4 EVDD=3.0...
Page 578 Figure 36-26. I/O Pin Output Voltage vs. Source Current (25° C, V = 3.0V) 0.45 DPD=0 DPD=1 DPD=2 DPD=3 0.35 0.25 0.15 0.05 10.0 15.0 20.0 25.0 30.0 IOH [mA] Figure 36-27. I/O Pin Output Voltage vs. Sink Current (V =3.0V, DPDS0 = 0) 0.45 125°...
Page 579 ATmega256/128/64RFR2 Figure 36-28. I/O Pin Output Voltage vs. Sink Current (25° C, DPDS0=1) 125 degC 0.25 85 degC 25 degC -40 degC 0.15 0.05 I_OL [mA] Figure 36-29. I/O Pin Output Voltage vs. Sink Current (25° C, V = 3.0V) 0.45 DPD=1 DPD=0...
Page 580 36.7 Power-Down Current Figure 36-30. Power-Down Current vs. Temperature (Watchdog Disabled) 3.6V 3.0V 1.8V Temperature [° C] Figure 36-31. Power-Down Current vs. Supply Voltage (Watchdog Disabled) 125° C 85° C 25° C -40° C ATmega256/128/64RFR2 8393C-MCU Wireless-09/14...
Page 581 ATmega256/128/64RFR2 Figure 36-32. Power-Down Current vs. Temperature (Watchdog Enabled) 3.6V 3.0V 1.8V Temperature [° C] Figure 36-33. Power-Down Current vs. Supply Voltage (Watchdog Enabled) 125°C 85° C 25° C -40° C 36.8 Static ADC Parameter – INL and DNL All static parameter of the ADC have been obtained with f = 2 MHz, SUT = 10, ADCLK THT = 0 and an internal reference voltage of 1.6V.
Page 582 Figure 36-34. Integral Nonlinearity vs. Output Code (Single-Ended, 3.0V, 25°C) -0.2 -0.4 1024 Digital Output Code Figure 36-35. Differential Nonlinearity vs. Output Code (Single-Ended, 3.0V, 25°C) -0.1 -0.2 -0.3 1024 Digital Output Code ATmega256/128/64RFR2 8393C-MCU Wireless-09/14...
Page 583 ATmega256/128/64RFR2 Figure 36-36. Integral Nonlinearity vs. Output Code (with PGA, Gain=10, 3.0V, 25° C) -1.0 -2.0 -3.0 -4.0 -512 -384 -256 -128 Digital Output Code Figure 36-37. Differential Nonlinearity vs. Output Code (with PGA, Gain=10, 3.0V, 25° C) -0.2 -0.4 -512 -384 -256...
Page 584 Figure 36-38. Integral Nonlinearity vs. Temperature at V = 3.6V DEVDD Gain = 200 Gain = 10 Gain = 1 Single Ended Temperature [° C] Figure 36-39. Integral Nonlinearity vs. Supply Voltage at 25° C Gain = 200 Gain = 10 Gain = 1 Single Ended ATmega256/128/64RFR2...
Page 585 ATmega256/128/64RFR2 Figure 36-40. Differential Nonlinearity vs. Temperature at V = 3.6V EVDD Gain = 200 Gain = 10 Gain = 1 Single Ended Temperature [° C] Figure 36-41. Differential Nonlinearity vs. Supply Voltage V at 25° C EVDD Gain = 200 Gain = 10 Gain = 1 Single Ended...
Page 586 wave of the input signal had a frequency of f = 20.207 kHz and peak-to-peak IN,SIN amplitude of V = 1.58V. IN,PP Figure 36-42. 2048 Point FFT Output for a Single-Ended ADC Channel (3.0V, 25 ° C) 20.21; 0.00 SINAD = 57.54 dB ENOB = 9.27 bit = -63.08 dB...
Page 587 ATmega256/128/64RFR2 The dynamic ADC parameters for the differential channels with a gain of 10 have been measured with f = 2 MHz, SUT = 10, THT = 0 and an internal reference voltage of ADCLK 1.6V. The input sine wave had a frequency of f = 20.124 kHz and peak-to-peak IN,SIN amplitude of V...
Page 588 36.10 ADC Voltage Reference Figure 36-46. 1.6V ADC Voltage Reference vs. Supply Voltage 1.63 1.62 1.61 125° C 85° C 1.60 27° C 1.59 -40° C 1.58 1.57 1.56 36.11 Temperature Sensor The temperature measurement results have been measured with an ADC clock of 500 kHz, SUT = 80, THT = 4 and an internal reference voltage of 1.6V.
Page 589 ATmega256/128/64RFR2 Figure 36-47. Measured Temperature Value vs. Temperature and V EVDD 3.6V 3.0V 1.8V Temperature [° C] Figure 36-48. Error of Measured Temperature Value θ – θ vs. Temperature MEAS IDEAL 3.0V Temperature [° C] 8393C-MCU Wireless-09/14...
Page 590 Figure 36-49. Standard Deviation of Measured Temperature vs. Temperature 3.0V -0.2 Temperature [° C] 36.12 Internal Oscillator Speed Figure 36-50. 128 kHz RC Oscillator Frequency vs. OSCCAL Register Value 125° C 85° C 25° C -40° C OSCCAL ATmega256/128/64RFR2 8393C-MCU Wireless-09/14...
Page 591 ATmega256/128/64RFR2 Figure 36-51. 128 kHz RC Oscillator Frequency vs. Supply Voltage 125° C 85° C 25° C -40° C Figure 36-52. 16 MHz RC Oscillator Frequency vs. OSCCAL Register Value 125° C 85° C 25° C -40° C OSCCAL 8393C-MCU Wireless-09/14...
Page 592 Figure 36-53. 16 MHz RC Oscillator Frequency vs. Supply Voltage V DEVDD 125° C 85° C 25° C -40° C 36.13 Programming Current The programming currents shown in the following figures are averaged over the entire write/erase time. The value is primarily defined by the integrated charge pump. Therefore the currents for Flash, EEPROM, Fuse- and Lock-bit programming operations are similar.
Page 593 ATmega256/128/64RFR2 Figure 36-54. Programming Current vs. Supply Voltage V DEVDD -40° C 25° C 85° C 125° C 8393C-MCU Wireless-09/14...
Page 594 1. Pb-free packaging, complies to European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 2. Performance figures for 125° C are only valid for devices with ordering code ATmega256RFR2-ZF/-ZFR. Package Type 64-lead, 9 x 9 x 0.9 mm Body, Quad Flat No-lead Package (QFN)
Page 595 ATmega256/128/64RFR2 ATmega128RFR2 Speed (MHz) Power Supply Ordering Code Package Packing Operation Range 1.8 – 3.6V ATmega128RFR2-ZU Tray Industrial (-40° C to 85° C) 1.8 – 3.6V ATmega128RFR2-ZUR Tape & Reel Industrial (-40° C to 85° C) 1.8 – 3.6V ATmega128RFR2-ZF Tray Industrial (-40°...
Page 596 ATmega64RFR2 Speed (MHz) Power Supply Ordering Code Package Packing Operation Range 1.8 – 3.6V ATmega64RFR2-ZU Tray Industrial (-40° C to 85° C) 1.8 – 3.6V ATmega64RFR2-ZUR Tape & Reel Industrial (-40° C to 85° C) 1.8 – 3.6V ATmega64RFR2-ZF Tray Industrial (-40°...
Page 597 PACKAGE WARPAGE MAX 0.08 mm. DRAWING No. REV. TITLE Atmel Nantes S.A. PI - 64 leads - 9.0 x 9.0 mm - pitch 0.5mm La Chantrerie - BP 70602 44306 Nantes Cedex 3 - France Quad Flat No Lead Package QFN...
Page 598 39 Errata 39.1 ATmega256RFR2 revision D • Interrupt restrictions in Deep-sleep Mode • Device does not enter Deep-Sleep if no crystal is connected to XTAL pins 39.2 ATmega256RFR2 revision C • Interrupt restrictions in Deep-sleep Mode • Device does not enter Deep-Sleep if no crystal is connected to XTAL pins 39.3 ATmega256RFR2 revision B...
Page 599 ATmega256/128/64RFR2 39.9.2 PMU shows erroneous behavior with a 3µs period The results from the phase measurement unit (PMU) depend on the length of the initial delay between a frequency change and the start of the phase measurement process (software timer). If the timer delay is increased then after adding 3µs, the same results are achieved.
Page 600 PRR1 = (1 << PRTRX24); /* power-off transceiver */ SMCR = (2 << SM0) | (1 << SE); if (MCUCR & (1 << IVSEL)) go_sleep_boot(); else go_sleep_appl(); /* back from sleep here */ SMCR = 0; Linker options to relocate the interrupt functions to the required memory address the linker need to have following options added (related to 256kByte FLASH memory configuration): ….
Page 601 ATmega256/128/64RFR2 40 Revision history Please note that the referring page numbers in this section are referring to this document. The referring revision in this section are referring to the document revision Rev. 8393C-MCU Wireless-09/14 1. Routing of divided EVDD voltage to the comparator added in the chapter "EVDD Voltage Measurement"...
Page 602 ATmega256/128/64RFR2 8393C-MCU Wireless-09/14...
Page 603: Table Of Contents
ATmega256/128/64RFR2 Table of Contents Features ....................1 Applications ................... 1 1 Pin Configurations ................2 2 Disclaimer .................... 2 3 Overview ....................3 3.1 Block Diagram ......................3 3.2 Pin Descriptions...................... 5 3.3 Unused Pins ......................7 3.4 Compatibility to ATmega128RFA1 ................. 7 4 Resources....................
Page 604 9.3 Transceiver to Microcontroller Interface ............... 34 9.4 Operating Modes ....................38 9.5 Functional Description ..................67 9.6 Module Description ....................80 9.7 Radio Transceiver Usage ..................90 9.8 Radio Transceiver Extended Feature Set ............92 9.9 Continuous Transmission Test Mode ..............107 9.10 Abbreviations ....................
Page 605 ATmega256/128/64RFR2 12.2 AVR Microcontroller Sleep Modes ..............186 12.2.6 Extended Standby Mode ................188 12.3 Power Reduction Register ................188 12.4 Minimizing Power Consumption ............... 189 12.5 Supply Voltage and Leakage Control ............... 191 12.6 Register Description ..................196 13 System Control and Reset ............209 13.1 Resetting the AVR ....................
Page 606 18.1 Features ......................276 18.2 Overview ......................276 18.3 Accessing 16-bit Registers ................278 18.4 Timer/Counter Clock Sources ................281 18.5 Counter Unit ..................... 281 18.6 Input Capture Unit .................... 282 18.7 Output Compare Units ..................284 18.8 Compare Match Output Unit ................286 18.9 Modes of Operation ..................
Page 607 ATmega256/128/64RFR2 22.4 Register Description ..................369 23 USART.................... 372 23.1 Features ......................372 23.2 Overview ......................372 23.3 Clock Generation ....................373 23.4 Frame Formats ....................376 23.5 USART Initialization ..................377 23.6 Data Transmission – The USART Transmitter ..........378 23.7 Data Reception –...
Page 608 27.2 Operation ......................445 27.3 ADC Start-Up....................446 27.4 Starting a Conversion ..................447 27.5 Pre-scaling and Conversion Timing ..............448 27.6 Changing Channel or Reference Selection ............451 27.7 ADC Noise Canceller ..................454 27.8 ADC Conversion Result ................... 458 27.9 Internal Temperature Measurement ..............
Page 609 ATmega256/128/64RFR2 30.5 Addressing the Flash During Self-Programming ..........490 30.6 Self-Programming the Flash ................491 30.7 Register Description ..................501 31 Memory Programming ..............504 31.1 Program And Data Memory Lock Bits .............. 504 31.2 Fuse Bits ......................505 31.3 Signature Bytes ....................507 31.4 User Signature Data ..................
Page 610 36.13 Programming Current ..................592 37 Ordering Information ..............594 38 Packaging Information ..............597 39 Errata ..................... 598 39.1 ATmega256RFR2 revision D ................598 39.2 ATmega256RFR2 revision C ................598 39.3 ATmega256RFR2 revision B ................598 39.4 ATmega256RFR2 revision A ................598 39.5 ATmega128RFR2 revision D ................
Page 611 Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products.

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