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Atmel AT91CAP7E Specifications
Atmel AT91CAP7E Specifications

Atmel AT91CAP7E Specifications

Cap customizable microcontrollers

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AT91CAP7E
AT91CAP7E is an ARM7™-based MCU with a direct FPGA interface, six-layer advanced high-speed
bus (AHB), peripheral DMA controller and 160 Kbytes of on-chip SRAM. It offers seamless migration to
AT91CAP7 customizable MCUs for ARM7-plus-FPGA designs. It includes on-chip peripherals such as
USB 2.0 full speed device, SPI master and slave, two USARTs, three 16-bit timer counters, an 8-channel/
10-bit analog to digital converter, plus a full-functioned system controller including interrupt and power
control and supervisory functions.
The FPGA interface on the AT91CAP7E provides the FPGA with direct access to the AT91CAP7E's
on-chip AHB and peripheral DMA controller. This architecture eliminates FPGA-induced bus contention,
off-loads MCU-to-FPGA communications from the CPU, and frees up the external bus interface for
external memory access.
Interfacing an ARM7-based MCU to an FPGA has traditionally been done through the external bus
interface (EBI) or programmable I/O. Either arrangement requires that the CPU transfer data to and from
System Controller
PLL
Main
OSC
PLL
WDT
PMC
PIT
AIC
32K OSC
RTT
RC OSC
POR
GPBREG
SHWDC
POR
AT91CAP7E
APB
the FPGA one word-at-a-time, basically stealing CPU cycles that should be conserved for processing and
limiting access to external memory during FPGA operations.
The FPGA interface on Atmel's AT91CAP7E provides the FPGA with two AHB masters, four AHB slaves,
a special direct AHB slave interface to an external RAM through the FPGA, and a programmable ROM
that remaps the external RAM to emulate and debug the ROM code. Fourteen advanced peripheral bus
(APB) slaves, two full-duplex DMA channels and 32-bit programmable I/O may be hardware selected to
share I/O. An on-chip priority interrupt controller provides up to 13 encoded interrupts and two additional
un-encoded interrupts for DMA transfers.
JTAG
ICE
ARM7TDMI
SRAM
SRAM
96KB
64KB
6 -layer AHB Matrix
ROM (256KB)
AMBA Bridge
USB
PIO
Timer
FS
SPI
x3
x32
Device
CAP
CUSTOMIZABLE MICROCONTROLLERS
TM
FPGA Interface
Peripheral DMA
Controller
USART
USART
ADC
EBI
Static Mem.
CF
NAND Flash
SDRAM

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Summary of Contents for Atmel AT91CAP7E

  • Page 1 FPGA operations. The FPGA interface on Atmel’s AT91CAP7E provides the FPGA with two AHB masters, four AHB slaves, a special direct AHB slave interface to an external RAM through the FPGA, and a programmable ROM that remaps the external RAM to emulate and debug the ROM code.
  • Page 2 OSC32 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. ExCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY ExPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.