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Implementation of DDR2 on AT91SAM9G45
1. Scope
The AT91SAM9G45 microprocessor features:
• One multi-port DDR2 controller that supports 16-bit DDR2 or 16-bit LP-DDR
memories only
• One single-port DDR2 controller that supports 16-bit DDR2, 16-bit LP-DDR, 16- or
32-bit SDR or LP-SDR memories through the EBI
The purpose of this document is to help the developer in the design of a system utiliz-
ing DDR2. Each DDR2 controller is described separately.
Devices
AT91 ARM
Thumb-based
Microcontrollers
Application Note
6492A–ATARM–22-Sep-09
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Summary of Contents for Atmel AT91SAM9G45
- Page 1 Implementation of DDR2 on AT91SAM9G45 Devices 1. Scope The AT91SAM9G45 microprocessor features: • One multi-port DDR2 controller that supports 16-bit DDR2 or 16-bit LP-DDR AT91 ARM memories only • One single-port DDR2 controller that supports 16-bit DDR2, 16-bit LP-DDR, 16- or...
- Page 2 2. Multi-Port DDR2 Controller Overview The DDR2 controller (DDR2C) extends the memory capabilities of a chip by providing the interface to an external 16-bit DDR2 device. The page size supports ranges from 2048 to 16384, and a number of columns from 256 to 4096. It supports byte (8-bit) and half-word (16-bit) accesses.
- Page 3 Application Note 3. Multi-Port DDR2 Controller Signals Definition The DDR2 controller is capable of managing 4-bank DDR2 devices. The signals generated by the controller are defined below. Table 3-1. DDR2 Controller Signals DDR_D0 - DDR_D15 Data Bus VDDIOM0 Pulled-up input at reset DDR_A0 - DDR_A13 Address Bus Output...
- Page 4 the bus. The conjunction with Write Enable (DDR_WE) and chip select (SDCS), at the rising edge of the clock (DDR_CK) or the falling edge of the #clock (#DDR_CK), determines the DDR2 operation. DDR_DQM[0..1]: Data is accessed in 8 or 16 bits by means of DDR_DQM[1..0], which are respectively the highest to lowest mask bit for the DDR2 data on the bus.
- Page 5 Application Note 4. EBI DDR2 Controller Overview The EBI embeds a single-port DDR2 controller (DDR2SDRC) that extends the memory capabil- ities of a chip by providing the interface to 16-bit DDR2, 16-bit LP-DDR, 16-bit or 32-bit SDR or LD-SDR external devices. The page size supports ranges from 2048 to 16384, and a number of columns from 256 to 4096.
- Page 6 5. EBI DDR2 Controller Signals Definition The DDR2 controller is capable of managing four-bank DDR2 devices. The signals generated by the controller are defined below (refer to the EBI Section on the product Datasheet). Table 5-1. EBI Controller Signals D0 - D31 Data Bus VDDIOM1 Pulled-up input at reset...
- Page 7 Application Note RAS - CAS, SDWE: The row address strobe (RAS), column address strobe (CAS) will assert to indicate that the corresponding address is present on the bus. The conjunction with write Enable (SDWE) and chip select (SDCS) at the rising edge of the clock (SDCK) determines the SDRAM operation.
- Page 8 6. DDR2 Connexion on AT91SAM9 Multi-Port Controller The AT91SAM9G45 microprocessor supports 16-bit DDR2 devices on DDR/LPDDR Chip Select area (0x70000000 memory zone). The user interface to configure the DDR2 controller is mapped at address 0xFFFF E600. Each DDR2 device must use sufficient decoupling to provide an efficient filtering on the power supply rails.
- Page 9 7. DDR2 Connexion on AT91SAM9 EBI Controller The AT91SAM9G45 microcontroller supports 16-bit DDR2 devices on one Chip Select area ( N C S 1 ) . T h e u s e r i n t e r f a c e t o c o n f i g u r e t h e D D R 2 c o n t r o l l e r i s m a p p e d a t address 0xFFFF E400.
- Page 10 8. DDR2 Signal Routing Considerations The critical high speed signal is associated with the DDR2. The following are general guidelines for designing a DDR2 interface with AT91SAM9 products with a targeted speed of 133 MHz on SDCK/#SDCK: • At first, position the DDR2 devices as close to the processor as possible. A longer trace will increase the rise time and the fall time of the signals.
- Page 11 High Speed MCI and EBI signals. Refer to the Product Datasheet for more details. Over-Shoots Over-shoots occur when the current driven is too high. The AT91SAM9G45 microprocessor embeds drive control on memory signals. Refer to the Product Datasheet for more details.
- Page 12 10. DDR2 VREF Signal Considerations DDR_VREF is used by the input buffers of the DDR2 memories and the DDR2 controller to determine logic levels. VREF is specified to be 0.9V (½ the power supply voltage) and is created using a voltage divider constructed from two 1.5 kOhm, 1% tolerance resistors. DDR_VREF is not a high current supply, but it is important to keep it as quiet as possible with minimal inductance.
- Page 13 11.1 DDR2-SDRAM Initialization The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following sequence: (For a register description, see DDR2-SDRAM Initialization section on the AT91SAM9G45 Datasheet) (For an example of initialization, see the “Appendix” 1. Program the memory device type into the Memory Device Register.
- Page 14 Micron MT47H64M8 The Micron MT47H64M8 are 64 MB devices arranged as 16 Mbit x 8 x 4 banks with a CAS latency of 3 at 133 MHz. These devices are featured on the AT91SAM9G45-EKES and AT91SAM9M10G45-EK evaluation kits. Application Note...
- Page 15 Application Note The following table gives the delay in ns extracted from the DDR2-SDRAM datasheet, the corre- sponding number of cycles at 133 MHz, and the field to program these values accordingly. Description Register/Field Value System PLL Frequency 800 MHz PMC_PLLAR 0x20c73f03 Processor / Bus Clock...
- Page 16 Description Register/Field Value Exit Self Refresh Delay to Read Command 200 cycles 200 cycles TXSRD 0xc8 Exit Power-down Delay to First Command 2 cycles 2 cycles 0x00000107 DDRSDRC Timing 2 Register DDRSDRC_T2PR Exit Active Power Down Delay to Read Command (Fast Exit) 2 cycles 2 cycles TXARD...
- Page 17 Application Note 12. Appendix Here is an example of the DDR2 initialization code, associated to the different steps introduced Section 11.1 “DDR2-SDRAM Initialization” on page //*---------------------------------------------------------------------------- //* \fn ddram_init //* \brief Initialization of the DDR Controller //*---------------------------------------------------------------------------- int ddram_init(unsigned int ddram_controller_address, unsigned int ddram_address, struct SDdramConfig *ddram_config) volatile unsigned int i;...
- Page 18 // Initialization Step 5: Set All Bank Precharge write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD); *((unsigned volatile int*) ddram_address) = 0; // wait 400 ns min for (i = 0; i < 100; i++) { asm(" nop"); // Initialization Step 6: Set EMR operation (EMRS2) write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_EXT_LMR_CMD);...
- Page 19 Application Note // Initialization Step 11: Set All Bank Precharge write_ddramc(ddram_controller_address, HDDRSDRC2_MR, AT91C_DDRC2_MODE_PRCGALL_CMD); *(((unsigned volatile int*) ddram_address)) = 0; // wait 400 ns min for (i = 0; i < 100; i++) { asm(" nop"); // Initialization Step 12: Two auto-refresh (CBR) cycles are provided. Program the auto refresh // command (CBR) into the Mode Register.
- Page 20 // Initialization Step 17: Program OCD field into the Configuration Register to low (OCD // calibration mode exit). cr = read_ddramc(ddram_controller_address, HDDRSDRC2_CR); write_ddramc(ddram_controller_address, HDDRSDRC2_CR, cr & (~AT91C_DDRC2_OCD_EXIT)); // Initialization Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD // exit.
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Page 21: Revision History
Application Note Revision History Change Doc. Rev Comments Request Ref. 6492A First issue 6492A–ATARM–22-Sep-09... - Page 22 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY...
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