Mbcg46183-129 (Xv833A00) Gate Array; Ym3436Dk (Xg948E00) Dir2 (Digital Format Interface Receiver) - Yamaha PM 5000 Series Service Manual

MBCG46183-129 (XV833A00) Gate Array

PIN
NAME I/O
NO.
1 D5 I/O
2 D6 I/O Data Bus
3 D7 I/O
4 /IRQ0 I/O Interrupt Request Port 0
5 /IRQ1 I/O Interrupt Request Port 1
6 Vss Ground
7 /IRQ2 I/O Interrupt Request Port 2
8 IRQ3 I/O Interrupt Request Port 3
9 /RD I Read Signal Input
10 /WR I Write Signal Input
11 /CE I Chip Enable Input
12 /ASTB I Address Strobe (Not used: to ground)
13 TESTSIO I Input with Pull-down Resistor (50 k)
14 RX0 I Receive Data 0
15 TX0 O Transmit Data 0
16 RX1 I Receive Data 1
17 TX1 O Transmit Data 1
18 Vss Ground
19 Vdd Power Supply
20 RX2 I Receive Data 2
21 TX2/BO2 O Transmit Data 2
22 RX30 I Receive Data 30
23 TX30 O Transmit Data 30
24 TX31 I Receive Data 31

YM3436DK (XG948E00) DIR2 (Digital Format Interface Receiver)

PIN
NAME I/O
NO.
1 DAUX I Auxiliary input for audio data
2 HDLT O Asynchronous buffer operation flag
3 DOUT O Audio data output
4 VFL O Parity flag output
5 OPT O Fs x 1 Synchronous output signal for DAC
6 SYNC O Fs x 1 Synchronous output signal for DSP
7 MCC O Fs x 64 Bit clock output
8 WC O Fs x 1 Word clock output
9 MCB O Fs x 128 Bit clock output
10 MCA O Fs x 256 Bit clock output
11 SKSY I Clock synchronization control input
12 XI I Crystal oscillator connection or external
clock input
13 XO O Crystal oscillator connection
14 P256 O VCO oscillating clock connection
15 LOCK O PLL lock flag
16 Vss Logic section power (GND)
17 TC O PLL time constant switching output
18 DIM1 I Data input mode selection
19 DIM0 I Data input mode selection
20 DOM1 I Data output mode selection
21 DOM0 I Data output mode selection
22 KM1 I Clock mode switching input 1
FUNCTION
FUNCTION
PIN
NAME I/O
NO.
25 TX31 O Transmit Data 31
26 RX32 I Receive Data 32
27 TX32 O Transmit Data 32
28 RX33 I Receive Data 33
29 TX33 I/O Transmit Data 33
30 /IC I Initial Clear
31 Vss Ground
32 XI I Quartz Crystal Input
33 Vss Ground
34 XO I/O Quartz Crystal Onput
35 A0 I
36 A1 I
37 A2 I
Address Bus
38 A3 I
39 A4 I
40 A5 I
41 CPUCLK I CPU Clock
42 Vss Ground
43 Vdd Power Supply
44 D0 I/O
45 D1 I/O
46 D2 I/O Data Bus
47 D3 I/O
48 D4 I/O
PIN
NAME I/O
NO.
23 RSTN I System reset input
24 Vdda VCO section power (+5 V)
25 CTLN I VCO control input N
26 PCO O PLL phase comparison output
27 (NC)
28 CTLP I VCO control input P
29 Vssa VCO section power (GND)
30 TSTN I Test terminal. Open for normal use
31 KM2 I Clock mode switching input 2
32 KM0 I Clock mode switching input 0
33 FS1 O Channel status sampling frequency
display output 1
34 FS0 O Channel status sampling frequency
display output 0
35 CSM I Channel status output method selection
36 EXTW I External synchronous auxiliary input
word clock
37 DDIN I EIAJ (AES/EBU) data input
38 LR O PLL word clock output
39 Vdd Logic section power (+5 V)
40 ERR O Data error flag output
41 EMP O Channel status emphasis control code
output
42 CD0 O 3-wire type microcomputer interface data
output
43 CCK I 3-wire type microcomputer interface clock
input
44 CLD I 3-wire type microcomputer interface load
input
PM5000
MAINCPU: IC128, 129
FUNCTION
MAINCPU: IC141
FUNCTION
99