Neoway N75 Hardware User's Manual
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Neoway N75 Hardware User's Manual

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N75
Hardware User Guide
Issue 1.0
Date 2019-05-23
Neoway Product Document

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Summary of Contents for Neoway N75

  • Page 1 Hardware User Guide Issue 1.0 Date 2019-05-23 Neoway Product Document...
  • Page 2 THIS GUIDE PROVIDES INSTRUCTIONS FOR CUSTOMERS TO DESIGN THEIR APPLICATIONS. PLEASE FOLLOW THE RULES AND PARAMETERS IN THIS GUIDE TO DESIGN AND COMMISSION. NEOWAY WILL NOT TAKE ANY RESPONSIBILITY OF BODILY HURT OR ASSET LOSS CAUSED BY IMPROPER OPERATIONS. THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE DUE TO PRODUCT VERSION UPDATE OR OTHER REASONS.

  • Page 3: Table Of Contents

    Hardware User Guide Contents 1 About N75 ....................1 1.1 Product Overview ......................... 1 1.2 Block Diagram ..........................2 1.3 Basic Features ..........................3 2 Module Pins ....................5 2.1 Pad Layout ........................... 5 2.2 Pin Description ..........................6 3 Application Interfaces ................14 3.1 Power Interface ..........................
  • Page 4 A.1 Approvals ........................... 82 A.2 American Notice ......................... 82 A.2.1 Modify ..........................82 A.2.2 FCC Class A Digital Device Notice ................... 82 A.2.3 FCC Class B Digital Device Notice ................... 82 Abbreviation .................... 84 Copyright © Neoway Technology Co., Ltd...
  • Page 5 Hardware User Guide Table of Figures Figure 1-1 Block Diagram ........................2 Figure 2-1 N75 pin definition (Top View) .................... 5 Figure 3-1 Current peaks and voltage drops (GSM/GPRS) ............15 Figure 3-2 Recommended design 1 ....................15 Figure 3-3 Recommended design 2 ....................16 Figure 3-4 Recommended design 3 ....................
  • Page 6 Figure 3-52 Reference design of active GNSS antenna ..............56 Figure 3-53 Reference layout of GNSS antenna traces ..............57 Figure 3-54 Specifications of MM9329-2700RA1 ................58 Figure 3-55 RF connections ......................58 Figure 3-56 Pulse wave for an incoming call ................... 62 Copyright © Neoway Technology Co., Ltd...
  • Page 7 Figure 3-60 Outgoing call service process ..................64 Figure 3-61 Process of exiting from sleep mode ................64 Figure 3-62 Reference design of USB_BOOT ................. 65 Figure 6-1 N75 dimensions ......................74 Figure 6-2 N75 label ......................... 75 Figure 7-1 Bottom view ........................78 Figure 7-2 Recommended Application Foot Print (Top View) ............
  • Page 8 Table 3-15 Timing parameters of SDIO/WLAN interface ..............49 Table 3-16 MUX pins ........................59 Table 4-1 Electric features ........................ 66 Table 4-2 Current consumption of N75 .................... 66 Table 4-3 Temperature features ....................... 68 Table 4-4 ESD protection features ....................69 Table 5-1 Operating Bands ......................
  • Page 9 Scope This document is applicable to N75 series. It defines the features, indicators, and test standards of the N75 module and provides reference for the hardware design of each interface. Reference designs in this document are only for reference. Customers should design applications based on the actual scenarios and conditions.Please contact Neoway FAE if you have any question or...
  • Page 10 Hardware User Guide Related Documents Neoway_N75_Datasheet Neoway_N75_Product_Specifications Neoway_N75_AT_Command_Manual Neoway_N75_EVK_User_Guide Neoway Module Reflow Manufacturing Recommendations Copyright © Neoway Technology Co., Ltd...

  • Page 11: About N75

    GNSS functions, N75 is well applicable to wireless metering terminals, in-vehicle terminals, POS, industrial routers, and other IoT terminals. 1.1 Product Overview N75 series include multiple variants. Table 1-1 lists the variants and frequency bands supported. Table 1-1 Variant and frequency bands Variant...

  • Page 12: Block Diagram

    Hardware User Guide 1.2 Block Diagram N75 consists of the following functionality units: Baseband ⚫ ⚫ Power management unit ⚫ 19.2MHz crystal oscillator ⚫ RF section ⚫ Digital interfaces (USIM, SPI, I2C, SGMII, SDIO, ADC, GPIO, UART, USB) ⚫ Figure 1-1 Block Diagram...

  • Page 13: Basic Features

    GSM850: (33dBm±2dB) (Power Class 4) PCS1900: (30dBm± 2dB) (Power Class 1) EDGE 850MHz: (27dBm± 3dB) (Power Class E2) Transmit power EDGE1900MHz: (26dBm±3dB) (Power Class E2) UMTS: (24dBm+1/-3dB) (Power Class 3) LTE: (23dBm±2dB) (Power Class 3) Copyright © Neoway Technology Co., Ltd...
  • Page 14 One SGMII/MDIO interface, used for Ethernet Four GPIO interfaces AT Command Neoway extended commands Data PPP, RNDIS, ECM, RMNET Protocol TCP, UDP, MQTT, FTP/FTPS, HTTP/HTTP(S), SSL, TLS Certification FCC, PTCRB, AT&T, CE-R, GCF, RoHS, NCC*, RCM* approval Copyright © Neoway Technology Co., Ltd...

  • Page 15: Module Pins

    Hardware User Guide 2 Module Pins There are 100 pins on N75 and their pads are introduced in LGA package. 2.1 Pad Layout Figure 2-1 shows the pad layout of N75. Figure 2-1 N75 pin definition (Top View) Copyright © Neoway Technology Co., Ltd...

  • Page 16: Pin Description

    = 0.3V IH min IL max 1.8V digital IO voltage =1.35V, V = 0.45V OH min OL max 1.8V: =1.27V~2V, =1.8V~3.15V, interface voltage, = -0.3V~0.58V = -0.3V~0.7V compatible with 1.8V/2.85V =1.4V~1.8V, =2.1V~2.85V, =0V~0.45V =0V~0.36V Copyright © Neoway Technology Co., Ltd...

  • Page 17: Table 2-2 Pin Description

    30, 31, 44, 49, Connect all GND 74, 75, 77, 91, Ground pins to the ground 93, 95, 97, 98, plane. 99, 100 Control Interfaces Triggered by low RESET_N Module reset input level to reset the module. Copyright © Neoway Technology Co., Ltd...
  • Page 18 USB_DP USB data plus Leave this USB_ID OTG detect floating if it is not used. ADC interface 15-bit, detectable =1.7V; Analog-to-digital signal voltage ranging ADC2 conversion =0.1V from 0.1V to 1.7V Leave this Copyright © Neoway Technology Co., Ltd...
  • Page 19 I2S/PCM interface I2S_1_SCLK I2S serial clock Multiplexed I2S_1_DOUT I2S data transmit Leave this I2S_1_DIN I2S data receive floating if it is not used. I2S_1_WS I2S word select Copyright © Neoway Technology Co., Ltd...
  • Page 20 Leave this Control WLAN WLAN_PWR_EN floating if it is not external power used. Do not pull this pin LTE/WLAN co-exist high during WCI_LTE_RXD/USB_B UART data startup receive/forcible module. download mode control Otherwise, module enters Copyright © Neoway Technology Co., Ltd...
  • Page 21 SDC command Leave them floating if they are SDC_CLK SDC clock output not used. SDC_DATA0 SDC data0 IO SDC_DATA1 SDC data1 IO Leave this SDC_DET SD card detect floating if it is not used. Copyright © Neoway Technology Co., Ltd...
  • Page 22 Sleep mode control floating if it is not used. Do not pull this pin External power high before OTG_5V_EN enable module is powered Leave this NET_LIGHT Network status indicator floating if it is not used. Copyright © Neoway Technology Co., Ltd...
  • Page 23 Hardware User Guide Leave this GNSS_LNA_EN GNSS LNA enable floating if it is not used. RESERVED Leave it floating Copyright © Neoway Technology Co., Ltd...

  • Page 24: Application Interfaces

    Hardware User Guide 3 Application Interfaces N75 provides power supply, control, communications, network and connection, RF, and other interfaces to meet customers requirements in different application scenarios. This chapter describes how to design each interface and provides reference designs and guidelines.

  • Page 25: Figure 3-1 Current Peaks And Voltage Drops (Gsm/Gprs)

    The power supply design covers two parts: schematic design and PCB layout. Schematic Design Design the circuit of the power supply for N75 based on the input voltage you choose.Generally there are three types of input voltages: 3.3V-4.3V (3.8 V typically, output by battery) ⚫...

  • Page 26: Figure 3-3 Recommended Design 2

    If a digital NPN bipolar transistor is used, Omit R1 and R2. TVS diodes work in the same way as those in Figure 3-2 and they should meet the same ⚫ requirements. Figure 3-4 shows schematic design recommended for 4.3V-5.5V input. Copyright © Neoway Technology Co., Ltd...

  • Page 27: Figure 3-4 Recommended Design 3

    500 kHz or larger switching frequency is recommended for DC-DC. The inductance depends on ⚫ the switching frequency. The switching frequency might produce EMC noise and it determines the performance of end products. For more design guidelines, see TPS54340 datasheet. ⚫ Copyright © Neoway Technology Co., Ltd...

  • Page 28: Vdd_1P8

    Connect GND pins and bottom pads to ground to optimize heat sink and separate noise. ⚫ 3.1.2 VDD_1P8 N75 provides one VDD_1P8 output, load current lower than 50 mA. It is recommended that VDD_1P8 is used only for level shift and digital IO power supply. An ESD Copyright © Neoway Technology Co., Ltd...

  • Page 29: Control Interfaces

    ON/OFF button Triggered by low level (recommended) N750 provides PWRKEY_N and RESET_N to power up and reset the module respectively. 3.2.1 PWRKEY_N N75 allows startup by the following controls: Button ⚫ ⚫ The values of R1 and R2 are determined by the IO domain of MCU. The voltage across the base of the triode should not exceed 1.8V.

  • Page 30: Figure 3-7 Reference Design Of Startup Controlled By Mcu

    Do not perform other operations on the module until it is initialized completely. If the module is powered up but the startup process has not been completed, the states of each pin are uncertain. Copyright © Neoway Technology Co., Ltd...

  • Page 31: Reset_N

    If you use a 2.8V/3.3V IO system, it is recommended to add a triode to separate it. For details, refer to 3.2.2 RESET_N. For how to power off through software, see Neoway_N75_AT_Command_Manual. Figure 3-9 N75 on/off timing Power Power Inactive...

  • Page 32: Figure 3-10 Reset Controlled By Button

    Figure 3-11 Reset circuit with triode separating Q304 RESET_N VCC_2P8/3P0/3P3 N75 module R317 R318 4.7kΩ 4.7kΩ VDD_1P8 Figure 3-12 shows the reset timing of N75. Figure 3-12 Reset timing of N75 VBAT RESET_N <0.6V Active Inactive All Interfaces Copyright © Neoway Technology Co., Ltd...

  • Page 33: Peripheral Interfaces

    USB_DP AIO USB data positive signal 90Ω impedance for differential traces. USB_ID USB ID Used for OTG function USB can be used to download firmware for N75 and establish data communication for commissioning. Copyright © Neoway Technology Co., Ltd...

  • Page 34: Figure 3-13 Usb Connection

    ⚫ lower than 1pF if possible. To enter sleep mode, shut down USB_VBUS. Add a switch to USB_VBUS to control it by MCU. ⚫ See Figure 3-14. For the switch circuit, see Figure 3-3. Copyright © Neoway Technology Co., Ltd...

  • Page 35: Usim

    USIM1 detect A pull-up resistor is recommended N75 provides one USIM1 interface by default. USIM2 interface is a multiplex function of Ethernet interface and compatible with 1.8V/2.85V USIM card. For details, see Section 3.7 MUX Interfaces. Figure 3-15 shows the reference design of the USIM card interface.

  • Page 36: Figure 3-15 Reference Design Of Usim Card Interface

    Connect a 20 Ω resistor respectively to USIM_DATA, USIM_RESET, USIM_CLK, and ⚫ USIM_DET in series to enhance the ESD performance. N75 supports USIM card detection. USIM_DET is a 1.8V interrupt pin. ⚫ The UIM detection circuit works by checking the levels across the USIM_DET pin before and after a UIM card is inserted.

  • Page 37: Uart

    UART5 data receiving Used for data transmission N75 provides one UART interface. To support hardware flow control, multiplex pin 51 and pin 52 as UART5_CTS and UART5_RTS. UART interfaces support 4 Mbps at most. The level at the interfaces 1.8V. To use multiple UART interfaces, see Section 3.7 MUX Interfaces. Figure 3-16 and Figure 3-17 show the reference designs of the UART interfaces.

  • Page 38: Figure 3-18 Recommended Level Shifting Circuit 1

    If the low level at MCU_UART (V ) is lower than 200mV, adopt recommended level shifting circuit 2. Otherwise, low level at UART might be higher than required, resulting in failure to identify signals. Copyright © Neoway Technology Co., Ltd...

  • Page 39: Figure 3-19 Recommended Level Shifting Circuit 2

    UART_RXD are respectively the TX and RX of the module. VCC_IO is the IO voltage of the MCU. Level shift chip is recommended if the level of MCU is larger than 3.3V or the baudrate is higher than 1 MHz. Copyright © Neoway Technology Co., Ltd...

  • Page 40: Sdc

    SDC clock output SDC_CMD SDC command SDC_DATA0 SDC data bit 0 SDC_DATA1 SDC data bit 1 SDC_DATA2 SDC data bit 2 SDC_DATA3 SDC data bit 3 SDC_DET SD card detect SDC_PWR_EN Control of SD external power Copyright © Neoway Technology Co., Ltd...

  • Page 41: Figure 3-21 Sd Connection

    VDD_SDC_IO is the power supply to which the DATA and AMD signals of SDC connect through ⚫ a pull-up resistor. The power source is determined by the IO level of SD chipset. If the IO level is Copyright © Neoway Technology Co., Ltd...

  • Page 42: Figure 3-22 Sdc Sdr Timing

    For the timing of the SDC interface in SDR and DDR mode, see Figure 3-22 and Figure 3-23. For parameter values for the SD interface, see Table 3-4. Figure 3-22 SDC SDR timing SDC_CLK t(csurd) t(chrd) t(dsurd) t(dhrd) Read t(pddwr) t(cdvrd) t(pdcwr) t(dvrd) Write Copyright © Neoway Technology Co., Ltd...

  • Page 43: I2S/Pcm

    Data set-up time t(pddwr) Delay time from data write to transmit t(pdcwr) Delay time from command write to transmit -8.2 3.3.6 I2S/PCM Signal Function Remarks I2S_MCLK I2S main clock 12.288 MHz by default Copyright © Neoway Technology Co., Ltd...

  • Page 44: Figure 3-24 I2S Connection

    N75 module Schematic Guidelines If the levels of N75 and CODEC do not match, add a level shift circuit as shown in 3.3.4. ⚫ Leave I2S_MCLK floating in your application if it is not required for the CODEC chipset selected.

  • Page 45: Figure 3-25 I2S Timing

    PCM interface supports primary mode and auxiliary mode. Table 3-6 PCM work modes Mode Synchronization Mode Work Mode Primary Mode Short sync Host mode or device mode Auxiliary Mode Long sync Host mode Figure 3-26 shows PCM connection. Copyright © Neoway Technology Co., Ltd...

  • Page 46: Figure 3-26 Pcm Connection

    The PCM interface supports only standard modes. Figure 3-27 PCM sync signal timing in primary mode t(sync) PCM_SYNC t(synca) t(syncd) Figure 3-28 PCM data input timing in primary mode t(clk) t(clkh) t(clkl) PCM_CLK t(sus t(hsync) ync) PCM_SYNC t(sudin) t(hdin) PCM_DIN Copyright © Neoway Technology Co., Ltd...

  • Page 47: Figure 3-29 Pcm Data Output Timing In Primary Mode

    Hold time from PCM_CLK low to PCM_DIN t(hdin) high Delay time from PCM_CLK high t(pdout) PCM_DOUT low Delay time from PCM_CLK t(zdout) PCM_DOUT high impedance Figure 3-30 PCM sync signal timing in auxiliary mode t(auxsync) PCM_SYNC t(auxsynca) t(auxsyncd) Copyright © Neoway Technology Co., Ltd...

  • Page 48: Figure 3-31 Pcm Data Input Timing In Auxiliary Mode

    62.4 62.5 t(auxsyncd) PCM_SYNC invalid time 62.4 62.5 t(auxclk) PCM_CLK cycle t(auxclkh) PCM_CLK high time t(auxclkl) PCM_CLK low time PCM_SYNC set-up time to PCM_CLK t(suauxsync) 1.95 rising t(hauxsync) PCM_SYNC hold time after PCM_CLK 1.95 Copyright © Neoway Technology Co., Ltd...

  • Page 49: Spi

    Note the SPI signal direction. ⚫ If the levels of slave SPI device and N75 do not match, add a level shifting circuit. Refer to ⚫ Figure 3-20 if the SPI speed does not exceed 20 MHz. Select other high-speed level shifting chipsets if the speed exceeds 20 MHz.

  • Page 50: I2C

    The I2C interface is open-drain driven and connected through an internal pull-up resistor. If you use other pins to multiplex I2C interface, reserve a place for the external pull-up resistor. It can be used in Copyright © Neoway Technology Co., Ltd...

  • Page 51: Figure 3-35 I2Cconnection

    I2C_SDA DATA Schematic Guidelines If the levels of slave I2C device and N75 do not match, add a level shifting circuit. Refer to ⚫ Figure 3-20. Some pins can be multiplexed for I2C function. Connect external pull-up resistors to these pins ⚫...

  • Page 52: Figure 3-36 I2C Data Transmission

    Hold time (repeated) START condition HD;STA LOW period of the SCL pin HIGH period of the SCL pin HIGH Set-up time for a repeated START SU;STA condition Data hold time HD;DAT Data set-up time SU;DAT Copyright © Neoway Technology Co., Ltd...

  • Page 53: Table 3-12 I2C Timing Parameters (Fast Mode)

    VD;DAT Data invalid acknowledge time VD;ACK Table 3-13 I2C timing parameters (fast mode plus) Minimum Typical Maximum Timing Parameter Unit Value Value Value SCL clock frequency 1000 Hold time (repeated) START condition 0.26 HD;STA Copyright © Neoway Technology Co., Ltd...

  • Page 54: Network And Connection

    SGMII receive plus Leave this pin floating if it is not used. SGMII interface is used for Ethernet connection. The SGMII interface provided by N75 Open Linux complies with ENG46158 Rev1.8. For its timing and electric parameters, see the definition in the standard.

  • Page 55: Figure 3-38 Sgmii Connection

    USIM2_VCC line to be pulled up to card SGMII_MDIO_CLK MDIO clock Add a 1.5kΩ resistor between SGMII_MDIO_DATA MDIO data IO this pin and UIM2_VCC. ETH_REST_N Ethernet PHY chipset reset ETH_INT_N Ethernet PHY chipset interrupt Copyright © Neoway Technology Co., Ltd...

  • Page 56: Figure 3-39 Connection Between Mdio And Phy

    1.8V/2.85V auto-adaption. Figure 3-40 and Figure 3-41 show MDIO input/output timing. Figure 3-40 MDIO input timing (MIN) MDIO_CLK (MAX) (MIN) MDIO_DATA (MAX) 10ns MIN 10ns MIN Figure 3-41 MDIO output timing (MIN) MDIO_CLK (MAX) (MIN) MDIO_DATA (MAX) 0ns MIN 300ns MAX Copyright © Neoway Technology Co., Ltd...

  • Page 57: Wlan

    Clock frequency: 32.768 KHz Table 3-14 SDIO/WLAN feature parameters Mode IO Level (V) Max Clock Frequency (MHz) Timing Mode DS, HS, SDR12, SDR25, SDR50, SDR104 DDR50 WLAN uses SDIO 3.0 interface. Figure 3-42 shows the WLAN connection. Copyright © Neoway Technology Co., Ltd...

  • Page 58: Figure 3-42 Wlan Connection

    Leave this pin floating if the WLAN chipset does not support this function. PCB Design Guidelines SDIO interface requires control of trace length. For details about the requirements, refer to the ⚫ WLAN chipset spec. Copyright © Neoway Technology Co., Ltd...

  • Page 59: Figure 3-43 Sdio Sdr Timing

    Data valid time Delay time from data write to t(pddwr) -1.45 0.85 transmit Delay time from command write to t(pdcwr) -1.45 0.85 transmit DDR mode (max. 50MHz) t(chrd) Command hold time t(csurd) Command set-up time 5.53 Copyright © Neoway Technology Co., Ltd...

  • Page 60: Bluetooth

    N75 communicates with Bluetooth chipset through UART for data transmission. To use Bluetooth audio, connect one set of PCM signals (pins 65 to 68). See section 3.7 MUX Interfaces. Figure 3-45 shows the Bluetooth connection.

  • Page 61: Rf Interface

    The Bluetooth audio function is implemented through a PCM interface. If the PCM interface is ⚫ used, leave I2S_MCLK floating. PCB Design Guidelines Refer to the PCB design guidelines of UART and PCM. ⚫ 3.5 RF Interface Signal Function Remarks 50Ω impedance ANT_MAIN AI/O 2G/3G/4G main antenna Copyright © Neoway Technology Co., Ltd...

  • Page 62: Ant_Main/Ant_Div Antenna Interface

    Diversity antenna 3.5.1 ANT_MAIN/ANT_DIV antenna interface MAIN_ANT and DIV_ANT of N75 require a characteristic impedance of 50 Ω. Developers should control the impedance of the traces between the pins and antenna to ensure the RF performance. An impedance matching circuit, such as L network, T network, or pi network is mandatory in between. Pi network is recommended.

  • Page 63: Figure 3-48 Pi Network

    Lay copper foil around RF connector. Dig as many ground holes as possible on the copper to ⚫ ensure lowest grounding impedance. The trace between N75 and the antenna connector, should be as short as possible. Control the ⚫ trace impedance to 50Ω.

  • Page 64: Ant_Gnss Interface

    Figure 3-49 Recommended RF PCB design 1 3.5.2 ANT_GNSS Interface GPS Impedance Control ANT_GNSS (92) is the GNSS RF interface of N75, which requires a characteristic impedance of 50Ω. Figure 3-50 shows the GNSS structure inside the module. Figure 3-50 GNSS RF structure...

  • Page 65: Figure 3-51 Reference Design Of Passive Gnss Antenna

    Reference design of active GNSS antenna After the antenna receives GNSS satellite signals, the LNA amplifies the signals first and then transmits them to the ANT_GNSS pin of N75 through feeder and PCB traces. See Figure 3-52. Copyright © Neoway Technology Co., Ltd...

  • Page 66: Figure 3-52 Reference Design Of Active Gnss Antenna

    Keep GNSS antenna circuit far away from the main/diversity antenna circuits on PCB. ⚫ Otherwise, these two parts will jam each other, lowing the RF performance. Figure 3-53 shows reference layout of GNSS antenna traces. This design is also applicable to Copyright © Neoway Technology Co., Ltd...

  • Page 67: Antenna Assembling

    Inverted F antenna (PIFA). Keep external RF wires far away from all disturbing sources, especially digital signals and DC/DC power if using RF wires. The following methods are commonly used to assemble antenna: GSC RF connector ⚫ MM9329-2700RA1 from Murata is recommended. Figure 3-54 shows its encapsulation specifications. Copyright © Neoway Technology Co., Ltd...

  • Page 68: Gpio

    GPIO with interrupt the module is started. N75 provides 4 GPIO pins, two among which support interrupt. Do not connect GPIO_78 or GPIO_79 to the power supply through a pull-up resistor before the module is started. Otherwise, the module will enter download mode forcibly once detecting high level or current input at this pin during startup.

  • Page 69: Mux Interfaces

    GPIO_31 USIM1_CLK GPIO_32 USIM1_RESET GPIO_33 USIM1_DET GPIO_34 Do not pull up these pins to high level before the module is started completely. otherwise, the module cannot start up successfully. GP_CLK indicates clock pulse signal. Copyright © Neoway Technology Co., Ltd...
  • Page 70 WAKE_ON_WIRELES GPIO_59 WLAN_EN GPIO_38 GPIO_79 GPIO_79 I2S_2_WS BT_PCM_SYNC GPIO_78 GPIO_78 I2S_2_SCLK BT_PCM_CLK GPIO_77 GPIO_77 I2S_2_D1 BT_PCM_DOUT Pull up this pin to high level before the module is started, and the module enter USB_BOOT mode. Copyright © Neoway Technology Co., Ltd...
  • Page 71 GPIO_54 SDC_DET GPIO_26 46 pins of N75 allow multiplexing and all of them can be used as GPIO. Please use their default functions if you do not have any special requirements in your application. Copyright © Neoway Technology Co., Ltd...

  • Page 72: Other Interfaces

    Once a voice call is incoming, the UART port outputs "RING" character strings and meanwhile the RING pin outputs negative pulse with a width of 30 ms and a period of 5 seconds. Figure 3-56 Pulse wave for an incoming call 30 ms 30 ms Copyright © Neoway Technology Co., Ltd...

  • Page 73: Dtr

    2: Allow to enter sleep mode Enter sleep mode at high level Exits from sleep mode at low level Pull SLEEP low Whether the module Processing current is in idle state services Enter sleep mode and disable all interfaces Copyright © Neoway Technology Co., Ltd...

  • Page 74: Figure 3-59 Incoming Call Service Process

    MCU pulls SLEEP pin MCU pulls SLEEP pin to Figure 3-61 Process of exiting from sleep mode Sleep mode MCU pulls DTR high UART enabled AT+ENPWRSAVE=0 Forbid sleep mode Exits from sleep mode Copyright © Neoway Technology Co., Ltd...

  • Page 75: Usb_Boot

    Reserve this pin to facilitate software upgrade and debugging. Figure 3-62 shows the reference design of this pin. Figure 3-62 Reference design of USB_BOOT DVDD_1P8 USB_BOOT 10kΩ 10kΩ ESD1 ESD2 Add an ESD component to protect USB_BOOT in circuit. Copyright © Neoway Technology Co., Ltd...

  • Page 76: Electric Feature And Reliability

    Hardware User Guide 4 Electric Feature and Reliability This chapter describes the electric features and reliability of N75, including current and voltage of each power pin, operating and storage temperature ranges, and ESD protection features. 4.1 Electric Features Table 4-1 Electric features...
  • Page 77 LTE-TDD Band25@ Max Tx power LTE-TDD Band26@ Max Tx power LTE-TDD Band66@ Max Tx power LTE-TDD Band71@ Max Tx power μA Power OFF Sleep Mode Active Mode μA Power OFF Sleep Mode Active Mode Copyright © Neoway Technology Co., Ltd...

  • Page 78: Temperature Features

    If the module works in an environment of -35°C to -40°C or 75°C to 85°C, RF performance might be worse. This does not affect the running of the module. The RF performance will meet the 3GPP standard after the temperature reaches the operating range. Copyright © Neoway Technology Co., Ltd...

  • Page 79: Esd Protection

    Table 4-4 ESD protection features Testing Point Contact Discharge Air Discharge VBAT ± 8kV ± 15kV ± 8kV ± 15kV ± 8kV ± 15kV Cover ± 8kV ± 15kV Others ± 2kV ± 4kV Copyright © Neoway Technology Co., Ltd...

  • Page 80: Rf Features

    Hardware User Guide 5 RF Features N75 supports 2G/3G/4G network modes and frequency bands as well as GNSS function. This chapter describes the RF features of N75. 5.1 Operating Bands Table 5-1 Operating Bands Operating Bands Uplink Downlink GSM850 824~849MHz...

  • Page 81: Tx Power And Rx Sensitivity

    UMTS B8 24dBm +1/-3dBm <-110dBm UMTS B19 24dBm +1/-3dBm <-110dBm FDD-LTE B1 23dBm+2/-2dBm <-98dBm FDD-LTE B2 23dBm+2/-2dBm <-98dBm FDD-LTE B3 23dBm+2/-2dBm <-96dBm FDD-LTE B4 23dBm+2/-2dBm <-98dBm FDD-LTE B5 23dBm+2/-2dBm <-98dBm FDD-LTE B7 23dBm+2/-2dBm <-96dBm Copyright © Neoway Technology Co., Ltd...

  • Page 82: Gnss Feature

    Acquisition sensitivity -144 dBm (GPS)/-143.5 dBm (GLONASS) Positioning precision (in air) < 3 m (CEP50) Hot start (in air) <2.5s Cold start (in air) <35s Update frequency 1Hz by default CNRin/CNRout Max. positioning altitude 18000m Copyright © Neoway Technology Co., Ltd...
  • Page 83 Tracking sensitivity, acquisition sensitivity, and re-acquisition sensitivity were obtained in signaling test on SPIRENT6300 and they are the maximum values of multiple tests on samples. No external LNA or active antenna was used in the test. Copyright © Neoway Technology Co., Ltd...

  • Page 84: Mechanical Features

    Hardware User Guide 6 Mechanical Features This chapter describes the mechanical features of N75. 6.1 Dimensions Figure 6-1 N75 dimensions The unit is mm. Copyright © Neoway Technology Co., Ltd...

  • Page 85: Label

    ⚫ 6.3 Pack N75 modules are packaged in sealed vacuum bags with dryer, humidity card, and tray on delivery to guarantee a long shelf life. Follow the same package method again in case of opened for any reasons. 6.3.1 Reel&Tape N75 in mass production are shipped in the following package.
  • Page 86 Hardware User Guide N75 module Tape Copyright © Neoway Technology Co., Ltd...

  • Page 87: Moisture

    Hardware User Guide Reel 6.3.2 Moisture N75 is a level 3 moisture-sensitive electronic elements, in compliance with IPC/JEDEC J-STD-020 standard. If the module is exposed to air for more than 48 hours at conditions not worse than 30°C/60% RH, bake it at a temperature higher than 90 degree for more than 12 hours before SMT.Or, if the indication card shows humidity greater than 20%, the baking procedure is also required.Do not bake modules...

  • Page 88: Mounting The Module Onto The Application Board

    7 Mounting the Module onto the Application Board N75 is introduced in 100-pin LGA package. This chapter describes N75V5 foot print, recommended PCB design and SMT information to guide users how to mount the module onto application PCB board. 7.1 Bottom Dimensions Figure 7-1 Bottom view Copyright ©...

  • Page 89: Application Foot Print

    It is easy to cause voiding for LGA and LCC inside the module after second reflow soldering. When using only solder pastes with lead, please ensure that the reflow temperature is kept at ⚫ 220 °C for more than 45 seconds and the peak temperature reaches 240 °C. Copyright © Neoway Technology Co., Ltd...

  • Page 90: Smt Furnace Temperature Curve

    Neoway will not provide warranty for heat-responsive element abnormalities caused by improper temperature control. For information about cautions in N75 storage and mounting, refer to Neoway Module Reflow Manufacturing Recommendations. When manually desoldering the module, use heat guns with great opening, adjust the temperature to 250 degrees (depending on the type of the solder paste), and heat the module till the solder paste is melt.

  • Page 91: Safety Recommendations

    ⚫ other electronic equipment. Please follow the requirements below in application design: Do not disassemble the module without permission from Neoway. Otherwise, we are entitled to ⚫ refuse to provide further warranty. Please design your application correctly by referring to the HW design guide document and our ⚫...

  • Page 92: Conformity And Compliance

    A.2.3 FCC Class B Digital Device Notice This equipment has been tested and found to comply with the limits for a Class B digital device, Copyright © Neoway Technology Co., Ltd...
  • Page 93 Increase the separation between the equipment and receiver. ⚫ Connect the equipment into an outlet on a circuit different from that to which the receiver is ⚫ connected. Consult the dealer or an experienced radio/TV technician for help. ⚫ Copyright © Neoway Technology Co., Ltd...

  • Page 94: Abbreviation

    Long-Term Evolution MDIO Management Data Input/Output Printed Circuit Board Pulse-Coded Modulation Power management unit Radio Frequency Secure Digital Controller SGMII Serial Gigabit Media Independent Interface Serial Peripheral Interface TD-SCDMA Time Division-Synchronous Code Division Multiple Access Copyright © Neoway Technology Co., Ltd...
  • Page 95 Universal asynchronous receiver-transmitter USIM Universal Subscriber Identity Module UMTS Universal Mobile Telecommunications System Universal Serial Bus USB-OTG Universal serial bus on-the-go WCDMA Wide-band Code Division Multiple Access Wireless Coexistence Interface WLAN Wireless Local Area Network Copyright © Neoway Technology Co., Ltd...

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