NXP Semiconductors Digital DNA MSC8102 User Manual And Hardware Detailed Design Description
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NXP Semiconductors Digital DNA MSC8102 User Manual And Hardware Detailed Design Description

NXP Semiconductors Digital DNA MSC8102 User Manual And Hardware Detailed Design Description

Packet telephony farm card (pfc)
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MSC8102 - Packet Telephony Farm Card (PFC)
User Guide and Hardware Detailed Design
Author:
Colin McEwan
Email:
colin.mcewan@motorola.com
Phone:
+44 1355 356061
Networking and Computing Systems Group (NCSG)
Colvilles Road, Kelvin Industrial Estate, East Kilbride, Glasgow G75 OTG. 44 (0) 1355 355000. Fax:
44 (0) 1355 260780
Reg. Office: Motorola Ltd., Jays Close, Viables Industrial Estate, Basingstoke, Hants., RG22 4PD
(registration No. 912182 England)
Description
PFC_DDD_v1.3.doc
Mark Knox
mark.knox@motorola.com
+44 1355 356034
MSC8102PFCUG/D
Rev. 1.3

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  • Page 1 MSC8102PFCUG/D Rev. 1.3 MSC8102 - Packet Telephony Farm Card (PFC) User Guide and Hardware Detailed Design Description PFC_DDD_v1.3.doc Author: Colin McEwan Mark Knox Email: colin.mcewan@motorola.com mark.knox@motorola.com Phone: +44 1355 356061 +44 1355 356034 Networking and Computing Systems Group (NCSG) Colvilles Road, Kelvin Industrial Estate, East Kilbride, Glasgow G75 OTG. 44 (0) 1355 355000. Fax: 44 (0) 1355 260780 Reg.
  • Page 2 Revision History Revision Date Description of Change 24/1/3 First Issue 7/3/3 Updated to reflect Pilot Production Boards 27/3/3 MSC8102 SDRAM increased to 16MB 21/4/3 Pilot Production Release (with quick start guide) PFC_DDD_v1.3.doc...

  • Page 3: Table Of Contents

    CONTENTS OVERVIEW..................................1 ....................................1 COPE ..............................1 EFERENCE OCUMENTS PFC OVERVIEW ................................2 PFC FEATURE LIST............................... 3 USER GUIDE..................................4 .................................. 4 UICK TART ..........................5 OARD ONFIGURATION PTIONS 4.2.1 Single MSC8101 with Default Configuration ......................5 4.2.2 MSC8101 Boot through HDI16..........................6 4.2.3 MSC8101 Ethernet/Utopia Options.........................
  • Page 4 APPENDIX B PFC BASE CARD PARTS..........................43 APPENDIX C JTAG CONFIGURATION FILE (21 CORES)..................... 44 APPENDIX D PFC LAYOUT ..............................45 FIGURES 1. MSC8102 - P ......................2 IGURE ACKET ELEPHONY 2. PFC S ..................................4 IGURE ETUP 3. P ......................
  • Page 5 36. CT B ..................................39 ABLE 37. E ..............................40 ABLE THERNET NTERFACE 38. M ............................40 ABLE ISCELLANEOUS IGNALS PFC_DDD_v1.3.doc...

  • Page 6: Overview

    1 Overview 1.1 Scope This document provides user guide information and a detailed design description of the MSC8102 Packet Telephony Farm Card. 1.2 Reference Documents The documents listed in the table below are referenced in this document. Table 1. Reference Documents Reference Document Description...

  • Page 7: Pfc Overview

    2 PFC Overview The Packet Telephony Farm Card is a PCI Telephony Mezzanine Card (PTMC) designed primarily as an MSC8102 upgrade and Media Gateway evaluation product for Media Gateway Systems. It is designed around the Star-Core MSC8102 16 bit fixed point DSP device from Motorola Semiconductor. The PFC DSP farm card utilizes five MSC8102 devices and a MSC8101 to aggregate the data to/from the DSP farm.

  • Page 8: Pfc Feature List

    3 PFC Feature List PFC Platform Digital Support for up to 672 channels PTMC Type 3 form card for interfacing to standard subsystems MSC8101 Aggregator One MSC8101 DSP communications processor with: 10/100BaseT Fast Ethernet via PTMC Interface RMII Ethernet via PTMC Interface UTOPIA interface via PTMC Interface Host Interface to enable Host control of Aggregator via PTMC Interface 64-bit/32-bit PPC interface to the MSC8102 DSI port for on board data...

  • Page 9: User Guide

    4 User Guide 4.1 Quick Start Start the Start the Codewarrior tools and ensure that the command converter is running Connect a dual supply to the 5V, 3.3V and 0V on the JP1 connector of the Base Card. The parallel command converter should also be connected to P3 on the PFC to enable JTAG access, reference Figure 2.

  • Page 10: Board Configuration Options

    The JTAG file “PFCjtag21.cfg” is selected. The file listing and core JTAG numbering is detailed in Appendix C. Table 2. MSC8101 Boot from Flash Feature Settings Comments SW3.1 A_MODCK1 = 1 MODCK 46 [101-110]. A_MODCK2= 1 CLKIN=34.5MHz SW3.2 A_MODCK3= 0 Core/CPM/Bus= 275/138/69 MHz SW3.3 SW3.4...

  • Page 11: Msc8101 Boot Through Hdi16

    SW3.4 Boot=0, Host Port disabled, Boot from external memory SW3.8 RSTCONF=1, Reset Configuration Slave 4.2.2 MSC8101 Boot through HDI16 To bootstrap the PFC through the MSC8101 HDI16 interface, set the switch settings detailed in Table 6 and Table 3. Table 6. MSC8101 HDI16 Boot Feature Settings Comments...

  • Page 12: Programming Flash

    SW2.8 Full Chain (21 cores) Pos 1-2 SW2.8 The JTAG configuration file for 21 cores is listed in Appendix C. 4.3 Programming Flash The PFC uses the same Flash (AM29LV320DB) as the MSC8102ADS so the option exists to use either the Metrowerks Code-warrior or PFC specific Flash Programmer (consult Motorola for additional details on programming Flash).

  • Page 13: Hardware Description

    5 Hardware Description This section describes the Packet Telephony Farm Card Hardware. The Hardware architecture has been partitioned into the following logical sections: Aggregator, DSP Processing Array, General Board Configuration, Firmware and PFC Base Card. 5.1 Board Architecture The board architecture of the Packet Telephony Farm Card is shown in Figure 3. CT Bus CT Bus 32-bit...

  • Page 14: Msc8101 Sdram Interface

    Table 9. MSC8101 Memory Controller Resources Chip Select Peripheral Flash (Boot) SDRAM DSI Asynchronous (Individual Chip Selects) DSI Asynchronous (Broadcast mode) 5.2.1 MSC8101 SDRAM Interface The Aggregator 60x bus incorporates 64M-bit x32-bit wide x4 bank Micron MT48LC2M32B2 SDRAM surface mounted onto the board providing 8 MBytes of general-purpose system RAM. The MSC8101’s Chip Select 2 is used to select the SDRAM devices through the SDRAM controller, which is capable of interfacing to JEDEC compatible SDRAM, the settings of which are now described.

  • Page 15: Sdram Initialization Command Sequence

    OP = 000 Normal Operation SDAM = 010 A[9:19] multiplexed to A[19:29] BSMA = 100 A17-A18 are used as Bank Selects Signals SDA10 = 001 A9 maps to A10/AP pin RFRC = 110 8 Clock Cycles Refresh Recovery PRETOACT = 011 Pre-charge to Activate 3 cycle interval ACTTORW= 011 Activate to Read/Write 3 clock cycles...

  • Page 16: Sdram Refresh

    Step 3. Issue Precharge All command (PALL) to all banks of the device. Program PSDMR[OP] bits to [101] and then perform an access to the SDRAM bank. Step 4. Issue 8 or more CBR Refresh (REF) commands. Program PSDMR[OP] bits to [001] and then perform 8 accesses to the SDRAM bank.

  • Page 17: Msc8101 60X To Dsi Interface

    A_BADDR[31] On the flash the BYTE signal is pulled down for byte mode which enables DQ[0:7] but tri-states DQ[8:14], with DDQ15/A-1 used as an input for the LSB address bit, A_BADDR31. The memory controller uses the BADDR[27-31] signals to interface to the memories when operating in multi- master mode.

  • Page 18: Msc8101 60X To Dsi Interface: Asynchronous Mode

    Dh[0:63] Dh[0:63] GRP_Ds[0:63] GRP_Ds[0:63] HD[0:63] HD[0:63] Ah[0:31] Ah[0:31] GRP_Ah[7:29] GRP_Ah[7:29] GRP_Ah[11:29] GRP_Ah[11:29] HA[11:29] HA[11:29] GRP_Ah[7:10] GRP_Ah[7:10] FPGA A_TSIZ[0:3] A_TSIZ[0:3] HCID[0:3] HCID[0:3] A_PUPMWAIT A_PUPMWAIT Xilinix XC2S300E - 7F - G456C Xilinix XC2S300E - 7F - G456C A_TS A_TS HBRST HBRST MSC8101 MSC8101 A_TBST A_TBST...

  • Page 19: Figure 7. Aggregator Msc8102 Interrupt Connectivity Options

    IRQ1_D1 IRQ2_D1 MSC8102 GPIO30_D1 FPGA INT_OUT_D1 IRQ1_D2 IRQ2_D2 MSC8102 GPIO30_D2 INT_OUT_D2 MSC 8101 A_IRQ[1:7] IRQ1_D3 IRQ2_D3 MSC8102 DSP_IRQ_GPIO[1:5] GPIO30_D3 INT_OUT_D3 IRQ1_D4 IRQ2_D4 MSC8102 GPIO30_D4 INT_OUT_D4 IRQ1_D5 IRQ2_D5 MSC8102 GPIO30_D5 INT_OUT_D5 Figure 7. Aggregator MSC8102 Interrupt Connectivity Options FPGA MSC8102 INT_OUT_D1 GPIO30_D1 MSC8102 8101...

  • Page 20: Msc8101 Fcc Interface

    5.2.5 MSC8101 FCC Interface The MSC8101 incorporates two FCC interfaces for packet transfers. The packet interfaces are configurable to perform 2xMII ports (FCC1 & FCC2) or an MII (FCC1) plus a UTOPIA (FCC2) port. Both configurations are routed out to the PTMC connector as detailed in Table 15. Signals that are common between UTOPIA FCC1 and MII FCC1 are routed to their connector positions via a PERICOM P13B16233 bus switch.

  • Page 21: Rmii Interface

    PD16 FCC1 Utopia II TXPRTY Pn4-31 PD17 FCC1 Utopia II RXPRTY Pn4-36 PD18 FCC1 Utopia II RXADDR4 Pn4-4 PD19 FCC1 Utopia II TXADDR4 Pn4-6 PD29 FCC1 Utopia II RXADDR3 Pn4-7 Table 16. MSC8101 Aggregator FCC2 PTMC Connectivity Function Signal Connects to PB18 FCC2 MII2 RXD3...

  • Page 22: Msc8102 Dsp Processing Array

    Table 17. HDI6 Configuration 60x signal HDI16 Signal Description Dh57 HDSP=0 Single data strobe mode Dh58 HDDS=0 Negative data strobe polarity Dh59 H8BIT=0 16-bit mode enabled Dh60 HCS2=1 Not used, pulled high Note that when using the host port the DSI interface must be configured for 32-bits 5.3 MSC8102 DSP Processing Array The DSP farm contains 5 MSC8102 DSPs connected to the MSC8101 via a shared DSI 60x bus interface.

  • Page 23: Able 17. Psdmr Settings

    Table 18. MSC8102 PSDMR settings Register Setting Description PBI = 1 Paged Based Interleaving RFEN = 1 Refresh services required OP = 000 Normal Operation SDAM = 010 A[9:19] muxed to A[19:29] BSMA = 011 A16-A17 are used as Bank Selects Signals SDA10 = 001 A9 maps to A10/AP pin RFRC = 110...

  • Page 24: Sdram Initialization Command Sequence

    5.3.1.1 SDRAM Initialization Command Sequence Step 1. Apply power and start clock. Maintain No Operation (NOP) condition at the inputs. Step 2. Maintain stable power, stable clock and NOP input conditions at the inputs. Step 3. Issue Precharge All command (PALL) to all banks of the device. Program PSDMR[OP] bits to [101] and then perform an access to the SDRAM bank.

  • Page 25: Tdm To Ct Routing

    TDM. With the P3TMC specification implemented the number of CT lines is further restricted to 20 streams. Each MSC8102 has four TDM interfaces. The TDM Streams are routed as follows: MSC8102 CT_C8_A_B TDM0TCLK TDM0TDAT CT_D0 CT_C8_ TDM0TSYN TDM0RDAT CT_D1 CT_FRAME_A_B TDM1TCLK TDM1TDAT CT_D2...

  • Page 26: Msc8102 Rs232 Interface

    TDM2 TDM2TDAT CT_D12 TDM2RDAT CT_D13 TDM3 TDM3TDAT CT_D18 TDM3RDAT CT_D19 MSC8102 #4 TDM0 TDM0TDAT CT_D14 TDM0RDAT CT_D15 TDM1 TDM1TDAT CT_D10 TDM1RDAT CT_D11 TDM2 TDM2TDAT CT_D16 TDM2RDAT CT_D17 TDM3 TDM3TDAT CT_D8 TDM3RDAT CT_D9 MSC8102 #5 TDM0 TDM0TDAT CT_D14 TDM0RDAT CT_D15 TDM1 TDM1TDAT CT_D10 TDM1RDAT...

  • Page 27: Clock Distribution

    FLASH MSC8102 MSC8101 MSC8102 A_PORESET MSC8102 A_PORESET_M1 GPIO[PA7] MSC8102 PORESET_M1 Reset In RESET MSC8102 PORESET_FPGA FPGA Figure 12. PORESET Scheme The MSC8101 controls the generation of individually buffered HRESET signals to the MSC8102s through the AND gating of its own HRESET signal and its HRESET GPIO control line PD31. Note that for flexibility the MSC8102 HRESETS have been routed to the FPGA via 0ohm resistors.

  • Page 28: Msc8101 Aggregator Clocking Scheme

    The frequency of operation will depend on the revision of silicon used and the required application. Consult Motorola Ltd for the latest operating frequency characteristics of the MSC8101 and MSC8102. Note that to ensure synchronous operation the following layout constraints are placed: •...

  • Page 29: Power

    5.4.3 Power The PICMG 2.15 standard currently stipulates that 5V, 3.3V and GND are provided through the PTMC connectors. The optional connector, Pn5/Jn5 has the capabilities to supply the core voltage, 1.6V to the card. In this configuration, there is no need for additional regulation on the card. However, in order to interface with standard PTMC cards Pn5/Jn5 may not be populated –...
  • Page 30 Color M eaning Not Connected Ground Voltage CT (TDM) Bus Host Interface Signals General Data I/O SIGN AL SIGN AL GM II_CK CP14_D0 CP13_D6 CP14_D1 CP13_D5 CP14_D2 CP13_D4 CP13_D3 CP14_D3 CP13_D2 CP14_D4 CP13_D1 CP14_D5 CP13_D0 CP14_D6 CP12_D6 CP15_D0 CP12_D5 CP15_D1 CP12_D4 CP15_D2 CP12_D3...
  • Page 31 SIGN AL SIGN AL HA 1 +3.3V PTM C_RESET HA 2 +3.3V HA 3 +3.3V HTREQ +3.3V HRREQ A _IRQ7 +3.3V +3.3V HD10 HD11 HD12 +3.3V HD13 +3.3V HD14 HD15 HA 0 +3.3V Table 24. Pn2/Jn2 Connector Pin Out (Host Port Interface) PFC_DDD_v1.3.doc...

  • Page 32: Msc8102 Clock Frequencies Table 22. P N 1/J N 1 Connector Pin Out (Cport Interface Table 23. P N 2/J N 2 Connector Pin Out (Host Port Interface Table 24. P N 3/J N 3 Connector Pin Out (Ct Bus & Rmii)

    SIGNAL SIGNAL M II_M DIO M II_M DC RM II_RX_ER0 RM II_TXD0 RM II_TXD1 REF_CLK RM II_RXD0 CT_FRA M E_A RM II_RXD1 RM II_TXEN0 RM II_CRS_DV0 CT_C8_A CT_D19 CT_D18 CT_D17 CT_D16 CT_D14 CT_D12 PTENB CT_D15 CT_D10 CT_D13 CT_D8 CT_D11 CT_D9 CT_D6 CT_D7 CT_D4...

  • Page 33: Table 25. P N 4/J N 4 Connector Pin Out (Utopia)

    SIGN AL SIGN AL TxSOC RXA DR4 TxCLA V TXA DR4 RXA DR3 I2C_SCL RXENB# TXA DR3 RXCLA V TXA DR2 TXENB# RXA DR2 TXCLK TXA DR1 TXA DR0 RXA DR1 TXPRTY RXA DR0 TXD7 RXPRTY TXD6 RXD7 RXD6 RXCLK RXD5 TXD5 RXD4...

  • Page 34: Jtag Connectivity

    SIGN AL SIGN AL M II2_TCLK M II2_TXD0 M II2_TXD1 M II2_RXDV M II2_TXD2 M II2_RXD0 M II2_TXD3 M II2_RXD1 M II2_RXD2 M II2_TXEN M II2_RXD3 M II2_TXER M II2_RXER M II2_COL M II2_CRS M II2_RCLK M II1_TXD0 VCC_CORE M II1_TXD1 M II1_RXDV M II1_TXD2 M II1_RXD0...

  • Page 35: Leds

    • TDI: The input signal is pulled high to save power in low power stop mode. All JTAG ports have a weak internal TDI pull up. • TDO: The output signal is pulled high MSC8101 MSC8101 MSC8101 MSC8102(1) MSC8102(1) MSC8102(1) MSC8102(2) MSC8102(2) MSC8102(2)
  • Page 36 SW2.4 Select DSI bus width (DSI64) ON = 32-bit OFF = 64-bit SW2.5 Select DSI Mode of Operation (DSISYNC) ON = Asynchronous mode OFF = Synchronous mode SW2.6 Software Watchdog timer enable (SWTE) ON = Software WDT disabled OFF =Software WDT enabled SW2.7 Reset Configuration SW2.1 SW2.7...

  • Page 37: Firmware Implementation

    6 Firmware Implementation This section describes the firmware implementation on the PFC board, which includes detailed memory maps and register settings and details on how the board is bootstrapped. 6.1 MSC8101 Host Memory Controller Settings The PFC MSC8101 host DSP uses 6 of the available chip selects as memory resources. Four of these are used for peripherals (Flash, SDRAM, DSI, DSI Broadcast) and 2 are used for internal resources (SRAM and Local Peripherals), which creates a memory map, illustrated in Table 30.

  • Page 38: Msc8102 Memory Controller Settings

    EFCOP I/O FIFOS 0x221E_FFFF [64KB] 0x221E_0000 System Registers 0x221D_FFFF [128KB] 0x221C_0000 0xFE3F_FFFF FLASH IP Address Space 0x221B_FFFF [256KB] 0xFE00_0000 0x2218_0000 M1 Core 3 0xF001_FFFF 0x2217_7FFF IMMR [224KB] 0x2214_0000 0xF000_0000 M1 Core 2 0x2213_7FFF DSI [Broadcast] [224KB] 0x22A0_0000 0x2210_0000 DSI [DSP #5] 0x2280_0000 M1 Core 1 0x220B_7FFF...

  • Page 39: Pfc Reset Configuration Word (Msc8101)

    0x20FF_FFFF SDRAM 0x2000_0000 0xF000_FFFF IMMR 0xF000_0000 0x021E_FFFF DSP Peripherals [64KB] 0x021E_0000 0x021B_FFFF IP Peripherals [256KB] 0x0218_0000 0x0217_FFFF Internal SRAM [1.5 MB] 0x0200_0000 Figure 19. MSC8102 Memory Map 6.3 PFC Reset Configuration Word (MSC8101) When the MSC8101 is configured to boot from external memory it will access the start of Flash at address 0xFE000000 (using CS0) to read the Reset Configuration Word.

  • Page 40: Pfc Reset Configuration Word (Msc8102)

    6.4 PFC Reset Configuration Word (MSC8102) The slave MSC8102s are configured to receive their reset configuration word through the DSI port Table 33. MSC8102 Hard Reset Configuration Word Name Description EARB Internal Arbitration EXMC Internal Memory Controller INT OUT INT_OUT selected Single MSC8102 Bus Mode Boot Port size is 64 bits (not used) SCDIS...

  • Page 41: Pfc Bootstrap Method

    POReset = OFF MSC8102 MSC8101 HReset =ON Execute HReset HReset Bootstrap code = OFF = OFF IMMR=0xF000_0000 EARB=0,EBM=1 MSC8101 reads RCW Initialise MSC8101 From flash MSC8102 MSC8101 ROM BOOT ROM BOOT BOOT BOOT Write RCW to G ET ISB [000] Delay to allow GET ISB [000] MSC8102 over DSI...

  • Page 42: Pfc Base Card

    7 PFC Base Card To facilitate debug and customer demonstrations the PFC base card is designed to break out a number of interfaces from the PFC: • The UTOPIA, Ethernet (MII2) and the Host port interfaces are routed to the VME connectors for interfacing to the MSC8101 ADS UTOPIA PHY, Ethernet PHY and the 60x bus (Host Port) •...

  • Page 43: I2C Interface

    UTOPIA_TXD6 Pn4 37 ATMTXD6 P2 B13 UTOPIA_TXD7 Pn4 35 ATMTXD7 P2 B14 UTOPIA_RXD0 Pn4 60 ATMRXD0 P2 B15 UTOPIA_RXD1 Pn4 58 ATMRXD1 P2 B16 UTOPIA_RXD2 Pn4 54 ATMRXD2 P2 B17 UTOPIA_RXD3 Pn4 52 ATMRXD3 P2 B18 UTOPIA_RXD4 Pn4 48 ATMRXD4 P2 B19 UTOPIA_RXD5 Pn4 46...

  • Page 44: Ct Bus Interface

    Pn2 19 P2 C18 Pn2 23 P2 C19 Pn2 25 P2 C20 Pn2 29 P2 C21 Pn2 31 P2 C22 Pn2 35 P2 C23 Pn2 39 P2 C24 HD10 Pn2 43 HD10 P2 C25 HD11 Pn2 45 HD11 P2 C26 HD12 Pn2 49 HD12...
  • Page 45 Table 38. Ethernet Interface MSC8101 ADS Signal Connector Signal P2/J2 Connector UTOPIA_MTXADDR1 Pn3 1 FETHMDC P2 D19 (MII_MDC) UTOPIA_MRXADDR1 Pn3 5 FETHMDIO P2 D20 (MII_MDIO MII2_RCLK Pn5 40 FETHRXCK P2 D3 MI2_TCLK Pn5 20 FETHTXCK P2 D4 MII2_RXDV Pn5 24 FETHRXDV P2 C2 MI2_RXER...

  • Page 46: Appendix A Pfc Parts

    Appendix A PFC Parts. Board Ref. Description Manufacturer Part Number D1,D2,D3,D4,D5,D6,D10 0603 SM YELLOW LED LiteON LTST-C190YKT D7,D8,D9 1A Silicon Rectifier General Semi GF1A HDR 1X3 SMT 100mil SP 380H Au SAMTEC TSM-103-01-S-SV Surface Mount 3x2 0.1" pitch header SAMTEC TSM-103-01-S-DV 1mm dia.
  • Page 47 EEPROM FLASH 2MX16/4MX8 TSSOP AM29LV320DB120EI 48PIN IC DSP 332PIN BGA MOTOROLA MSC8101 IC FPGA 1.8V Spartan-IIE Xilinix XC2S300E-7FG456C 2K2 variable res Bourns 3214W-1-222E PFC_DDD_v1.3.doc...

  • Page 48: Appendix B Pfc Base Card Parts

    Appendix B PFC Base Card Parts. Board Ref. Description Manufacturer Part Number D1,D2,D3 1A Silicon Rectifier GENERAL SEMI GF1A 3 way Low Profile PCB Screw terminal 20.501/3SB (5mm pitch) 2 way Low Profile PCB Screw terminal 20.501/2SB (5mm pitch) Right Angle Male Connector (128pin type J1,J2 ERNI 023816...

  • Page 49: Appendix C Jtag Configuration File (21 Cores)

    Appendix C JTAG configuration file (21 cores) MSC8102Sync MSC8102 # DSP5 Core 0 MSC8102 # DSP5 Core 1 MSC8102 # DSP5 Core 2 MSC8102 # DSP5 Core 3 MSC8102Sync MSC8102 # DSP4 Core 0 MSC8102 # DSP4 Core 1 MSC8102 # DSP4 Core 2 MSC8102 # DSP4 Core 3...

  • Page 50: Appendix D Pfc Layout

    Appendix D PFC Layout Figure 22. PFC Layout - Top Figure 23. PFC Layout - Bottom PFC_DDD_v1.3.doc...
  • Page 51 MSC8102PFCUG/D Rev. 1.3 PFC_DDD_v1.3.doc...

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