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NXP Semiconductors PN544 C2 User Manual

NXP Semiconductors PN544 C2 User Manual

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UM191812
PN544 C2 User Manual
Rev. 1.2 — 2010-06-16
Document information
Info
Content
Keywords
PN544 C2, Logical Link Control Protocol, Host controller interface, Single
Wire Protocol, NFC 2
the Field
Abstract
This is a user manual for the PN544 C2 NFC IC.
The aim of the document is to describe the PN544 Firmware API enabling
you to design your NFC system.
nd
generation, SIM centered solution, Powered by
User Manual

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Summary of Contents for NXP Semiconductors PN544 C2

  • Page 1 Wire Protocol, NFC 2 generation, SIM centered solution, Powered by the Field Abstract This is a user manual for the PN544 C2 NFC IC. The aim of the document is to describe the PN544 Firmware API enabling you to design your NFC system.
  • Page 2 UM191812 NXP Semiconductors PN544 C2 User Manual Revision history Date Description 2010-04-28 Release for PN544 C2 2010-05-07 Add register: TX_Current_Check, 0x9F14 change default value, NXP_EVT_NFC_DEACTIVATED description update, Add NAD usage NfcT (0x98A3), 0x997A, 0x9F19 default value update, registers 0x998 and 0x9931 removed (trimmed value –...

  • Page 3: Introduction

    For further information please refer to the PN544 data sheet [7]. 2. PN544 C2 This document is related to the PN544 C2, it gives an overview of the Software API available. Please refer to the ‘PN544 Release Note’ [10] for further information on PN544 samples functionality level.

  • Page 4: Abbreviations

    UM191812 NXP Semiconductors PN544 C2 User Manual 3. Abbreviations Table 1. Abbreviations Abbr. Abbreviation Application Program Interface Contact less front-end Contact less Tunnel Cyclic Redundancy Check (according to SWP specification) Control Line on RS232: Data Set Ready Control Line on RS232: Data Terminal Ready...
  • Page 5 UM191812 NXP Semiconductors PN544 C2 User Manual Abbr. Abbreviation Random Access Module (volatile memory) Register Reject (HDLC) Radio Frequency (here 13,56MHz) Reserved for future use Control Line on RS232: Ring Indicator Receiver Not Ready (HDLC) Read only Receiver Ready (HDLC)

  • Page 6: References

    PN544 C2 Datasheet – Doc Number 1878xx Application Note “PN544 Software update” – 1581xx PN544 Custom Clock settings (Excel Worksheet Formula) – Doc Number 1610xx [10] PN544 C2 Release Note – Doc Number 1882xx [11] PN544 RF Configuration – Doc Number 1659xx 191812 All information provided in this document is subject to legal disclaimers.

  • Page 7: Pn544 Software Architecture

    UM191812 NXP Semiconductors PN544 C2 User Manual 5. PN544 Software Architecture 5.1 System Overview UICC interface Secure chip Interface ETSI Wired interface to ETSI connect Secure Element PN544 RF Protocols Host Interface (1) A high level view on the PN544 interface / software structure Fig 1.

  • Page 8: Host Hardware Interface Configuration

    UM191812 NXP Semiconductors PN544 C2 User Manual From software point of view we refer to “PN544 HCI”. Depending on the interface used the ETSI or the NXP proprietary one is used. For ease of nomenclature we refer to HCI meaning NXP PN544 HCI.
  • Page 9 UM191812 NXP Semiconductors PN544 C2 User Manual CPOL and CPHA are part of SPI Configuration. For more information about these 2 parameters, please refer to following table: Table 3. CPOL / CPHA description Bit name description CPOL Clock polarity: selects the polarity of the shift clock 1: shift clock is active low.

  • Page 10: Spi Interface

    UM191812 NXP Semiconductors PN544 C2 User Manual 6.2 SPI interface The PN544 is a slave SPI.., The mode used for the clock can be chosen for the phase (CPHA) and the polarity (CPOL). The pin IFSEL0 is used to set CPHA and IFSEL1 is used to set CPOL.

  • Page 11: C Interface

    UM191812 NXP Semiconductors PN544 C2 User Manual 6.3 I C interface The PN544 is an I C slave. To use this interface, an I C address has to be set. The default address of the device is set to binary “0 1 0 1 0 IF1 IF0”. The prefix “0 1 0 1 0” is a fixed value inside PN544.

  • Page 12: Hsu Interface

    UM191812 NXP Semiconductors PN544 C2 User Manual 6.4 HSU interface HSU interface default configuration is: Data bit : 8 bits Parity bit : none Stop bit : 1 bit Baud rate : 115200 bauds Data order : LSB first 7. NXP Logical Link Layer PN544 offers four interfaces using LLC on top of the physical layer.

  • Page 13: Overview On Physical Interfaces

    UM191812 NXP Semiconductors PN544 C2 User Manual 7.1 Overview on physical interfaces Table 5. Physical host Interfaces Overview Communication Half Duplex Full Duplex Full Duplex Full Duplex Flow Clock Generator Host Only Host Only Host and Device (CLF) Only Device...

  • Page 14: Llc On I C, Spi, Uart

    UM191812 NXP Semiconductors PN544 C2 User Manual 7.4 LLC on I C, SPI, UART The link layer of the host protocol is derived from the ETSI SWP specification. The deviations from the ETSI LLC layer are as follows: • CLT protocol is not supported •...

  • Page 15: Chaining Description

    UM191812 NXP Semiconductors PN544 C2 User Manual The LLC Length specifies the length of the frame to follow. The length itself is not counted. The two CRC bytes are counted. The LLC frame is represented as follows: • LLC Length is mandatory (valid range: 03h – 20h) •...
  • Page 16 UM191812 NXP Semiconductors PN544 C2 User Manual Examples of possible usage of CB bit: (1) HCI single frame without chaining Fig 6. HCI packet smaller than maximum packet size (1) The HCI component splits up the content into two different LLC frames. Therefore HCI must perform two “LLC Send ()”...

  • Page 17: Llc Header Description

    UM191812 NXP Semiconductors PN544 C2 User Manual 7.4.3 LLC Header description The LLC Header (called also SHDLC control field) is part of the LLC frame structure defined in the following figure: Fig 8. LLC layer (SHDLC) 7.4.3.1 SHDLC frame types...
  • Page 18 UM191812 NXP Semiconductors PN544 C2 User Manual Where: - N(S): Number of the information frame - N(R): Number of next information frame to receive - TYPE: Type of S-Frame - M: Modifier bits for U-Frame I-Frames coding The functions of the information(I) command and response is to transfer sequentially numbered frames, each containing an information field, which might be empty, across the data link.

  • Page 19: Rset Frame

    UM191812 NXP Semiconductors PN544 C2 User Manual U-Frames coding The unnumbered (U) format commands and responses are used to extend the number of data link control functions. The unnumbered format frames have 5 modifier bits which allow for up to 32 additional commands and responses. Only a subset of the HDLC...
  • Page 20 UM191812 NXP Semiconductors PN544 C2 User Manual (1) U RSET frame (with 115200 baud rate for HSU) Fig 10. LLC RSET frame example Another example of complete LLC frame: (1) U RSET frame (without HSU baud rate setup) Fig 11. Recommended RSET frame It is recommended to use the frame with no baud rate indicator if the baud rate is not changed.

  • Page 21: Baud Rate Change (Hsu)

    UM191812 NXP Semiconductors PN544 C2 User Manual 7.4.3.4 Baud rate change (HSU) Additionally to the window size and the endpoint capabilities another optional parameter is introduced on the Host interface. This parameter identifies the baud rate used for the HSU interface. The frame on the host side looks now as follows: (1) 2 ≤...
  • Page 22 UM191812 NXP Semiconductors PN544 C2 User Manual Byte coding of optional HSU baud rate: 0x00 9 600 baud 0x01 0x02 28 800 baud 0x03 0x04 0x05 115 200 baud 0x06 230 400 baud 0x07 460 800 baud 0x08 A baud rate change is always initiated by the host. The flow is as follows:...

  • Page 23: Crc Description

    UM191812 NXP Semiconductors PN544 C2 User Manual Example of change baud rate LLC frame Change baud rate to 9600 (00h) Fig 14. example of change baud rate LLC frame 7.4.4 CRC description The detection of errors in a frame is based on the standard CRC-16 defined in [2]. The CRC polynomial is: Its initial value is 0xFFFF.

  • Page 24: Error Detection And Error Handling

    UM191812 NXP Semiconductors PN544 C2 User Manual 7.4.5 Error Detection and Error Handling 7.4.5.1 Inter-frame-character timeout PN544 measures the time between characters within a frame. If the time exceeds the timer T , PN544 considers the frame invalid. The error handling depends on the...

  • Page 25: Guard Host Timeout

    UM191812 NXP Semiconductors PN544 C2 User Manual 7.4.5.2 Guard Host Timeout This timeout defines the maximum time the Host has to acknowledge a frame received. When timeout is reached, PN544 resends the frame. It is used with HSU interface. (1) T: Guard Timeout Host Fig 17.

  • Page 26: Hsu

    UM191812 NXP Semiconductors PN544 C2 User Manual 7.4.6 HSU All communication is performed via RX and TX. Data may be sent or received at any point in time and could overlap (full duplex). The interrupt pin will notify that is being sent.

  • Page 27: Example: Full Duplex Transfer

    UM191812 NXP Semiconductors PN544 C2 User Manual Fig 19. Sample transfer PN544 to Host 7.4.6.3 Example: Full Duplex Transfer PN544 is capable of receiving and transmitting frames at the same time. The host shall be able to handle this situation as well. The frames shall be considered as completely independent.

  • Page 28: I2C

    UM191812 NXP Semiconductors PN544 C2 User Manual 7.4.7 PN544 performs its I C communication over SDA and SCL. The bit rate is given by the master (= host). The default address of the device is set to binary “0 1 0 1 0 IF1 IF0” (the prefix “0 1 0 1 0”...

  • Page 29: Example: Communication From Slave To Master (Pn544 To Host)

    UM191812 NXP Semiconductors PN544 C2 User Manual : inter-character timeout Fig 21. Sample I C Host to PN544 Communication 7.4.7.2 Example: Communication from Slave to Master (PN544 to Host) The PN544 shall notify via the IRQ line that it wants to transmit data. The host shall now start to address the PN544 and shall set the direction to READ.

  • Page 30: Spi

    UM191812 NXP Semiconductors PN544 C2 User Manual Fig 23. I C PN544 to Host Split Transfer 7.4.8 SPI The PN544 performs its communication by using the signals NSS, MISO, MOSI, SCK. PN544 only acts as slave; hence it only consumes but never drives the signals NSS, MOSI and SCK.

  • Page 31: Communication From Slave To Master (Pn544 To Host)

    UM191812 NXP Semiconductors PN544 C2 User Manual Frame Transfer: Host -> PN544 MOSI Host sends the length of the frame MISO PN544 does not have anything to send, therefore it applies zeros Fig 24. Sample SPI Host to PN544 Transfer 7.4.8.2 Communication from Slave to Master (PN544 to Host)

  • Page 32: Duplex Communication

    UM191812 NXP Semiconductors PN544 C2 User Manual 7.4.8.3 Duplex Communication The PN544 is capable of receiving and sending data at the same time. This situation can be recognized when the other channel is conveying a non zero value. As soon as a byte is arriving which has a value greater than 0, it shall be handled as a regular frame and shall therefore handle this byte as length information.

  • Page 33: Etsi Host Controller Interface Compliancy

    UM191812 NXP Semiconductors PN544 C2 User Manual 8. ETSI Host Controller Interface Compliancy This chapter describes the functional interface provided by PN544. This API implements the part of ETSI HCI specification [1] concerning the CLF. It handles the HCI Network management and defines how to control the CLF to act as Reader or Card emulation.
  • Page 34 UM191812 NXP Semiconductors PN544 C2 User Manual Table 12. HCI Gate Identity Management Gate Identity Management Status No specific command for this gate Table 13. HCI Gate Loopback Gate Loop-Back Status EVT_POST_DATA Supported (fragmented message supported up to 255 bytes) Table 14.
  • Page 35 UM191812 NXP Semiconductors PN544 C2 User Manual Gate Card Emulation Type A Status EVT_FIELD_OFF Supported Table 17. HCI Gate Card Emulation B Gate Card Emulation Type B Status EVT_SEND_DATA Supported in emission and reception (fragmented message supported up to 255 data...

  • Page 36: Etsi Hci Registries Supported

    UM191812 NXP Semiconductors PN544 C2 User Manual 8.2 ETSI HCI Registries Supported To have more details on the following registries, please refer to the HCI specification [1]. Table 19. HCI Gate Administration Gate Administration Status SESSION_IDENTITY Supported MAX_PIPE Supported WHITELIST...
  • Page 37 UM191812 NXP Semiconductors PN544 C2 User Manual Table 23. HCI Gate Reader A Gate Reader A Status Supported ATQA Supported APPLICATION_DATA Supported Supported FWI, SFGT Supported DATARATE_MAX Supported Table 24. HCI Gate Reader B Gate Reader B Status PUPI Supported...
  • Page 38 UM191812 NXP Semiconductors PN544 C2 User Manual Table 26. HCI Gate Emulation B Gate Card Emulation Type B Status MODE Supported PUPI Supported Supported ATQB Supported Supported HIGHER_LAYER_RESPONSE (maximum size of 31 bytes) DATARATE_MAX Supported 191812 All information provided in this document is subject to legal disclaimers.

  • Page 39: Nxp Host Controller Interface

    UM191812 NXP Semiconductors PN544 C2 User Manual 9. NXP Host Controller Interface PN544 provides proprietary gates to enhance the HCI feature set given in [1] . Here is a description of them. This is the block named “PN544 HCI” in “Fig 1 System Overview”.

  • Page 40: Initialization & Default Mode Of Pn544

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.2 Initialization & Default mode of PN544 This chapter describes the PN544 setup at boot level, and the different steps to perform the initialization. The following chapters describe the pipes that have to be created, opened or closed, and how it has to be managed by the Host Controller.
  • Page 41 UM191812 NXP Semiconductors PN544 C2 User Manual • RF configuration (Card RF gate, RF Reader Gates). From NXP HCI proprietary: • System management, • SWP, • Polling Loop, • NFC-WI, • MIFARE Reader (Integrated to generic Reader Gates), • FeliCa Reader, •...
  • Page 42 UM191812 NXP Semiconductors PN544 C2 User Manual Here is an example of Type A Reader RF gate initialization: PN544 HOST ADM_CREATE_PIPE Gate Gate ( READER RF GATE A ID = ‘0x13’) ANY_OK Gate Gate ( PipeID ) HOST must save the...
  • Page 43 UM191812 NXP Semiconductors PN544 C2 User Manual The first PN544 initialization can be performed as follows: PN544 HOST mandatory PN544 first startup optional ANY_OPEN_PIPE Gate Gate The Administration Gate ANY_OK hast a static PipeID ‘0x01’ Gate Gate Administration Gate, Pipe Open*...

  • Page 44: After First Setup - Default State

    UM191812 NXP Semiconductors PN544 C2 User Manual As soon as Pipes are created and opened, PN544 will save this setup in EEPROM (Pipe states are persistent). It means that at the next PN544 restart (VEN reset); PN544 will stay in this mode also called ‘default mode’.

  • Page 45: System Management

    UM191812 NXP Semiconductors PN544 C2 User Manual Fig 30. After First Setup – Default state 9.3 System Management This chapter describes the System Management of PN544. The host could manage the management of the system through a dedicated gate ‘PN544Mgt’.
  • Page 46 UM191812 NXP Semiconductors PN544 C2 User Manual mode is left as soon as PN544 receive any data from the host or in case of PN544 Reset. • Receive information about PN544 behaviour. • Access PN544 configuration (EEDATA, HW registers) via Read & Write commands.
  • Page 47 UM191812 NXP Semiconductors PN544 C2 User Manual The NXP_SELF_TEST_ANTENNA command has the following parameters: Table 29. Antenna Self test Command Description Length BoundaryConditions 4 Boundary conditions used during Antenna Self test: - 1st one relates to RF sensitivity on TX1.
  • Page 48 UM191812 NXP Semiconductors PN544 C2 User Manual The response to the NXP_SELF_TEST_SWP command is as follows: Table 31. SWP Self test Command Response Description Length ErrorCode PmuVccStatus 1 ErrorCode field indicates which condition has made the test failing: 0x00: No failure...
  • Page 49 UM191812 NXP Semiconductors PN544 C2 User Manual Value Description 0x02 Type F 0x03 No modulation others RFU Baud rate indicates the RF modulation bitrates to be used for the test Table 35. PRBS test Command Bitrate Parameter Value Description 0x00...
  • Page 50 UM191812 NXP Semiconductors PN544 C2 User Manual Value Event Description ‘12’ NXP_EVT_INFO_EXT_RF_FIELD This event is sent to the host to inform about external RF field presence. This notification is sent, if at least one Card Emulation is enabled. ‘13’ NXP_EVT_INFO_MEM_VIOLATION This event is sent to the host to inform about PN544 internal memory violation.
  • Page 51 UM191812 NXP Semiconductors PN544 C2 User Manual The NXP_EVT_INFO_EXT_RF_FIELD event has the following parameter: Table 39. EXT_RF_FIELD Event Description Length Presence Presence field indicates current external RF field presence - 0x00: indicates no RF field present - 0x01: indicates RF field present The NXP_EVT_INFO_TEMP_OVERHEAT event has the following parameter: Table 40.
  • Page 52 UM191812 NXP Semiconductors PN544 C2 User Manual The NXP_READ command has the following parameters: Table 42. Read Command Description Length Address Address contain the memory address to be read The response to the NXP_READ command is as follows: Table 43.
  • Page 53 UM191812 NXP Semiconductors PN544 C2 User Manual Table 46. System Management Registry Name Access Comment Length Default Rights 0x00 ‘02’ NXP_INFO_NOTIFICATION Indicates on information s the host wants to be notified of. (EE) Information event Overcurrent PmuVcc switch External RF field...

  • Page 54: Default Mode To Standby Mode

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.3.1 Default mode to Standby mode When PN544 is not used (No RF communication, no Host communication, no UICC communication), it stays in a “default mode” which can be set by the PWR_STATUS EEPROM area.

  • Page 55: Host Link Wake-Up From Standby Mode

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.3.2 Host Link Wake-up from Standby mode When PN544 is in Standby mode, it is still possible to communicate with through the Host link (HSU, I2C or SPI). However it can happen that PN544 will not answer to the first frame sent. Host needs to re-send the frame according to SHDLC definition (See [2]) T1: Acknowledge time, T1 ≤5ms.

  • Page 56: Information Notification

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.3.3 Information notification This feature is mainly for debug/trace purpose to inform Host Controller that: 1. An OverCurrent occurs. 2. PMUVCC has changed. 3. External RF Field is present. This feature is optional for Host Controller.

  • Page 57: Clock Management

    UM191812 NXP Semiconductors PN544 C2 User Manual • If Vbat<VbatCritical, PN544 is able to supply Secure Element and switch automatically in ‘Power by the field’ (No battery resources needed). 9.4 Clock Management This chapter describes the clock setup, the clock request and acknowledge in the case of a clock provided by the system (Baseband, PMU, Host Controller …) to the PN544.

  • Page 58: Use Of System Clock

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.4.1.2 Use of system clock To setup the use of the system clock, the following EEPROM area has to be set: Table 50. Setting for external oscillator Name Length Value(s) Comments (bytes) HW_Conf Bit7 set to 0.

  • Page 59: Clock Request Using Gpio Pin

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.4.2.1 Clock Request using GPIO pin The following figures show the 2 possible use of GPIO pin for Clock Request (GPIO2) & acknowledge (GPIO1): CLKREQ System Clock CLKACK Fig 32. Clock request with CLKREQ pin, acknowledge with CLCKACK pin Fig 33.

  • Page 60: Clock Request Using Hci Event

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.4.2.2 Clock Request using HCI Event The following figures show the 2 possible use of HCI Event for Clock Request & acknowledge: Fig 34. Clock request with HCI Event, acknowledge with HCI Event Fig 35.

  • Page 61: No Clock Request

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.4.3.1 No clock request In the case of a clock always provided by the system, the request/acknowledge mechanism is not needed. To setup such a configuration, the following EEPROM area has to be set (See ’...

  • Page 62: Request Through Nxp_Evt_Clk_Request

    UM191812 NXP Semiconductors PN544 C2 User Manual The request & release mechanism using CLKREQ pin is described in the following figure: Fig 36. Clock request with CLKREQ pin Step1: As soon as the PN544 needs system clock, it puts the CLKREQ level to high.

  • Page 63: Clock Acknowledge

    UM191812 NXP Semiconductors PN544 C2 User Manual Fig 37. Clock request with HCI event Step1: As soon as the PN544 needs system clock, it sends the HCI event NXP_EVT_CLK_REQUEST (with status byte set to ‘0x00’ for Clock request) to the Host controller.

  • Page 64: Acknowledge Through Clkack Pin

    UM191812 NXP Semiconductors PN544 C2 User Manual The acknowledge mechanism using timeout is described in the following figure: Fig 38. Clock acknowledge with timeout Step1: PN544 request the clock from the system (for clock request, see previous chapter: ‘Clock Request & Release’, Fig 33 & Fig 35).

  • Page 65: Acknowledge Through Nxp_Evt_Clk_Ack

    UM191812 NXP Semiconductors PN544 C2 User Manual The acknowledge mechanism using CLKACK pin is described in the following figure: Fig 39. Clock acknowledge with CLKACK pin Step1: PN544 request the clock from the system (for clock request, see previous chapter: ‘Clock Request & Release’).
  • Page 66 UM191812 NXP Semiconductors PN544 C2 User Manual The acknowledge mechanism using HCI event is described in the following figure: Host Link NXP_EVT_CLK_ACK (I2C, SPI, ..) System Clock Fig 40. Clock acknowledge with HCI event Step1: PN544 request the clock from the system (for clock request, see previous chapter: ‘Clock Request &...

  • Page 67: Clk Request In Nfc Active Target Mode

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.4.5 CLK request in NFC active target mode In NFC active reader mode the clock request usage is illustrated: (1) ATR_RES has to be in-time to serve an ATR_REQ Fig 41. NFC CLK request in NFC active target mode...

  • Page 68: Swp

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.5 SWP The host can manage the secure element connected over SWP through a dedicated gate “SWPMgt”. Table 58. SWP Management Gate Gate SwpMgt gate ‘A0’ Using this gate the host is able to: •...
  • Page 69 UM191812 NXP Semiconductors PN544 C2 User Manual • Mode indicates the mode to switch to: Table 61. SWP Switch Mode Event Parameters Value Description 0x00 Off (deactivated) 0x01 Default mode 0x02 On (activated) others RFU Table 62. SWP Registry Name...
  • Page 70 UM191812 NXP Semiconductors PN544 C2 User Manual Name Access Comment Length Default Rights 0x00 4. ‘03’ 5. NXP_SWP_PROTECTION_MODE 6. RW 8. Indicates if the protected mode is enabled (see below a description of 7. (Reg the protection mode feature) : 9.

  • Page 71: Configuration Of Swp Link

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.5.1 Configuration of SWP link The SWP registry is stored in EEPROM (except NXP_SWP_STATUS (Id ‘02’), which is a “read only” parameter stored in RAM). 9.5.1.1 Enabling SWP link By default the SWP link is disabled. The host can enable it using NXP_SWP_DEFAULTMODE (Id ‘01’) of the registry.

  • Page 72: Reading Swp Status

    UM191812 NXP Semiconductors PN544 C2 User Manual Note: If Host wants to enable these registries change, it has to force the UICC re- initialization, by setting the UICC_AdminSessionId EEPROM area to its default value. Host has also to take care of UICC power reset to ensure the settings change. This command has to be sent before NXP_SWP_DEFAULTMODE use for enabling SWP link.
  • Page 73 UM191812 NXP Semiconductors PN544 C2 User Manual UICC Type A Card Emulation Example Fig 43. UICC Type A Card Emulation Example 191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.

  • Page 74: Reader Use Case

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.5.2.2 Reader use case The host shall set the parameters of the SwpMgt gate as described in the previous paragraph. The UICC shall behave as described in HCI specification. • The UICC creates and open the pipe between the reader gates and reader RF gates.
  • Page 75 UM191812 NXP Semiconductors PN544 C2 User Manual UICC Reader Type A Example Fig 44. UICC Type A Reader Example 191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. User Manual Rev.
  • Page 76 UM191812 NXP Semiconductors PN544 C2 User Manual SWP Protected Mode Protected mode is a feature which intends to be used by the host to block any transaction between an external RF reader and the UICC. Then receiving the notification of the UICC activation, the host can authorize UICC access through SWP.

  • Page 77: Uicc Dependency For Paypass Compliance

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.5.3 UICC dependency for PAYPASS Compliance In order to fit with PAYPASS requirements, the following registry has to be correctly set by UICC: Table 63. Type A Card RF Registry for PAYPASS Name...

  • Page 78: Polling Loop

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6 Polling Loop The host could manage the polling loop mechanism through a dedicated gate “PollingLoopMgt”. Table 65. Polling Loop Management Gate Gate PollingLoopMgt gate ‘94’ Using this gate the host is able to:...
  • Page 79 UM191812 NXP Semiconductors PN544 C2 User Manual Table 68. Status values Value Description 0x00 Clock request 0x01 Clock release Others The NXP_EVT_ACTIVATE_RDPHASE event has parameters as follows: Table 69. NXP_EVT_ACTIVATE_RDPHASE Event Parameters Description Length Technology 1 • Technology indicates the Reader phase requested Table 70.
  • Page 80 UM191812 NXP Semiconductors PN544 C2 User Manual Table 71. Polling Loop Registry Name Access Comment Length Default Rights ‘06’ NXP_PL_RDPHASES 0x00 Indicates the status of the phases: (Reg) Technology Detection type A Detection type B Detection type F 212 Detection type F 424...

  • Page 81: Clock

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6.1 Clock Refer to ‘Clock Management 9.4’ paragraph for details. It includes an explanation on the usage of the events: • NXP_EVT_CLK_ACK • NXP_EVT_CLK_REQUEST And an explanation on the usage of the EEPROM data area: •...

  • Page 82: Pollingloop Management

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6.2 PollingLoop Management At start up, the PN544 is in a “default” mode (The Power level of this mode is set according to PWR_STATUS EEPROM area value). It waits for a command from the host, or from an external reader if the RF level detector has been enabled (in that case Refer to SWP &...

  • Page 83: Detection Guard Time

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6.2.1 Detection Guard Time Polling Loop timings for detection are set as follows: Fig 47. Polling Loop Timings All Guard Times are set with respect to the technology specification. However, these timings can be changed (see ‘0’ chapter).

  • Page 84: Activation Timeout For Nfc-Ip1 Initiator

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6.2.2 Activation Timeout for NFC-IP1 Initiator When NFC-IP1 Initiator mode is enabled, PN544 is not able to detect absence of NFC- IP1 Target. After the ATR_REQ has been sent, it waits the ‘NFCI_ATR timeout’ for ATR_RES before starting next phase of Polling Loop.

  • Page 85: Nxp_Pl_Rdphases Parameter

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6.2.4 NXP_PL_RDPHASES parameter To setup and launch the Polling Loop mechanism, the host has to use the NXP_PL_RDPHASES registry. This registry allows choosing the desired type of communication. NXP_PL_RDPHASES registry contains: • One bit that enables/disables the “Pause” mode (PN544 is in a non active state). To enable the Card Emulation mode (i.e.

  • Page 86: Nxp_Pl_Emulation, Nxp_Pl_Pause

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6.2.5 NXP_PL_EMULATION, NXP_PL_PAUSE parameters NXP_PL_EMULATION and NXP_PL_PAUSE timings have sense only when a reader sequence has been started by NXP_PL_RDPHASES. As the Polling Loop is running, Emulation & Pause modes have a different meaning: Emulation mode means card emulation mode (either from Host or UICC or SmartMX) as well as NFC Target.
  • Page 87 UM191812 NXP Semiconductors PN544 C2 User Manual Fig 49. Emulation Phase only Note: From a functional point of view, this mode is equivalent to the previous mode: ‘No phase started’. One Pause phase only: If only a Pause phase is enabled, PN544 can stay in an inactive mode (no Reader action, no Card Emulation).
  • Page 88 UM191812 NXP Semiconductors PN544 C2 User Manual One reader phase, with one RF type only: If a reader phase is started, the duration of it is fixed (depending on RF type). Then PN544 waits, during NXP_PL_PAUSE time. Then it starts again the reader phase, and so on (until a card is detected).
  • Page 89 UM191812 NXP Semiconductors PN544 C2 User Manual PN544 HOST Pause Phase = 200ms NXP_PL_PAUSE Polling Polling Loop Loop Gate Gate Pause Pause Phase Duration = 0x1046 = 200 ms EVT_READER_REQUESTED Detection Type A Type A Reader Reader Type A Gate...

  • Page 90: Nxp_Evt_Activate_Rdphase

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6.2.6 NXP_EVT_ACTIVATE_RDPHASE, NXP_EVT_DEACTIVATE_RDPHASE events These events are only used in case of UICC wants to act as a reader. When the UICC wants to start a reader RF gate, the PN544 sends a NXP_EVT_ACTIVATE_RDPHASE to the host.

  • Page 91: Nxp_Evt_Deactivate_Rdphase Events

    UM191812 NXP Semiconductors PN544 C2 User Manual At the end of the reader operation, PN544 can inform the host by sending a NXP_EVT_DEACTIVATE_RDPHASE. The host can decide to stop the reader request by sending NXP_PL_RDPHASES and disable the RF technology detection.

  • Page 92: Example Of Polling Loop

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6.3 Example of Polling Loop Here is an example of Polling Loop launch with an ISO14443 type A card detected: Fig 56. Polling Loop with ISO14443 Type A card detected Notes: If the Host wants to restart the Polling Loop, it has to send the EVT_READER_REQUESTED event.

  • Page 93: Nfc-Ip1 In Polling Loop

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.6.4 NFC-IP1 in Polling Loop If NFC-IP1 Initiator gate is setup (Pipe Opened, and NXP_NFCI_MODE registry set with at least one baudrate). The NFC-IP1 Initiator mode will be executed during the ‘Reader phase’ of the Polling Loop.

  • Page 94: Type B, 212Kbps And 424Kbps Passive Initiator And Active Initiator/Target

    UM191812 NXP Semiconductors PN544 C2 User Manual Fig 57. Card Emulation RF step 9.6.6.2 Type B, 212kbps and 424kbps Passive Initiator and Active Initiator/Target When TVDD is not configured to 2.7V, for VBAT higher than: • TVDD configured + 0.5V when TXLDO offset is used •...

  • Page 95: Nfc-Wi

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.7 NFC-WI The host could manage the secure element connected over NFC-WI through a dedicated gate “NfcWiMgt”. Table 72. NfcWiMgt gate Gate NfcWiMgt gate ‘A1’ Using this gate the host is able to: - Manage the secure element connected over NFC-WI Table 73.
  • Page 96 UM191812 NXP Semiconductors PN544 C2 User Manual • Mode indicates the mode to switch to Table 75. Mode Description Value Description 0x00 ‘Wired mode’ 0x01 ‘Default mode’ 0x02 ‘Virtual mode’ 0x03 ‘Off mode’ others RFU Note: ‘Default mode’ is the mode set by NXP_SE_DEFAULTMODE registry.
  • Page 97 UM191812 NXP Semiconductors PN544 C2 User Manual There are 3 possible configurations for the NFC-WI Secure Element: • Off mode is used when no communication with the Secure Element is needed, either from the host controller or from an external PCD.
  • Page 98 UM191812 NXP Semiconductors PN544 C2 User Manual • Virtual mode, Secure Element is seen as a real contact less card. HOST NFC-WI NFC-WI application Virtual mode NFC-WI application gate I2C or SPI or HSU NFC-WI gate NFC-WI NFC-WI Secure Element...

  • Page 99: Mifare Pcd

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.8 MIFARE PCD PN544 offers MIFARE PCD functionality through the generic “Type A reader RF gate” of the ETSI HCI specification [1]. Activation is as defined in the specification, and then the MIFARE card (MIFARE UltraLight & MIFARE 1K/4K) can be accessed with the following NXP proprietary command of the “Type A RF reader gate”...

  • Page 100: Nxp_Mifare Commands And Registry

    UM191812 NXP Semiconductors PN544 C2 User Manual The response to this command is as follows: Table 79. NXP_MIFARE_RAW Response parameters Description Length Response code 1 Status Data • Response code possible values: any of the ETSI HCI generic response code.
  • Page 101 UM191812 NXP Semiconductors PN544 C2 User Manual Table 82. Description Value Description 0x60 Authentication A 0x61 Authentication B 0x30 16 bytes reading 0xA0 16 bytes writing 0xA2 4 bytes writing 0xC1 Incrementation 0xC0 Decrementation 0xB0 Transfer 0xC2 Restore 0x38 Read sector...
  • Page 102 UM191812 NXP Semiconductors PN544 C2 User Manual The response to this command is as follows: Table 83. NXP_MIFARE_CMD Response parameters Description Length Response code 1 Data • Response code possible values: any of the ETSI HCI generic response code and in case of error: Table 84.
  • Page 103 UM191812 NXP Semiconductors PN544 C2 User Manual Table 87. MIFARE Authenticate command – Authentication type value Value Description 0x00 Use key A 0x01 Use key B The response to the MIFARE Authenticate command is as follows: Table 88. NXP_MIFARE_AUTHENTICATE_CMD Command Response...
  • Page 104 UM191812 NXP Semiconductors PN544 C2 User Manual Table 91. MIFARE Registry Name Access Comment Length Default Rights ‘10’ NXP_AUTO_ACTIVATION RW If set to 0, the activation procedure will stop after 0x01 Select (SAK has been received). The host could (EE)
  • Page 105 UM191812 NXP Semiconductors PN544 C2 User Manual mandatory MIFARE ® 1K/4K Reader (from the host) example optional HOST PN544 RF exchanges (One arrow does NOT represent one RF request) ADM_CREATE_PIPE ADM Gate ADM Gate HOST ANY_OPEN_PIPE Type A Type A RF...
  • Page 106 UM191812 NXP Semiconductors PN544 C2 User Manual Examples: for a MIFARE 1K (all values are in hex) • Authentication example : • 60 02 E2 3F B8 1E FF FF FF FF FF FF => authenticate using the keys FF FF FF FF FF FF (value by default for a new card) to the address 02 with UID number E2 3F B8 1E •...

  • Page 107: Felica Reader

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.9 FeliCa Reader PN544 offers FeliCa reader functionality through the generic “Reader RF gates” features of the ETSI HCI specification. This is done with the following proprietary gate: Table 92. Type F Reader RF gate Gate Type F reader RF gate ‘14’...
  • Page 108 UM191812 NXP Semiconductors PN544 C2 User Manual The response to the NXP_FELICA_RAW command is as follows: FeliCa Table 95. Raw Response parameters Description Length Status Data • Status: bits b0 to b2 indicate information on valid bits in the last data byte (value 0 indicates all are valid, from 1 to 7 it indicated the number of valid bits.
  • Page 109 UM191812 NXP Semiconductors PN544 C2 User Manual NbrOfServices Service Code List NbrOfBlocks Block List 1 byte (2 * NbrOfServices) bytes 1 byte (2 * NbrOfBlocks) bytes − Update command: NbrOfServices Service Code List NbrofBlocks Block List Block Data 1 byte...

  • Page 110: Jewel/Topaz Reader

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.10 Jewel/Topaz Reader PN544 offers Jewel/Topaz reader functionality through the generic “Reader RF gates” features of the ETSI HCI specification. This is done with the following proprietary gate: Table 101. Jewel reader RF gate Gate Jewel reader RF gate ‘15’...
  • Page 111 UM191812 NXP Semiconductors PN544 C2 User Manual Value Description Data Byte 1 : address 0x01 Read1 Byte 2 : 0x00 Byte 3..6 : card ID 0x02 Read4 Byte 1 : address Byte 1 : address 0x03 Read8 Byte 2..9 : 0x00 Byte 9..12 : card ID...
  • Page 112 UM191812 NXP Semiconductors PN544 C2 User Manual Table 105. Jewel Command Description For NDEF Card (bit 4 of HRO = 1) Value Description Data Byte 1..2 : 0x00 0x00 ReadALL Byte 3..6 : card ID Byte 1 : address 0x01...

  • Page 113: Iso15693

    UM191812 NXP Semiconductors PN544 C2 User Manual The response to the NXP_JEWEL_RAW_CMD command is as follow: Table 106. Jewel Raw Command Response Description Length Data • Data contain the data read, in case of write command N=0. Discovered tag information (UID, Size, HR0 …) can be retrieved using the NXP_JEWEL_RAW_CMD with Jewel “RID”...
  • Page 114 UM191812 NXP Semiconductors PN544 C2 User Manual The NXP_ISO15693_CMD command has the following parameters: Table 109. Reader ISO15693 Command arameters Description Length Payload • Payload defines general request content as defined in ISO15693-3 specification: • • • • Flags Command code...

  • Page 115: Nfcip-1

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.12 NFCIP-1 PN544 offers Peer to Peer functionality based on NFCIP-1 protocol through the two following proprietary gates: Table 112. NFC-IP1 gate Gate NFCIP1 Initiator RF gate ‘30’ NFCIP1 Target RF gate ‘31’...
  • Page 116 UM191812 NXP Semiconductors PN544 C2 User Manual Value Event Description ‘05’ NXP_EVT_NFC_CONTINUE_MI This event is sent to the host to indicate the remote peer acknowledged the previous Meta-chained packet and then the host can send the next one. The NXP_EVT_NFC_ACTIVATED event has the following parameter: Table 114.
  • Page 117 UM191812 NXP Semiconductors PN544 C2 User Manual Value Description 0x01 RF error others RFU • MI indicates Multiple Information chaining information (activated if set to 1). • Data which are received from the peer (in case of RF error, data length is null) NFCIP-1 RF gates use the same mechanism as ETSI HCI “Reader RF gate”...

  • Page 118: Initiator

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.12.1 Initiator To start discovering a remote NFC target, the host shall send an ETSI HCI generic event “EVT_READER_REQUESTED”. When a remote NFC target has been activated, host receives the proprietary event “NXP_EVT_NFC_ACTIVATED”. Then the host can exchange data with the remote peer using event “NXP_EVT_NFC_SND_DATA”...
  • Page 119 UM191812 NXP Semiconductors PN544 C2 User Manual HOST PN544 PN544 Initialization NFC-IP1 Initialization & activation performed External NFC-IP1 Target NXP_EVT_NFC_SND_DATA (MI=1) NFC-IP1 NFC-IP1 Initiator Initiator Gate Gate Send the data in NFC-IP1 protocol NXP_EVT_NFC_CONTINUE_MI NFC-IP1 NFC-IP1 Initiator Initiator Gate Gate...
  • Page 120 UM191812 NXP Semiconductors PN544 C2 User Manual Value Command Description ’13’ NXP_NFCI_CONTINUE_ACTIVATION The host sends this command to allow NFCIP-1 activation when a NFC target has been discovered in Type A Reader RF gate or type F Reader RF gate.
  • Page 121 UM191812 NXP Semiconductors PN544 C2 User Manual HOST PN544 PN544 Initialization NFC-IP1 & Reader TypeA External NFC-IP1 Target Type A Type A EVT_TARGET_DISCOVERED Reader Reader Gate Gate ANY_GET_PARAMETER ( SAK ) Type A Type A Reader Reader Gate SAK == NFC-IP1 Target...
  • Page 122 UM191812 NXP Semiconductors PN544 C2 User Manual Table 119. NFC-IP1 Initiator Registry Name Access Comment Length Default Rights Supported NFCIP-1 Modes. ‘01’ NXP_NFCI_MODE 0x00 (EE) This value shall be interpreted as a bit mask: Mode 106kbit/s passive 212kbit/s passive 424kbit/s passive...
  • Page 123 UM191812 NXP Semiconductors PN544 C2 User Manual Name Access Comment Length Default Rights ‘04’ NXP_NFCI_BRS 0x00 Specifies the bit rates to be used for DEP exchanges: (EE) - Bits 0 to 2: Target to initiator - Bits 3 to 5: Initiator to target Bit rate is coded as follow: 0x00 ->...
  • Page 124 UM191812 NXP Semiconductors PN544 C2 User Manual Name Access Comment Length Default Rights ‘0C’ NXP_NFCI_PARAM 0x00 Contains the current parameters of the NFCIP-1 link when communication has (RAM) been set. - bits 0 to 2: datarate Target to Initiator - bits 3 to 5: datarate Initiator to Target 0 ->...

  • Page 125: Target

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.12.2 Target When a remote NFC initiator has activated the local NFC target handled in the PN544, the host receives the proprietary event “NXP_EVT_NFC_ACTIVATED”. Then the host can exchange data with the remote peer receiving event “NXP_EVT_NFC_RCV_DATA”...
  • Page 126 UM191812 NXP Semiconductors PN544 C2 User Manual HOST PN544 PN544 Initialization NFC-IP1 Activation performed External NFC-IP1 Initiator Receive the data in NFC-IP1 protocol NXP_EVT_NFC_RCV_DATA NFC-IP1 NFC-IP1 Target Target Gate Gate NXP_EVT_NFC_SND_DATA (MI=1) NFC-IP1 NFC-IP1 Target Target Gate Gate Send the data in...
  • Page 127 UM191812 NXP Semiconductors PN544 C2 User Manual The proprietary ‘NFCIP1 Target’ gate has the following registry: Table 120. NFC-IP1 Target Registry Name Access Comment Length Default Rights Supported NFCIP-1 Modes. ‘01’ NXP_NFCT_MODE 0x00 (EE) This value shall be interpreted as a bit...
  • Page 128 UM191812 NXP Semiconductors PN544 C2 User Manual Name Access Comment Length Default Rights ‘0C’ NXP_NFCT_PARAM 0x00 Contains the current parameters of the NFCIP-1 link when communication has (RAM) been set. - bits 0 to 2: datarate Target to Initiator - bits 3 to 5: datarate Initiator to Target 0 ->...

  • Page 129: Reader Rf Gates - Additional Commands

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.13 Reader RF gates – additional commands PN544 implement reader feature defined in ETSI HCI specification. However, it provides the following additional commands: Table 121. Reader RF Additional Commands Value Command Description ’30’...
  • Page 130 UM191812 NXP Semiconductors PN544 C2 User Manual The response to the NXP_WR_ACTIVATE_NEXT command is as follows: Table 122. NXP_WR_ACTIVATE_NEXT Response Description Length Status • Status field indicates if the activation has been successful Table 123. NXP_WR_ACTIVATE_NEXT Response Description Value Description...
  • Page 131 UM191812 NXP Semiconductors PN544 C2 User Manual The response to the NXP_WR_DISPATCH_TO_UICC command is as follows: Table 126. NXP_WR_DISPATCH_TO_UICC Command Response Description Length ErrorCode 1 • ErrorCode field indicates reason of the dispatch failure test (optional: ErrorCode field is only present in case of failure) •...

  • Page 132: Type A Picc

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.14 Type A PICC This paragraph explains in which ways the PN544 can behave like a Type A card. 9.14.1 Type A PICC over NFC WI (SMX as a Type A card) The Type A card emulation can be located in the secure element connected to PN544 over NFC WI link.

  • Page 133: Type A Pcd

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.15 Type A PCD This paragraph explains how to realize a PN544 and its host(s) can be a Type A reader. 9.15.1 Type A PCD over SWP (UICC as a Type A reader) The UICC can run a Type A reader application, as described in HCI specification.
  • Page 134 UM191812 NXP Semiconductors PN544 C2 User Manual PN544 HOST NXP_PL_RDPHASES Polling Loop Polling Loop Gate Gate to allow Reader type A External ISO14443A External ISO14443A Only a reader phase is shown here card in the field card in the field...
  • Page 135 UM191812 NXP Semiconductors PN544 C2 User Manual To reactivate a chosen card, its UID is used, in NXP_WR_ACTIVATE_ID command. Fig 70. Host as a Type A reader, two Type A cards in the field 191812 All information provided in this document is subject to legal disclaimers.

  • Page 136: Presence Check Of Iso14443A Card: Use Nxp_Wr_Prescheck

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.15.3.2 Presence check of ISO14443A card: use NXP_WR_PRESCHECK When the reader wants to check the presence of the ISO14443 card in the field, it shall send the command NXP_WR_PRESCHECK. In ISO14443, the PN544 will send a R(NAK) block to the card.
  • Page 137 UM191812 NXP Semiconductors PN544 C2 User Manual Both the host and the UICC must configure their pipes as defined in HCI specification. The host must in addition set some NXP proprietary parameters to enable the UICC as a reader (refer to SWP paragraph). The next figure shows those exchanges between the host, the PN544 and the UICC.
  • Page 138 UM191812 NXP Semiconductors PN544 C2 User Manual Fig 73. Communication with a card 191812 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. User Manual Rev. 1.2 — 2010-06-16 138 of 172...

  • Page 139: Type B Picc

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.16 Type B PICC This paragraph explains in which ways the PN544 can behave like a Type B card. 9.16.1 Type B PICC over SWP (UICC as a Type B card) The Type B card emulation can be located in the UICC connected to PN544 over SWP link.

  • Page 140: Type B Pcd

    UM191812 NXP Semiconductors PN544 C2 User Manual Type B PCD This paragraph explains how to realize a PN544 and its host(s) can be a Type B reader. WARNING: Type B PCD does not support multiple card detection (Anti-collision not supported). Thus only one Type B card can be detected by PN544.

  • Page 141: Gpio(S)

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.17 GPIO(s) The host can change the General Purpose Input Output pins configuration • * Either by accessing directly the hardware registers (in that case the configuration will be lost after a power down) •...

  • Page 142: Output Configuration

    UM191812 NXP Semiconductors PN544 C2 User Manual “Temporarily” means that the change is applied directly in the register of the hardware, therefore the new value is immediately applied, but will be lost after power down (at next power up, the EEPROM values will be applied) 9.17.3.1 Output configuration...

  • Page 143: Input Configuration

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.17.3.3 Input configuration To configure permanently GPIO5 in input • Set 0x9893 GPIO_Config_PDIR bit 5 to 0. • Set 0x9899 GPIO_Config_PEN bit 5 to 1. • The value is stored in EEPROM; it will be loaded at next power up of the IC.

  • Page 144: Download

    UM191812 NXP Semiconductors PN544 C2 User Manual To inverse permanently the polarity of a GPIO port, the corresponding bit to 1 in 0x9892 GPIO_Config_PINV register. 9.18 Download This chapter describes the EEPROM download of PN544. The Download mode use a specific protocol (different from LLC/HCI) described in [8].
  • Page 145 UM191812 NXP Semiconductors PN544 C2 User Manual Fig 74. Switch to Download mode Note: WRITE, READ, CHECK & RESET command are part of the Download protocol documented in the dedicated Application Note [8]. WRITE command is mandatory to use, READ & CHECK commands are optional to cross check the consistency of the EEPROM.

  • Page 146: Pn544 Debug Mode

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.19 PN544 Debug Mode This chapter describes the debug functionality of PN544 (i.e. Output signal on GPIO). To setup the PN544 in debug mode, the following register has to be used: Table 129.

  • Page 147: Rf Level Detector

    UM191812 NXP Semiconductors PN544 C2 User Manual On GPIO5, the PN544 System Clock is output, 27.12 MHz. To disable this setup: -1- Perform a Hardware Reset (VEN pin use). -2- Set GPIO7 and GPIO5 direction to their default configuration (depending of application use).
  • Page 148 UM191812 NXP Semiconductors PN544 C2 User Manual -2- Set Debug_Interface to 0x01. For further details on this signal, refer to [11]. To disable this setup: -1- Perform a Hardware Reset (VEN pin use). -2- Set GPIO(s) direction to its default configuration (depending of application use).

  • Page 149: Pn544 Configuration

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.20 PN544 Configuration PN544 can be customized thanks to the data EEPROM. The following settings can be accessed using NXP_READ and NXP_WRITE commands (Refer to ‘PN544 System Management’ chapter). 9.20.1 SWP configuration Table 130.
  • Page 150 UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x9F0A SWP_PBTF_RFLD SWP PowerByTheField RF Level Detector sensitivity: 0x05 Value to be set from 0x00 to 0x07. 0x00: Maximum sensitivity (to detect Low RF field). 0x07: Minimum sensitivity. 0x9ED7 UICC_GateList Registry entry related to the Gate list (IdentityManagement gate) of the Uicc.
  • Page 151 UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x9EE9 0xFF 0x9EEA 0xFF 0x9C02 0x13 SWP_SyncID0 Reference value for checking the UICC identity during ACT SYNC_ID verification sequence (SWP activation). Can be used to inhibit the UICC. 0x9C03...

  • Page 152: Se Configuration

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.20.2 SE configuration ＳＷＰ－ＳＩＭ卡模拟配置 Table 132. SE Configuration in EEPROM Address Name Comment Default 0x9800 0x3F SE_Conf Defines the properties of Secure Elements (UICC and NFC-WI device) -Bit 0 : NFC-WI device connected to PN54x...

  • Page 153: Hw Configuration

    UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x9B4B 0x00 NfcWi_SE_TimeOut_L 9.20.3 HW configuration Table 133. HW configuration in EEPROM Address Name Comment Default 0x9810 HW_Conf 0xBC TX-LDO configuration -Bits 0-1 : TVDD Supply select for TX-LDO 00 ...
  • Page 154 UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x9808 AST-ANT1-ANT2 0xFF Antenna Self Test: default PBF (4 parameter) AST-GSP2 0x27 0x989D Antenna Self Test: GSP for TX2 AST_Current 0x3F 0x989E Antenna Self Test: Current start threshold 0x989F...
  • Page 155 UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x9898 IRQ_Config 0x02 - Bit 5 : 0 ... IRQ logical level is active HIGH (Default value) 1 ... IRQ logical level is active LOW - Other Bits : RFU (keep unchanged)
  • Page 156 UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x9809 FRAC_ClkSel 0x00 Input Clock selection for FracNPLL -00h ... No input clock -01h ... 13.0 MHz -02h ... 19.2 MHz -03h ... 26.0 MHz -04h ... 38.4 MHz -05h ...
  • Page 157 UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x9EAA PWR_STATUS Indicates PN544 power modes used: 0x00 0x00 -> PN544 stays in active bat mode (except when generating RF field) 0x01 -> PN544 goes in standby when possible otherwise stays in active bat mode 0x02 ->...
  • Page 158 UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x98A4 RTOX value to compute RWTINT (See [4]) 0x07 NFCT_RTOX (PN544 timeout will be half as specified) 0x98DE Initiator Activation timeout 0x00 (in 1ms step) NFCI_ATR_TO_MSB (Recommended Max value is 30 ms).
  • Page 159 UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x9F62 Key B of Keyset 3 for MIFARE authenticate command MIF_KEYSET3_KEY_B 0x9F67 0x9F68 Key A of Keyset 4 for MIFARE authenticate command MIF_KEYSET4_KEY_A 0x9F6D Key B of Keyset 4 for MIFARE authenticate command...
  • Page 160 UM191812 NXP Semiconductors PN544 C2 User Manual Address Name Comment Default 0x9F9C FeRd System code LSB 0x9F9E 0x1570 NfcT-RFOFF-TO_MSB In NFC target active, Time the target wait after command reception has been ended and RF OFF before reinitializing. 0x9F9F NfcT-RFOFF-TO_LSB To avoid active target in front of passive reader (in 5.5µs step)

  • Page 161: Rf Configuration

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.20.4 RF configuration Table 134. RF settings in EEPROM Address Name Comment Default 0x9976 ANATXCWGSN - bits 4 to 7: Set_Conductance_NMOS_LoadNoMod in PCD mode 0xFF - Others bits are reserved 0x9977 ANATXCWGSPON Set_Conductance_PMOS_LoadNoMod in PCD mode...

  • Page 162: Pn544 Register Access

    UM191812 NXP Semiconductors PN544 C2 User Manual 9.21 PN544 register access PN544 HW registers can be accessed using NXP_READ and NXP_WRITE commands. 9.21.1 GPIO settings For a detailed description please refer to the ‘GPIO chapter’. Table 135. GPIO register set...

  • Page 163: Practical Approach On Pn544 Hci

    UM191812 NXP Semiconductors PN544 C2 User Manual 10. Practical Approach on PN544 HCI For debug of your system we give a first short idea how to verify your host interface connection of PN544 as well as the validation of your chip itself by reading out the version numbers.

  • Page 164: Pn544 Software & Hardware Version

    UM191812 NXP Semiconductors PN544 C2 User Manual 10.2 PN544 Software & Hardware Version For information, “VERSION_SW”, “VERSION_HW” and “MODEL_ID”, registry entries defined in the ETSI HCI specification indicates PN544 version as follows: VERSION_SW Table 136. description byte byte byte RomLib...

  • Page 165: Pn544 Versioning And Configuration Management

    UM191812 NXP Semiconductors PN544 C2 User Manual In addition to Identity management gate, PN544 provides the following additional registry entry NXP_FULL_VERSION_SW: Table 139. NXP_FULL_VERSION_SW description Name Access Comment Length Default Rights ‘10’ NXP_FULL_VERSION_SW RO Version of the software as followed:...
  • Page 166 11.2 Disclaimers In no event shall NXP Semiconductors, its affiliates or their suppliers be Limited warranty and liability — Information in this document is believed to liable to customer for any special, indirect, consequential, punitive or be accurate and reliable.
  • Page 167 UM191812 NXP Semiconductors PN544 C2 User Manual 12. List of figures Fig 1. System Overview ..........7 Fig 44. UICC Type A Reader Example .......75 Fig 2. SPI interface configuration ......10 Fig 46. Polling Loop Overview........82 Fig 3. I2C interface configuration ......11 Fig 47.
  • Page 168 UM191812 NXP Semiconductors PN544 C2 User Manual 13. List of tables Table 2. Host Interface Selection ........8 Table 69. NXP_EVT_ACTIVATE_RDPHASE Event Parameters............79 Table 3. CPOL / CPHA description .........9 Table 70. Technology Description........79 Table 4. Pin functional description ........9 Table 72. NfcWiMgt gate..........95 Table 5.
  • Page 169 UM191812 NXP Semiconductors PN544 C2 User Manual Table 110. Reader ISO15693 Command Response ..114 Table 111. ISO15693 Registry........114 Table 112. NFC-IP1 gate ..........115 Table 113. NFC-IP1 Events ..........115 Table 114. NFCIP-1 Activated Event ......116 Table 115. NXP_EVT_NFC_SND_DATA Parameters..116 Table 116.

  • Page 170: Table Of Contents

    UM191812 NXP Semiconductors PN544 C2 User Manual 14. Contents ETSI HCI Registries Supported......36 Introduction ............3 NXP Host Controller Interface ......39 PN544 C2..............3 Access Rights NXP HCI Registry .....39 Abbreviations ............4 Initialization & Default mode of PN544 .....40 References ............6 9.2.1 Gates &...
  • Page 171 UM191812 NXP Semiconductors PN544 C2 User Manual Polling Loop .............78 9.15.4 Handling of multiple Type A readers ....136 9.6.1 Clock ..............81 9.16 Type B PICC ..........139 9.6.2 PollingLoop Management ........82 9.16.1 Type B PICC over SWP (UICC as a Type B 9.6.2.1...
  • Page 172 UM191812 NXP Semiconductors PN544 C2 User Manual Legal information ..........166 11.1 Definitions ............166 11.2 Disclaimers.............166 11.3 Licenses ............166 11.4 Patents ............166 11.5 Trademarks ............166 List of figures...........167 List of tables ............168 Contents............170 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'.

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